Abstract is missing.
- Abstraction of word-level linear arithmetic functions from bit-level component descriptionsPallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti. 4-8 [doi]
- Biasing symbolic search by means of dynamic activity profilesGianpiero Cabodi, Paolo Camurati, Stefano Quer. 9-15 [doi]
- A methodology for interfacing open source systemC with a third party softwareLuc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois. 16 [doi]
- Behavioral synthesis with systemCGeorge Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou. 21-25 [doi]
- SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system designRobert Siegmund, Dietmar Müller. 26-33 [doi]
- Embedded tutorial: TRP: integrating embedded test and ATEYervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher. 34-37 [doi]
- Embedded tutorial: current trends in the design of automotive electronic systemsPeter van Staa, Thomas Beck. 38-39 [doi]
- Component selection and matching for IP-based designG. Martin, Ralf Seepold, Ting Zhang, Luca Benini, Giovanni De Micheli. 40-46 [doi]
- A universal communication model for an automotive system integration platformThilo Demmeler, Paolo Giusto. 47-54 [doi]
- An efficient architecture model for systematic design of application-specific multiprocessor SoCAmer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya. 55-63 [doi]
- The simulation semantics of systemCJürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller 0003. 64-70 [doi]
- MetaRTL: raising the abstraction level of RTL designJ. Zhu. 71-76 [doi]
- A model for describing communication between aggregate objects in the specification and design of embedded systemsKjetil Svarstad, Gabriela Nicolescu, Ahmed Amine Jerraya. 77-85 [doi]
- Circuit partitioning for efficient logic BIST synthesisA. Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich. 86-91 [doi]
- Deterministic software-based self-testing of embedded processor coresAntonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian. 92-96 [doi]
- Memory fault diagnosis by syndrome compressionJin-Fu Li, Cheng-Wen Wu. 97-101 [doi]
- Diagnosis for scan-based BIST: reaching deep into the signaturesIsmet Bayraktaroglu, Alex Orailoglu. 102-111 [doi]
- Methods and tools for systems engineering of automotive electronic architecturesJakob Axelsson. 112 [doi]
- Using SAT for combinational equivalence checkingEvguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton. 114-121 [doi]
- Combinational equivalence checking using Boolean satisfiability and binary decision diagramsSherief Reda, A. Salem. 122-126 [doi]
- An efficient learning procedure for multiple implication checksYakov Novikov, Evguenii I. Goldberg. 127-135 [doi]
- C/C++: progress or deadlock in system-level specificationDaniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong. 136-137 [doi]
- An integrated system-on-chip test frameworkErik Larsson, Zebo Peng. 138-144 [doi]
- Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb codingAnshuman Chandra, Krishnendu Chakrabarty. 145-149 [doi]
- Testing TAPed cores and wrapped cores with the same test access mechanismMounir Benabdenbi, Walid Maroufi, Meryem Marzouki. 150-155 [doi]
- On applying the set covering model to reseedingSilvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich. 156-161 [doi]
- Data management: limiter or accelerator for electronic design creativityPeter van Staa, Robert Bosch, H. Heidbrink, B. Potock, J. Mueller, W. Kisselmann, W. Herden. 162-163 [doi]
- Efficient bit-error-rate estimation of multicarrier transceiversGerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels, Ivo Bolsens. 164-168 [doi]
- Efficient time-domain simulation of telecom frontends using a complex damped exponential signal modelPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. 169-175 [doi]
- Microprocessor power analysis by labeled simulationCheng-Ta Hsieh, L. Chen, Massoud Pedram. 182-189 [doi]
- Power aware microarchitecture resource scalingAnoop Iyer, Diana Marculescu. 190-196 [doi]
- Extending lifetime of portable systems by battery schedulingLuca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi. 197-203 [doi]
- Efficient spectral techniques for sequential ATPGAshish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal. 204-208 [doi]
- On the test of microprocessor IP coresFulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante. 209-213 [doi]
- Sequence reordering to improve the levels of compaction achievable by static compaction proceduresIrith Pomeranz, Sudhakar M. Reddy. 214-218 [doi]
- SEU effect analysis in an open-source router via a distributed fault injection environmentAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 219-225 [doi]
- Slicing tree is a complete floorplan representationMinghorng Lai, D. F. Wong. 228-232 [doi]
- Further improve circuit partitioning using GBAW logic perturbation techniquesChak-Chung Cheung, Yu-Liang Wu, David Ihsin Cheng. 233-239 [doi]
- Clustering based fast clock scheduling for light clock-treeMakoto Saitoh, Masaaki Azuma, Atsushi Takahashi. 240-245 [doi]
- Power-efficient layered turbo decoder processorJohn Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf. 246-251 [doi]
- Exploiting data forwarding to reduce the power budget of VLIW embedded processorsMariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon. 252-257 [doi]
- Design of low-power high-speed maximum a priori decoder architecturesAlexander Worm, Holger Lamm, Norbert Wehn. 258-267 [doi]
- Low complexity FIR filters using factorization of perturbed coefficientsCassondra Neau, Khurram Muhammad, Kaushik Roy. 268-272 [doi]
- An adaptive algorithm for low-power streaming multimedia processingAndrea Acquaviva, Luca Benini, Bruno Riccò. 273-279 [doi]
- A static power estimation methodolodgy for IP-based designXun Liu, Marios C. Papaefthymiou. 280-289 [doi]
- Optimization of error detecting codes for the detection of crosstalk originated errorsMichele Favalli, Cecilia Metra. 290-296 [doi]
- System safety through automatic high-level code transformations: an experimental evaluationPh. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 297-301 [doi]
- From DFT to systems test - a model based cost optimization toolMichael G. Wahl, Anthony P. Ambler, Christoph Maaß, Mohammed Rahman. 302-306 [doi]
- Efficient on-line testing method for a floating-point adderAlexander V. Drozd, M. V. Lobachev. 307-313 [doi]
- Design methodology for PicoRadio networksJulio Leao da Silva Jr., J. Shamberger, M. Josie Ammer, C. Guo, Suet-Fei Li, Rahul C. Shah, Tim Tuan, Michael Sheets, Jan M. Rabaey, Borivoje Nikolic, Alberto L. Sangiovanni-Vincentelli, Paul K. Wright. 314-325 [doi]
- High-level simulation of substrate noise generation from large digital circuits with multiple suppliesMustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens. 326-330 [doi]
- Crosstalk noise in future digital CMOS circuitsChr. Werner, R. Göttsche, A. Wörner, Ulrich Ramacher. 331-335 [doi]
- Modeling electromagnetic emission of integrated circuits for system analysisP. Kralicek, Werner John, Heyno Garbe. 336-340 [doi]
- Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technologyRocio del Río, Josep Lluís de la Rosa, F. Medeiro, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez. 348-352 [doi]
- Analog design for reuse - case study: very low-voltage sigma-delta modulatorMohamed Dessouky, Andreas Kaiser, Marie-Minerve Louërat, Alain Greiner. 353-360 [doi]
- A design strategy for low-voltage low-power continuous-time sigma-delta A/D convertersFriedel Gerfers, Yiannos Manoli. 361-369 [doi]
- Minimizing stand-by leakage power in static CMOS circuitsSrinath R. Naidu, E. T. A. F. Jacobs. 370-376 [doi]
- In-place delay constrained power optimization using functional symmetriesChih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska. 377-382 [doi]
- High-quality sub-function construction in functional decomposition based on information relationship measuresLech Józwiak, Artur Chojnacki. 383-390 [doi]
- Generalized reasoning scheme for redundancy addition and removal logic optimizationJosé Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías. 391-397 [doi]
- LPSAT: a unified approach to RTL satisfiabilityZhihong Zeng, Priyank Kalla, Maciej J. Ciesielski. 398-402 [doi]
- Functional test generation for behaviorally sequential modelsFabrizio Ferrandi, G. Ferrara, Donatella Sciuto, Alessandro Fin, Franco Fummi. 403-410 [doi]
- High quality behavioral verification using statistical stopping criteriaAmjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman. 411-419 [doi]
- Network processors: a perspective on market requirements, processor architectures and embedded S/W toolsPierre G. Paulin, Faraydon Karim, Paul Bromley. 420-429 [doi]
- Efficient inductance extraction via windowingMichael W. Beattie, Lawrence T. Pileggi. 430-436 [doi]
- Efficient and passive modeling of transmission lines by using differential quadrature methodQinwei Xu, Pinaki Mazumder. 437-444 [doi]
- Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elementsQingjian Yu, Ernest S. Kuh. 445-450 [doi]
- On the impact of on-chip inductance on signal nets under the influence of power grid noiseTom Chen. 451-459 [doi]
- Timing simulation of digital circuits with binary decision diagramsRaimund Ubar, Artur Jutman, Zebo Peng. 460-466 [doi]
- HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay modelPaulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia. 467-471 [doi]
- dibSIM: a parallel functional logic simulator allowing dynamic load balancingKlaus Hering, Jork Löser, Jens Markwardt. 472-478 [doi]
- Architecture driven partitioningJoachim Küter, Erich Barke. 479-487 [doi]
- Low-power systems on chips (SOCs)Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés. 488 [doi]
- Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMsZaid Al-Ars, A. J. van de Goor. 496-503 [doi]
- Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverageIrith Pomeranz, Sudhakar M. Reddy. 504-508 [doi]
- CMOS open defect detection by supply current testMasaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada. 509 [doi]
- Full chip false timing path identification: applications to the PowerPCTM microprocessorsJing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham. 514-519 [doi]
- CAD for RF circuitsPiet Wambacq, Gerd Vandersteen, Joel R. Phillips, Jaijeet S. Roychowdhury, Wolfgang Eberle, Baolin Yang, David E. Long, Alper Demir. 520-529 [doi]
- Modeling crosstalk noise for deep submicron verification toolsPirouz Bazargan-Sabet, Fabrice Ilponse. 530-534 [doi]
- Repeater block planning under simultaneous delay and transition time constraintsProbir Sarkar, Cheng-Kok Koh. 540-545 [doi]
- On-the-fly layout generation for PTL macrocellsLuca Macchiarulo, Luca Benini, Enrico Macii. 546-551 [doi]
- Automatic datapath tile placement and routingTatjana Serdar, Carl Sechen. 552-559 [doi]
- A boolean satisfiability-based incremental rerouting approach with application to FPGAsGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar. 560-565 [doi]
- Dual transitions petri net based modelling technique for embedded systems specificationMauricio Varea, Bashir M. Al-Hashimi. 566-571 [doi]
- Probabilistic application modeling for system-level perfromance analysisRadu Marculescu, Amit Nandi. 572-579 [doi]
- Reliable estimation of execution time of embedded softwarePaolo Giusto, Grant Martin, Edwin A. Harcourt. 580-589 [doi]
- Implementation of a linear histogram BIST for ADCsFlorence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. 590-595 [doi]
- Test generation based diagnosis of device parameters for analog circuitsSasikumar Cherubal, Abhijit Chatterjee. 596-602 [doi]
- Managing the SoC design challenge with Soft hardwareRon Wilson. 610-611 [doi]
- Allocation and scheduling of conditional task graph in hardware/software co-synthesisYuan Xie, Wayne Wolf. 620-625 [doi]
- System-on-a-chip processor synchronization support in hardwareBilge Saglam Akgul, Vincent John Mooney III. 633-641 [doi]
- Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computersIyad Ouaiss, Ranga Vemuri. 650-657 [doi]
- Optimal FPGA module placement with temporal precedence constraintsSándor P. Fekete, Ekkehard Köhler, Jürgen Teich. 658-667 [doi]
- Generation of minimal size code for scheduling graphsClaudio Passerone, Yosinori Watanabe, Luciano Lavagno. 668-673 [doi]
- Generating production quality software development tools using a machine description languageAndreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr. 674-678 [doi]
- Automatic generation and targeting of application specific operating systems and embedded systems softwareLovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya. 679-685 [doi]
- Cache conscious data layout organization for embedded multimedia applicationsChidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man. 686-693 [doi]
- Design challenges and emerging EDA solutions in mixed-signal IC designGeorges G. E. Gielen, B. Sorensen, H. Casier, Philippe Magarshack, J. Rodriguez. 694-695 [doi]
- CPU for PlayStation 2Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto. 696 [doi]
- SH-4 RISC microprocessor for multimedia, game machineSusumu Narita. 699-701 [doi]
- Streaming BDD manipulation for large-scale combinatorial problemsShin-ichi Minato, Shinya Ishihara. 702-707 [doi]
- Binary decision diagram with minimum expected path lengthYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu. 708-712 [doi]
- Spectral decision diagrams using graph transformationsMitchell A. Thornton, Rolf Drechsler. 713-719 [doi]
- Electronic system design methodology: Europe s positioningAhmed Amine Jerraya, G. Matheron. 720-721 [doi]
- Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAsAnshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee. 722-728 [doi]
- A HW/SW partitioning algorithm for dynamically reconfigurable architecturesJuanjo Noguera, Rosa M. Badia. 729 [doi]
- Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networksZhining Huang, Sharad Malik. 735 [doi]
- Simulation-guided property checking based on a multi-valued AR-automataJürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel. 742-748 [doi]
- Mixed-level cosimulation for fine gradual refinement of communication in SoC designGabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya. 754-759 [doi]
- A framework for fast hardware-software co-simulationAndreas Hoffmann, Tim Kogel, Heinrich Meyr. 760-765 [doi]
- Retargeting of mixed-signal blocks for SoCsR. Castro-López, Francisco V. Fernández, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez. 772-775 [doi]
- Standard bus vs. bus wrapper: what is the best solution for future SoC integration?C. Yeung, Anssi Haverinen, Graham Matthews, Jonathan Morris, Jauher Zaidi. 776-777 [doi]
- Access pattern based local memory customization for low power embedded systemsPeter Grun, Nikil D. Dutt, Alexandru Nicolau. 778-784 [doi]
- Static memory allocation by pointer analysis and coloringJianwen Zhu. 785-790 [doi]
- Heuristic datapath allocation for multiple wordlength systemsGeorge A. Constantinides, Peter Y. K. Cheung, Wayne Luk. 791-797 [doi]
- On the verification of synthesized designs using automatically generated transformational witnessesElena Teica, Rajesh Radhakrishnan, Ranga Vemuri. 798 [doi]
- Property-specific witness graph generation for guided simulationAlbert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar. 799 [doi]
- Two approaches for developing generic components in VHDLVytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius, Giedrius Majauskas. 800 [doi]
- Annotated data types for addressed token passing networksGordon Cichon, Winthir Bunnbauer. 801 [doi]
- Testability trade-offs for BIST RTL data paths: the case for three dimensional design spaceNicola Nicolici, Bashir M. Al-Hashimi. 802 [doi]
- Towards a better understanding of failure modes and test requirements of ADCsA. Lechner, Andrew Richardson, B. Hermes. 803 [doi]
- Exact fault simulation for systems on Silicon that protects each core s intellectual propertyMd. Saffat Quasem, Sandeep K. Gupta. 804 [doi]
- Using mission logic for embedded testingRainer Dorsch, Hans-Joachim Wunderlich. 805 [doi]
- An improved hierarchical classification algorithm for structural analysis of integrated circuitsMarkus Olbrich, Achim Rein, Erich Barke. 807 [doi]
- Automatic nonlinear memory power modellingEike Schmidt, Gerd Jochens, Lars Kruse, Frans Theeuwen, Wolfgang Nebel. 808 [doi]
- An operation rearrangement technique for power optimization in VLIM instruction fetchDongkun Shin, Jihong Kim, Naehyuck Chang. 809 [doi]
- A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuitsOscar Garnica, Juan Lanchares, Román Hermida. 810 [doi]
- A register-transfer-level fault simulator for permanent and transient faults in embedded processorsC. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus. 811 [doi]
- Efficient finite field digital-serial multiplier architecture for cryptography applicationsGuido Bertoni, Luca Breveglieri, Pasqualina Fragneto. 812 [doi]
- Task concurrency management methodology summaryChun Wong, Paul Marchal, Peng Yang, Francky Catthoor, Hugo De Man, Aggeliki S. Prayati, Nathalie Cossement, Rudy Lauwereins, Diederik Verkest. 813 [doi]
- Order determination for frequency compensation of negative-feedback systemsArie van Staveren, Chris J. M. Verhoeven. 815 [doi]
- Minimizing the number of floating bias voltage sources with integer linear programmingE. Yildiz, Arie van Staveren, Chris J. M. Verhoeven. 816 [doi]
- CMOS sizing rule for high performance long interconnectsGregorio Cappuccino, Giuseppe Cocorullo. 817 [doi]
- On automatic analysis of geometrically proximate nets in VSLI layoutSandeep Koranne, Om Prakash Gangwal. 818 [doi]
- AnalogRouter: a new approach of current-driven routing for analog circuitsJens Lienig, Goeran Jerke, Thorsten Adler. 819 [doi]
- A hardware-software operating system for heterogeneous designsJosé Manuel Moya, Francisco Moya, Juan Carlos López. 820 [doi]
- PRMDL: a machine description language for clustered VLIW architecturesAndrei Terechko, Evert-Jan D. Pol, Jos T. J. van Eijndhoven. 821 [doi]
- Functional units with conditional input/output behavior in VLIW processorsMarco Bekooij, Loek J. M. Engels, Albert van der Werf, Natalino G. Busá. 822 [doi]
- Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulationMina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi. 823 [doi]
- Constraint satisfaction for storage files with Fifos or stacks during schedulingCarlos A. Alba Pinto, Bart Mesman, Koen Van Eijk, Jochen A. G. Jess. 824 [doi]