Abstract is missing.
- Physical-design-friendly hierarchical logic built-in self-test - A case studyKelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang. 1-6 [doi]
- A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiersAbhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee, Duane C. Howard, John D. Cressler. 7-12 [doi]
- Improved path clustering for adaptive path-delay testingTuck Boon Chan, Andrew B. Kahng. 13-20 [doi]
- TSV and DFT cost aware circuit partitioning for 3D-SOCsAmit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker. 21-26 [doi]
- A design-for-test apparatus for measuring on-chip temperature with fine granularityJames S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada. 27-32 [doi]
- Wearout-aware compiler-directed register assignment for embedded systemsFahad Ahmed, Mohamed M. Sabry, David Atienza, Linda Milor. 33-40 [doi]
- Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yieldDavit Mirzoyan, Benny Akesson, Kees Goossens. 41-48 [doi]
- Single fault reliability analysis in FPGA implemented circuitsHadi Jahanirad, Karim Mohammadi, Pejman Attarsharghi. 49-56 [doi]
- Low complexity cross parity codes for multiple and random bit error correctionMahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty. 57-62 [doi]
- Delay insensitive code-based timing and soft error-resilient and adaptive-performance logicBao Liu, Xuemei Chen, Fiona Teshome. 63-72 [doi]
- A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chipShirish Bahirat, Sudeep Pasricha. 78-83 [doi]
- A preliminary study on system-level impact of persistent main memoryTaciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose. 84-90 [doi]
- Optimal microarchitectural design configuration selection for processor hard-error reliabilityYing Zhang, Lide Duan, Bin Li, Lu Peng. 91-96 [doi]
- NoC-based platform for embedded software design: An extension of the Hellfire FrameworkFelipe G. Magalhaes, Oliver B. Longhi, Sergio Johann Filho, Alexandra Aguiar, Fabiano Hessel. 97-102 [doi]
- Thermal via structural design in three-dimensional integrated circuitsLeslie Hwang, Kevin L. Lin, Martin D. F. Wong. 103-108 [doi]
- Functional test pattern generation for maximizing temperature in 3D IC chip stackSudarshan Srinivasan, Sandip Kundu. 109-116 [doi]
- Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element methodAmir Zjajo, Nick van der Meijs, Rene van Leuken. 117-222 [doi]
- Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES methodXuexin Liu, Zao Liu, Sheldon X.-D. Tan, Joseph A. Gordon. 123-128 [doi]
- Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICsKan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong. 129-136 [doi]
- A 3D IC designs partitioning algorithm with power considerationHo-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi. 137-142 [doi]
- Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementationKareem Ragab, Ranjit Gharpurey, Michael Orshansky. 143-150 [doi]
- An ultra-low voltage digitally controlled low-dropout regulator with digital background calibrationYongtae Kim, Peng Li. 151-158 [doi]
- Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm processKarthik Rajagopal. 159-164 [doi]
- Design of an efficient NoC architecture using millimeter-wave wireless linksSujay Deb, Kevin Chang, Amlan Ganguly, Xinmin Yu, Christof Teuscher, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer. 165-172 [doi]
- A novel robust signaling scheme for high-speed low-power communication over long wiresMarshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 173-178 [doi]
- An extended-range incremental CT ∑Δ ADC with optimized digital filterJulian Garcia, Ana Rusu. 179-184 [doi]
- Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern densityAlbert H. Chang, Kewei Zuo, Jean Wang, Douglas Yu, Duane S. Boning. 185-192 [doi]
- Post-placement lithographic hotspot detection and removal in one-dimensional gridded designsJen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska. 193-199 [doi]
- On lithography aware metal-fill insertionVikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu. 200-207 [doi]
- Understanding, modeling, and detecting pooling hotspots in copper CMPAaron Gower-Hall, Tamba Gbondo-Tugbawa, JenPin Weng, Wei-tsu Tseng, Laertis Economikos, Toshiaki Yanagisawa, Pavan Bashaboina, Stephen Greco. 208-215 [doi]
- Methodology for analysis of TSV stress induced transistor variation and circuit performanceLi Yu, Wen-Yao Chang, Kewei Zuo, Jean Wang, Douglas Yu, Duane S. Boning. 216-222 [doi]
- High performance electrical driven hotspot detection solution for full chip design using a novel device parameter matching techniqueRami F. Salem, Mohamed Al-Imam, Abdelrahman ElMously, Haitham Eissa, Ahmed Arafa, Mohab H. Anis. 223-227 [doi]
- Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnectsYoung-Joon Lee, Sung Kyu Lim. 228-335 [doi]
- Functional composition: A new paradigm for performing logic synthesisMayler G. A. Martins, Renato P. Ribas, André Inácio Reis. 236-242 [doi]
- A new voltage binning technique for yield improvement based on graph theoryRuijing Shen, Sheldon X.-D. Tan, Xuexin Liu. 243-248 [doi]
- A complete power estimation methodology for DSP blocks in FPGAsHassan Hassan, Nizar Abdallah. 249-254 [doi]
- Process variation aware DRAM design using block based adaptive body biasing algorithmSatyajit Desai, Sanghamitra Roy, Koushik Chakraborty. 255-261 [doi]
- Device- and system-level performance modeling for graphene P-N junction logicChenyun Pan, Azad Naeemi. 262-269 [doi]
- Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM applicationYasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu. 270-274 [doi]
- A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs)Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic. 275-282 [doi]
- Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limitsShaloo Rakheja, Azad Naeemi. 283-290 [doi]
- Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnectsManoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas. 291-297 [doi]
- Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibrationVikram B. Suresh, Wayne P. Burleson. 298-305 [doi]
- Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devicesTakashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi. 306-311 [doi]
- Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuitZafar Takhirov, Bobak Nazer, Ajay Joshi. 312-319 [doi]
- The combined effect of process variations and power supply noise on clock skew and jitterHu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli. 320-327 [doi]
- TDDB-based performance variation of combinational logic in deeply scaled CMOS technologyHaiqing Nan, Li Li, Ken Choi. 328-333 [doi]
- Critical area driven dummy fill insertion to improve manufacturing yieldNishant Dhumane, Sandip Kundu. 334-341 [doi]
- Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOSRoberto Menchaca, Hamid Mahmoodi. 342-346 [doi]
- A highly reliable SEU hardened latch and high performance SEU hardened flip-flopRiadul Islam. 347-352 [doi]
- A scalable curve-fit model of the substrate coupling resistances for IC designVijaya Kumar Gurugubelli, Shreepad Karmalkar. 353-357 [doi]
- Efficient reduction techniques for statistical model generation of standard cellsSachin Shrivastava, Harindranath Parameswaran. 358-363 [doi]
- Efficient electro-thermal co-analysis on CPU+GPU heterogeneous architectureHuang Kun, Yang Xu, Guoxing Zhao, Zuying Luo. 364-369 [doi]
- Dynamic range estimation for systems with control-flow structuresBin Wu. 370-377 [doi]
- Comparison of variations in MOSFET versus CNFET in gigascale integrated systemsAli Arabi M. Shahi, Payman Zarkesh-Ha, Mirza Elahi. 378-383 [doi]
- Vertical Slit Field Effect Transistor in ultra-low power applicationsXiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly. 384-390 [doi]
- Design and optimization of power gating for DVFS applicationsTong Xu, Peng Li. 391-397 [doi]
- An area efficient on-chip hybrid voltage regulatorSelçuk Köse, Eby G. Friedman, Simon Tarn, Sally Pinzon, Bruce McDermott. 398-403 [doi]
- Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrixPatrick Le Maitre, Melanie Brocard, Alexis Farcy, Jean-Claude Marin. 404-411 [doi]
- A case for 3D stacked analog circuits in high-speed sensing systemsMohammad Abdel-Majeed, Mike Chen, Murali Annavaram. 412-417 [doi]
- A DyadicCluster method used for nonlinear placementWenchao Gao, Qiang Zhou, Xu Qian, Yici Cai. 418-423 [doi]
- Clock mesh frameworkPinaki Chakrabarti, Vikram Bhatt, Dwight Hill, Aiqun Cao. 424-431 [doi]
- Placement aware clock gate cloning and redistribution methodologyRamamurthy Vishweshwara, Nagabhiru Mahita, Ramakrishnan Venkatraman. 432-436 [doi]
- Impact of C-elements in asynchronous circuitsMatheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans. 437-343 [doi]
- Cost-minimized double die DRAM packaging for ultra-high performance DDR3 and DDR4 multi-rank server DIMMsRichard Crisp, Bill Gervasi, Wael Zohni, Bel Haba. 437-444 [doi]
- A top-down design methodology using virtual platforms for concept developmentMohit Shah, Brian Mears, Chaitali Chakrabarti, Andreas Spanias. 444-450 [doi]
- Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoCEduardo Antunes, Matheus Soares, Alexandra Aguiar, Sergio Johann Filho, Marcos Sartori, Fabiano Hessel, César A. M. Marcon. 451-457 [doi]
- Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimizationOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos. 458-463 [doi]
- CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effectsYu Zhang, Bo Liu, Bo Yang 0004, Jing Li, Shigetoshi Nakatake. 464-469 [doi]
- DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAMAmith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N. Singh, Aditya Bansal. 470-476 [doi]
- Hierarchical power network synthesis for multiple power domain designsChieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee. 477-482 [doi]
- Algorithmic study on the routing reliability problemQiang Ma 0002, Zigang Xiao, Martin D. F. Wong. 483-488 [doi]
- A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reductionMasaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. 489-492 [doi]
- Process variation tolerant 9T SRAM bitcell designG. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty. 493-497 [doi]
- History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoringAvesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi. 498-505 [doi]
- VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOSJeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey. 506-515 [doi]
- Bit error rate estimation in SRAM considering temperature fluctuationYuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 516-519 [doi]
- Chip-package power delivery network resonance analysis and co-design using time and frequency domain analysis techniquesJonathan Watkins, Jai Pollayil, Calvin Chow, Aveek Sarkar. 520-524 [doi]
- Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm OptimizationJai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee. 525-528 [doi]
- A design tradeoff study with monolithic 3D integrationChang Liu, Sung Kyu Lim. 529-536 [doi]
- Speed-path analysis for multi-path failed latches with random variationTsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, Hiroaki Komatsu. 545-552 [doi]
- st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOSHironori Sakamoto, Shigetaka Kumashiro, Shigeo Sato, Naoki Wakita, Tohru Mogami. 553-560 [doi]
- An accurate current source model for CMOS based combinational logic cellBaljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand. 561-565 [doi]
- Effcient approaches to overcome non-convexity issues in analog design automationSupriyo Maji, Pradip Mandal. 566-571 [doi]
- Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysisTakeshi Kida, Yasumasa Tsukamoto, Yuji Kihara. 572-579 [doi]
- Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applicationsOleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah. 580-585 [doi]
- DDmin limited ultra low voltage logic circuitsTadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai. 586-591 [doi]
- Enhancing efficiency and robustness of a photovoltaic power system under partial shadingYanzhi Wang, Xue Lin, Younghyun Kim, Naehyuck Chang, Massoud Pedram. 592-600 [doi]
- Comparison between power gating and DVFS from the viewpoint of energy efficiencyAtsuki Inoue. 601-608 [doi]
- Design of low-power, scalable-throughput systems at near/sub threshold voltageMeeta Srivastav, Michael B. Henry, Leyla Nazhandali. 609-616 [doi]
- Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platformsChirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings. 617-624 [doi]
- Efficient leakage power saving by sleep depth controlling for Multi-mode Power GatingSeidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura. 625-632 [doi]
- DDRO: A novel performance monitoring methodology based on design-dependent ring oscillatorsTuck Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai. 633-640 [doi]
- An analytical approach to efficient circuit variability analysis in scaled CMOS designSamatha Gummalla, Anupama R. Subramaniam, Yu Cao, Chaitali Chakrabarti. 641-647 [doi]
- Process mismatch analysis based on reduced-order modelsMustafa Berke Yelten, Paul D. Franzon, Michael B. Steer. 648-655 [doi]
- Transistor channel decomposition for structured analog layout, manufacturability and low-power applicationsQing Dong, Bo Yang 0004, Gong Chen, Jing Li, Shigetoshi Nakatake. 656-662 [doi]
- Theory of redundancy for logic circuits to maximize yield/areaMohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian. 663-671 [doi]
- A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variabilityRouwaida Kanj, Rajiv V. Joshi. 672-678 [doi]
- Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESLMao-Yin Wang, Jen-Chieh Yeh. 679-685 [doi]
- Automated correction of design errors by edge redirection on High-Level Decision DiagramsAnton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik. 686-693 [doi]
- Assertion clustering for compacted test sequence generationJason G. Tong, Marc Bottle, Zeljko Zilic. 694-701 [doi]
- Transaction-based post-silicon debug of many-core System-on-ChipsAmir Masoud Gharehbaghi, Masahiro Fujita. 702-708 [doi]
- An enhanced debug-aware network interface for Network-on-ChipMohammad Hossein Neishaburi, Zeljko Zilic. 709-716 [doi]
- Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performanceNaushad Alam, Bulusu Anand, Sudeb Dasgupta. 717-722 [doi]
- Design issues and insights of multi-fin bulk silicon FinFETsHsun Li, Meng-Hsueh Chiang. 723-726 [doi]
- Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysisXin Huang, Tianwei Zhang, Runsheng Wang, Changze Liu, Yuchao Liu, Ru Huang. 727-731 [doi]
- Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerationsShaloo Rakheja, Vachan Kumar. 732-739 [doi]
- Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devicesKaiyuan Yang, Dae-Hyun Kim, Sung Kyu Lim. 740-746 [doi]
- Learning based DVFS for simultaneous temperature, performance and energy managementHao Shen, Jun Lu, Qinru Qiu. 747-754 [doi]
- Hot peripheral thermal management to mitigate cache temperature variationHouman Homayoun, Mehryar Rahmatian, Vasileios Kontorinis, Shahin Golshan, Dean M. Tullsen. 755-763 [doi]
- Power-Performance Yield optimization for MPSoCs using MILPKshitij Bhardwaj, Sanghamitra Roy, Koushik Chakraborty. 764-771 [doi]
- A variation and energy aware ILP formulation for task scheduling in MPSoCMahboobeh Ghorbani. 772-777 [doi]
- Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesisKeisuke Inoue, Mineo Kaneko. 778-783 [doi]