Abstract is missing.
- A Test Retrospection and a Quest for DirectionRobert E. Anderson. 11
- Test: The New Value-Added FieldAart J. de Geus. 12
- Faster, Better, Cheaper: What Does This Mean For The Test Industry?Walt Wilson. 13
- Development of a Solution for Achieving Known-Good-DieLina Prokopchak. 15-21
- Membrane Prove Technology for MCM Known-Good-DieToshiaki Ueno, You Kondoh. 22-29
- High-Yield Multichip Modules Based on Minimal IC PretestWilliam E. Burdick Jr., Wolfgang Daum. 30-40
- Feasibility Study of Smart Substrate Multichip ModulesAnne E. Gattiker, Wojciech Maly. 41-49
- Testability Strategy of the ALPHA AXP 21164 MicroprocessorDilip K. Bhavsar, John H. Edmondson. 50-59
- Testabilty Features of the MC 68060 MicroprocessorAlfred L. Crouch, Matthew Pressly, Joe Circello. 60-69
- microSPARC:::TM:::: A Case Study of Scan-Based DebugKalon Holdbrook, Sunil Joshi, Samir Mitra, Joe Petolino, Renu Raman, Michelle Wong. 70-75
- Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603:::TM::: MicroprocessorCraig Hunter, E. Kofi Vida-Torku, Johnny LeBlanc. 76-83
- System Test Cost Modelling Based on Event Rate AnalysisDes Farren, Anthony P. Ambler. 84-92
- ASIC Test Cost/Strategy Trade-offsDonald L. Wheater, Phil Nigh, Jeanne Trinko Mechler, Luke Lacroix. 93-102
- A Test Process Optimization and Cost Modeling ToolTimothy J. Moore. 103-110
- When Does It Make cents to Give Up Physical Test Access?David A. Greene. 111-119
- 3B21D BIST/Boundary-Scan System Diagnostic Test StoryEdward C. Behnke. 120-126
- Modeling for Structured System Interconnect TestFrank W. Angelotti. 127-133
- System-Level Testability of Hardware/Software SystemsHarald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee. 134-142
- A Generic Test and Maintenance Node for Embedded System TestJohn D. Lofgren. 143-153
- Fastpath: A Path-Delay Test Generator for Standard Scan DesignsBill Underwood, Wai-On Law, Sungho Kang, Haluk Konuk. 154-163
- On Path-Delay Testing in a Standard Scan EnvironmentPrab Varma. 164-173
- Automated Logic Synthesis of Random-Pattern-Testable CircuitsNur A. Touba, Edward J. McCluskey. 174-183
- Transforming Behavioral Specifications to Facilitate Synthesis of Testable DesignsSujit Dey, Miodrag Potkonjak. 184-193
- QTAG: A Standard for Test Fixture Based I::DDQ::/I::SSQ:: MonitorsKeith Baker. 194-202
- An Off-chip I::DDQ:: Current Measurement Unit for Telecommunication ASICsHans A. R. Manhaeve, Paul L. Wrighton, Jos van Sas, Urbain Swerts. 203-212
- Development of a CLASS 1 QTAG MonitorKeith Baker, A. Bratt, Andrew M. D. Richardson, A. Welbers. 213-222
- A Serially Addressable, Flexible Current Monitor for Test Fixture Based I::DDQ::/I::SSQ:: TestingAlan Hales. 223-232
- On the Initialization of Sequential CircuitsJalal A. Wehbeh, Daniel G. Saab. 233-239
- An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic AlgorithmsPaolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 240-249
- ATPG for Heat Dissipation Minimization During Test ApplicationSeongmoon Wang, Sandeep K. Gupta. 250-258
- Sequentially Untestable Faults Identified Without Search ( Simple Implications Beat Exhaustive Search! )Mahesh A. Iyer, Miron Abramovici. 259-266
- Implementation of a Dual-Segment Architecture for a High-Pin-Count VLSI Test SystemMichael G. Davis. 267-272
- 500-MHz Testing on a 100-MHz TesterDidier Wimmers, Kris Sakaitani, Burnell G. West. 273-278
- Modeling the Effect of Ground Bounce on Noise MarginMary Sue Haydt, Robert Michael Owens, Samiha Mourad. 279-285
- Modular Mixed Signal Testing: High Speed or High ResolutionEric Kushnick. 286-290
- Built-in System Test and Fault LocationGordon R. McLeod. 291-299
- Roadmap for Extending IEEE 1149.1 for Hierarchical Control of Locally-Stored, Standardized-Command-Set Test ProgramsJohn Andrews. 300-306
- Environmental Stress Testing with Boundary-ScanDuy Le, Ivan Karolik, Ronald Smith, A. J. Mcgovern, Chyral Curette, Joseph Ulbin, Michael Zarubaiko, Charles Henry, Lewis Stevens. 307-313
- An Approach to Accelerate Scan Testing in IEEE 1149.1 ArchitecturesLee Whetsel. 314-322
- Multi-Frequency, Multi-Phase Scan ChainKee Sup Kim, Len Schultz. 323-330
- A Test-Clock Reduction Method for Scan-Designed CircuitsJau-Shien Chang, Chen-Shang Lin. 331-339
- Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test GenerationSanghyeon Baeg, William A. Rogers. 340-349
- In-System Timing Extraction and Control Through Scan-Based, Test-Access PortsAndré DeHon. 350-359
- Testing 256k Word x 16 Bit Cache DRAM (CDRAM)Yasuhiro Konishi, T. Ogawa, M. Kumanoya. 360
- Testing High Speed DramsJames A. Gasbarro. 361
- Practical Test Methods for Verification of the EDRAMKent Stalnaker. 362
- Testing Issues on High Speed Synchronous DRAMsWha-Joon Lee. 363
- BenchmarkingKamalesh N. Ruparel. 364
- Potential Solutions for Benchmarking IssuesDon Sterba. 365
- Multichip Module Testing Methodologies: What s In; What s NotKenneth E. Posse. 366
- MCM Test Trade-OffsJed Eastman. 367
- Aliasing-free Signature Analysis for RAM BISTVyacheslav N. Yarmolik, Michael Nicolaidis, O. Kebichi. 368-377
- An Effective BIST Scheme for Ring-Address Type FIFOsYervant Zorian, A. J. van de Goor, Ivo Schanstra. 378-387
- The PowerPC 603:::TM::: Microprocessor: An Array Built-In Self-Test MechanismCraig Hunter, Jeff Slaton, Jim Eno, Romesh M. Jessani, Carl Dietz. 388-394
- Testing CMOS Logic Gates for Realistic ShortsBrian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee. 395-402
- A Study of I::DDQ:: Subset Selection Algorithms for Bridging FaultsSreejit Chakravarty, Paul J. Thadikaran. 403-412
- Defect Classes - An Overdue Paradigm for CMOS ICCharles F. Hawkins, Jerry M. Soden, Alan W. Righter, F. Joel Ferguson. 413-425
- A Test Methodology to Support an ASEM MCM FoundryThomas M. Storey, C. Lapihuska, E. Atwood, L. Su. 426-435
- Test Strategies for a Family of Complex MCMsAndrew Flint. 436-445
- Designing Dual-Personality IEEE 1149.1-Compliant Multi-Chip ModulesNajmi T. Jarwala. 446-455
- A Case Study in the Use of Scan in microSparc:::TM::: Testing and DebugJerry Katz. 456-460
- A Hierarchical Environment for Interactive Test EngineeringThomas Burch, J. Hartmann, Günter Hotz, M. Krallmann, U. Nikolaus, Sudhakar M. Reddy, Uwe Sparmann. 461-470
- Ensuring System Traceability to International StandardsSolomon Max. 471-480
- GLFSR - A New Test Pattern Generator for Built-In Self-TestDhiraj K. Pradhan, Mitrajit Chatterjee. 481-490
- Design of an Efficient Weighted-Random-Pattern Generation SystemRohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams. 491-500
- Efficient Test-Response Compression for Multiple-Output CicuitsKrishnendu Chakrabarty, John P. Hayes. 501-510
- ECC-On-SIMM Test ChallengesTimothy J. Dell. 511-515
- Techniques for Characterizing DRAMs With a 500-MHz InterfaceJames A. Gasbarro, Mark Horowitz. 516-525
- Automatic Failure-Analysis System for High-Density DRAMSang-Chul Oh, Jae-Ho Kim, Ho-Jeong Choi, Si-Don Choi, Ki Tae Park, Jong-Woo Park, Wha-Joon Lee. 526-530
- Detection and Correction of Systematic Type 1 Test Errors Through Concurrent EngineeringWilliam R. Kosar. 531-538
- Defects, Fault Coverage, Yield and Cost in Board ManufacturingMick Tegethoff, Tom Chen. 539-547
- HALT: Bridging the Gap Between Theory and PracticeCheryl Ascarrunz. 548-554
- Residual Charge on the Faulty Floating Gate MOS TransistorSimon Johnson. 555-561
- Variable Supply Voltage Testing for Analogue CMOS and Bipolar CircuitsEric Bruls. 562-571
- Is I::DDQ:: Yield Loss Inevitable?Scott Davidson. 572-579
- A Software Architecture for Mixed-Signal Functional TestingJohn A. Masciola, Gerald K. Morgan, Geoffrey L. Templeton. 580-586
- A Procedural Interface to TestGregory A. Maston. 587-593
- An Intelligent Software-Integrated Environment of IC TestingYuning Sun, Xiaoming Wang, Wanchun Shi. 594-603
- Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/OJ. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor. 604-613
- A Hybrid Fault Simulator for Synchronous Sequential CircuitsRolf Krieger, Bernd Becker, Martin Keim. 614-623
- Reduced Scan Shift: A New Testing Method for Sequential CircuitYoshinobu Higami, Seiji Kajihara, Kozo Kinoshita. 624-630
- An Integrated Approach for Analog Ciruit Testing with a Minmum Number of Detected ParametersMustapha Slamani, Bozena Kaminska, Guy Quesnel. 631-640
- Analogue Fault Simulation Based on Layout-Dependent Fault ModelsR. J. A. Harvey, Andrew M. D. Richardson, Eric Bruls, Keith Baker. 641-649
- An Analog Multi-Tone Signal Generator for Built-In Self-Test ApplicationsA. K. Lu, Gordon W. Roberts. 650-659
- Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power SolutionAlfred L. Crouch, Rick Ramus, Colin Maunder. 660-669
- An I::DDQ:: Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan EnvironmentChauchin Su, Kychin Hwang, Shyh-Jye Jou. 670-676
- Fault Injection Boundary-Scan Design for Verification of Fault-Tolerant SystemsSavio N. Chau. 677-682
- Ultra Hi-Speed Pin-Electronics and Test Station Using GaAs ICTakashi Sekino, Toshiyuki Okayasu. 683-690
- Achieving +/-30ps Accuracy in the ATE EnvironmentDennis Petrich. 691-700
- A Test-System Architecture to Reduce Transmission Line Effects During High-Speed TestingMarc Mydill. 701-709
- Application of Optoelectronic Techniques to High Speed TestingEwa Sokolowska, Bozena Kaminska. 710-719
- Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICsM. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. 720-728
- Simulation Results of an Efficient Defect-Analysis ProcedureOlaf Stern, Hans-Joachim Wunderlich. 729-738
- The Effect on Quality of Non-Uniform Fault Coverage and Fault ProbabilityPeter C. Maxwell, Robert C. Aitken, Leendert M. Huisman. 739-746
- Application of Joint Time-Frequency Analysis in Mixed-Signal TestingFrank Bouwman, Taco Zwemstra, Sonny Hartanto, Keith Baker, Jan Koopmans. 747-756
- Digitizer Error Extraction in the Nonlinearity TestLuke S. L. Hsieh, Sandeep P. Kumar. 757-762
- An Improved Method of ADC Jitter MeasurementYves Langard, Jean-Luc Balat, Jacques Durand. 763-770
- An On-Line Data Collection and Analysis System for VLSI Devices at Wafer Probe and Final TestGregory W. Papadeas, David Gauthier. 771-780
- Test Station Workcell Controller and Resource Relationship DesignScott A. Erjavic. 781-792
- Calculating Error of Measurement on High-Speed Microprocessor TestTamorah Comard, Madhukar Joshi, Donald A. Morin, Kimberley Sprague. 793-801
- Goal-Directed Vector Generation Using Sample ICsDouglas W. Raymond, Philip J. Stringer, Harold W. Ng, Michael Mitsumata, Robert Burk. 802-810
- NAND Trees Accurately Diagnose Board-Level Pin FaultsGordon D. Robinson. 811-816
- Non-Volatile Programmable Devices and In-Circuit TestDouglas W. Raymond, Dominic F. Haigh, Ray Bodick, Barbara Ryan, Dale McCombs. 817-823
- A Practical System for Mutation Testing: Help for the Common ProgrammerA. Jefferson Offutt. 824-830
- Improving Software Testability with Assertion InsertionHwei Yin, James M. Bieman. 831-839
- Sleuth: A Domain-Based Testing ToolAnneliese Amschler Andrews, Jeff Walls, Richard T. Mraz. 840-849
- Efficient O(sqrt(n)) BIST Algorithms for DDNPS Faults in Dual-Port MemoriesAlaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb. 850-859
- Transparent Memory Testing for Pattern-Sensitive FaultsMark G. Karpovsky, Vyacheslav N. Yarmolik. 860-869
- Generating March Tests AutomaticallyA. J. van de Goor, B. Smit. 870-878
- Concurrent Engineering with DFT in the Digital System: A Parallel ProcessRalph Sanchez. 879-886
- Do You Practice Safe Tests? What We Found Out About Your HabitsCecil A. Dean, Yervant Zorian. 887-892
- Control Strategies for Chip-Based DFT/BIST HardwareDebaditya Mukherjee, Massoud Pedram, Melvin A. Breuer. 893-902
- Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMsMick Tegethoff, Tom Chen. 903-910
- Testing Two Generations of HDTV Decoders - The Impact of Boundary-ScanLars Eerenstein. 911-918
- Structure and Metrology for a Single-wire AnalogYunsheng Lu, Weiwei Mao, Ramaswami Dandapani, Ravi K. Gulati. 919-928
- Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant CircuitsMohammed F. AlShaibi, Charles R. Kime. 929-938
- Configuring Flip-Flops to BIST RegistersAlbrecht P. Stroele, Hans-Joachim Wunderlich. 939-948
- Making the Circular Self-Test Path Technique Effective for Real CircuitsFulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 949-957
- Behavioral-Test Generation using Mixed-Integer Non-linear ProgrammingR. S. Ramchandani, Donald E. Thomas. 958-967
- B-algorithm: A Behavioral-Test Generation AlgorithmChang Hyun Cho, James R. Armstrong. 968-979
- Full-Symbolic ATPG for Large CircuitsGianpiero Cabodi, Paolo Camurati, Stefano Quer. 980-988
- On Synthesizing Circuits With Implicit Testability ConstraintsHenry Cox. 989-998
- A Simulation-Based Protocol-Driven Scan-Test-Design Rule CheckerEdward B. Pitty, Denis Martin, Hi-Kyeung Tony Ma. 999-1006
- On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing SequencesIrith Pomeranz, Sudhakar M. Reddy. 1007-1016
- Integration of Design, Manufacturing and TestingWojciech Maly. 1017
- Navigating Test Access in SystemsLee Whetsel. 1018
- Using SCAN:::TM::: Bridge as an IEEE 1149.1 Protocol Addressable, Multi-Drop, Backplane Test BusJohn Andrews. 1019
- The IEEE P1149.5 MTM-Bus, A Backplane Test and Initialization InterfacePatrick F. McHugh. 1020
- Backplane Test Bus Selection CriteriaCary Champlin. 1021
- 1149.1 Scan Control Transport LevelsRobert Gage. 1022
- Observations on the 1149.x Family of StandardsKenneth P. Parker. 1023
- Optimizing Boundary Scan in a Proprietary EnvironmentWilliam Eklow. 1024