Roger Woods - researchr alias

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2011

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM DetectionXuezheng Chu, John McAllister, Roger Woods. arc 2011: 133-144 [doi]

Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. ProceedingsAndreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, Tarek A. El-Ghazawi, editors, Volume 6578 of Lecture Notes in Computer Science, Springer, 2011. [doi]

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data localityStephen McKeown, Roger Woods. iet-cdt, 5(2):136-144, 2011. [doi]

Real-Valued Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO SystemsC. Zheng, Xuezheng Chu, John McAllister, Roger Woods. tsp, 59(9):4493-4499, 2011. [doi]

2010

Differential Power Analysis of CAST-128Keanhong Boey, Yingxi Lu, Máire O Neill, Roger Woods. isvlsi 2010: 143-148 [doi]

SoC Memory Hierarchy Derivation from Dataflow GraphsScott Fischaber, Roger Woods, John McAllister. vlsisp, 60(3):345-361, 2010. [doi]

Metric-induced optimal embedding for intrinsic 3D shape analysisRongjie Lai, Yonggang Shi, Kevin Scheibel, Scott Fears, Roger Woods, Arthur W. Toga, Tony F. Chan. cvpr 2010: 2871-2878 [doi]

Adapting noisy speech models - Extended uncertainty decodingJianhua Lu, Ji Ming, Roger Woods. icassp 2010: 4322-4325 [doi]

Design of a flexible high-speed FPGA-based flow monitor for next generation networksJohn McGlone, Roger Woods, Alan J. Marshall, Michaela Blott. samos 2010: 37-44 [doi]

Guest Editorial ARC 2009Roger Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan. trets, 4(1):1, 2010. [doi]

2009

2008

2007

2006

2005

FPGA Core Network Implementation and Optimization: A Case StudyScott Fischaber, R. Hasson, John McAllister, Roger Woods. fpt 2005: 319-320

Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous PlatformsJohn McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson. samos 2005: 414-423 [doi]

Programmable Network Functionality for Improved QoS of Interactive Video TrafficBrendan McAllister, Alan Marshall, Roger Woods. ifip6-2 2007: 283-296 [doi]

FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference SchemesErdem Motuk, Roger Woods, Stefan Bilbao. fpt 2005: 103-110

A Novel Packet Marking Function for Real-Time Interactive MPEG-4 Video Applications in a Differentiated Services NetworkShane O Neill, Alan Marshall, Roger Woods. networking 2005: 1031-1042 [doi]

Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receiversLok-Kee Ting, Roger Woods, C. F. N. Cowan. tvlsi, 13(1):86-95, 2005. [doi]

High Speed FPGA-Based Implementations of Delayed-LMS FiltersYing Yi, Roger Woods, Lok-Kee Ting, C. F. N. Cowan. vlsisp, 39(1-2):113-131, 2005. [doi]

2004

Embedded Context Aware Hardware Component Generation for Dataflow System ExplorationJohn McAllister, Roger Woods, Richard Walke. samos 2004: 254-263 [doi]

Guest Editorial: Field Programmable LogicRoger Woods, Russell Tessier. vlsisp, 36(1):5-6, 2004. [doi]

2003

Design of a parameterizable silicon intellectual property core for QR-based RLS filteringGaye Lightbody, Roger Woods, Richard Walke. tvlsi, 11(4):659-678, 2003. [doi]

Design Flow for Efficient FPGA ReconfigurationRichard H. Turner, Roger Woods. fpl 2003: 972-975 [doi]

2002

Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXesTim Courtney, Richard H. Turner, Roger Woods. fccm 2002: 318 [doi]

Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAsRichard H. Turner, Roger Woods, Tim Courtney. fpl 2002: 192-201 [doi]

2001

Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, ProceedingsGordon J. Brebner, Roger Woods, editors, Volume 2147 of Lecture Notes in Computer Science, Springer, 2001.

Development of a Run-Time Reconfiguration System with Low Reconfiguration OverheadJean-Paul Heron, Roger Woods, Sakir Sezer, Richard H. Turner. vlsisp, 28(1-2):97-113, 2001. [doi]

Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures ReceiverLok-Kee Ting, Roger Woods, Colin Cowan. fpl 2001: 367-376 [doi]

2000

An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal ProcessingTim Courtney, Richard H. Turner, Roger Woods. fccm 2000: 341-343 [doi]

Multiplexer Based Reconfiguration for Virtex MultipliersTim Courtney, Richard H. Turner, Roger Woods. fpl 2000: 749-758 [doi]

Linear QR Architecture for a Single Chip Adaptive BeamformerGaye Lightbody, Richard Walke, Roger Woods, John V. McCanny. vlsisp, 24(1):67-81, 2000. [doi]

1999

Accelerating Run-Time Reconfiguration on FCCMsJean-Paul Heron, Roger Woods. fccm 1999: 260-261 [doi]

A Virtual Hardware Handler for RTR SystemsRichard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron. fccm 1999: 262-263 [doi]

1998

The impact of data characteristics and hardware topology on hardware selection for low power DSPGareth Keane, Jonathan Spanier, Roger Woods. islped 1998: 94-96 [doi]

Fast Partial Reconfiguration for FCCMsSakir Sezer, Roger Woods, Jean-Paul Heron, Alan Marshall. fccm 1998: 318-319 [doi]

Applying an XC6200 to Real-Time Image ProcessingRoger Woods, David W. Trainor, Jean-Paul Heron. dt, 15(1):30-38, 1998. [doi]

1997

FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again)Roger Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring. fccm 1997: 155-164 [doi]

1996

Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGAJean-Paul Heron, Roger Woods. fpl 1996: 317-326

Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate ArraysDavid W. Trainor, Roger Woods. fpl 1996: 116-125