Abstract is missing.
- Nanostructure devices for logic and memory and beyondSandip Tiwari. 28-35 [doi]
- Modeling circuits with spins and magnets for all-spin logicBehtash Behin-Aein, Angik Sarkar, Supriyo Datta. 36-40 [doi]
- Organic complementary circuits - Scaling towards low voltage and submicron channel lengthHagen Klauk. 41-45 [doi]
- Design challenges for nano-scale devicesMarc Belleville, Olivier Thomas, Alexandre Valentian, Fabien Clermidy. 69-72 [doi]
- Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETsMasahiro Koyama, Mikaël Casse, Remi Coquand, Sylvain Barraud, Hiroshi Iwai, Gérard Ghibaudo, Gilles Reimbold. 73-76 [doi]
- Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cellsVita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang. 77-80 [doi]
- Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO2 gate stacksYukinori Morita, Shinji Migita, Wataru Mizubayashi, Meishoku Masahara, Hiroyuki Ota. 81-84 [doi]
- Thin germanium dioxide film with a high quality interface formed in a direct neutral beam oxidation processAkira Wada, Seiji Samukawa, Rui Zhang, Shinichi Takagi. 85-88 [doi]
- (100)- and (110)-oriented nMOSFETs with highly scaled EOT in La-silicate/Si interface for multi-gate architectureTakamasa Kawanago, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori Kataoka, A. Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo Hattori, Hiroshi Iwai. 89-92 [doi]
- CMOS compatible ALD high-k double slot grating couplers for on-chip optical interconnectsMaziar M. Naiini, Christoph Henkel, B. Gunnar Malm, Mikael Östling. 93-96 [doi]
- Transport in amorphous materials with applications to phase-change memoriesCarlo Jacoboni, Enrico Piccinini, Fabrizio Buscemi. 97-100 [doi]
- Geometry based resistance model for phase change memoryK. C. Kwong, Philip K. T. Mok, Mansun Chan. 101-104 [doi]
- Drain-conductance optimization in nanowire TFETsElena Gnani, Susanna Reggiani, Antonio Gnudi, Giorgio Baccarani. 105-108 [doi]
- Comprehensive statistical comparison of RTN and BTI in deeply scaled MOSFETs by means of 3D 'atomistic' simulationSalvatore M. Amoroso, Louis Gerrer, Stanislav Markov, Fikru Adamu-Lema, Asen Asenov. 109-112 [doi]
- Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell designXingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Asen Asenov. 113-116 [doi]
- Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cellsValentina Bonfiglio, Giuseppe Iannaccone. 117-120 [doi]
- Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunitiesVeeresh Deshpande, Sylvain Barraud, Xavier Jehl, Romain Wacquez, Maud Vinet, Remi Coquand, B. Roche, B. Voisin, F. Triozon, C. Vizioz, L. Tosti, Bernard Previtali, P. Perreau, T. Poiroux, Marc Sanquer, Olivier Faynot. 121-124 [doi]
- Active strain modulation in field effect devicesTom van Hemert, Raymond J. E. Hueting. 125-128 [doi]
- Static and low frequency noise characterization of densely packed CNT-TFTsMin-Kyu Joo, Un Jeong Kim, Dae-Young Jeon, So-Jeong Park, Mireille Mouis, Gyu-Tae Kim, Gérard Ghibaudo. 129-132 [doi]
- Mechanically flexible double gate a-IGZO TFTsNiko Munzenrieder, Christoph Zysset, Thomas Kinkeldei, Luisa Petti, Giovanni A. Salvatore, Gerhard Tröster. 133-136 [doi]
- Top-down fabricated ZnO nanowire transistors for application in biosensorsSuhana M. Sultan, Kai Sun, Maurits R. R. de Planque, Peter Ashburn, H. M. H. Chong. 137-140 [doi]
- Manufacturing aspects of an ultra-thin chip technologyEvangelos A. Angelopoulos, Muhammad S. Al-Shahed, Wolfgang Appel, Stefan Endler, Saleh Ferwana, Christine Harendt, Mahadi-Ul Hassan, Horst Rempp, Martin Zimmermann, Joachim N. Burghartz. 141-144 [doi]
- +n diodes at 400 ºC by Aluminum-Induced CrystallizationAgata Sakic, Lin Qi, Tom L. M. Scholtes, Johan van der Cingel, Lis K. Nanver. 145-148 [doi]
- Current-voltage characteristics of vertical diodes for next generation memoriesHokyun An, Kong-Soo Lee, Yoongoo Kang, Seonghoon Jeong, Wonseok Yoo, Jae-Jong Han, Bonghyun Kim, Hanjin Lim, Seokwoo Nam, Gi-Tae Jeong, Ho-Kyu Kang, Chilhee Chung, Byoungdeog Choi. 149-152 [doi]
- A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performanceYin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang. 157-160 [doi]
- Tunnel FET with non-uniform gate capacitance for improved device and circuit level performanceCem Alper, Luca De Michielis, Nilay Dagtekin, Livio Lattanzio, Adrian M. Ionescu. 161-164 [doi]
- From FinFET to nanowire ISFETMichal Zaborowski, Daniel Tomaszewski, Piotr Dumania, Piotr Grabiec. 165-168 [doi]
- Micro- and nano-link ultra-low power heaters for sensorsAlfons W. Groenland, Elizaveta Vereshchagina, Alexey Y. Kovalgin, Rob A. M. Wolters, J. G. E. Gardeniers, J. Schmitz. 169-172 [doi]
- High performance printed N and P-type OTFTs for complementary circuits on plastic substrateStéphanie Jacob, Mohamed Benwadih, Jacqueline Bablet, Isabelle Chartier, Romain Gwoziecki, Sahel Abdinia, Eugenio Cantatore, Lidia Maddiona, Francesca Tramontana, Giorgio Maiellaro, Luigi Mariucci, Giuseppe Palmisano, Romain Coppard. 173-176 [doi]
- A gate-last In0.53Ga0.47As channel FinFET with Molybdenum source/drain contactsXingui Zhang, Hua Xin Guo, Xiao Gong, Yee-Chia Yeo. 177-180 [doi]
- Complementary RF-LDMOS transistors realized with standard CMOS implantationsAndreas Mai, Holger Rücker. 181-184 [doi]
- Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped Nisi2 tunnel junctionsLars Knoll, Qing-Tai Zhao, Stefan Trellenkamp, Anna Schäfer, K. K. Bourdelle, S. Mantl. 183-156 [doi]
- TCAD degradation modeling for LDMOS transistorsSusanna Reggiani, Gaetano Barone, Elena Gnani, Antonio Gnudi, S. Poli, M.-Y. Chuang, W. Tian, R. Wise. 185-188 [doi]
- Pulsed I(V) - pulsed RF measurement system for microwave device characterization with 80ns/45GHzMario Weis, Sébastien Fregonese, Marco Santorelli, Amit Kumar Sahoo, Cristell Maneux, Thomas Zimmer. 189-192 [doi]
- 2 cell for sub 30nm DRAM technologyYoungseung Cho, Yoosang Hwang, Huijung Kim, Eunok Lee, Soojin Hong, Hyun-Woo Chung, Daeik Kim, Jinyoung Kim, Yong-Chul Oh, Hyeongsun Hong, Gyo-Young Jin, Chilhee Chung. 193-196 [doi]
- 2-FET used as 1-transistor high-speed DRAMJing Wan, Cyrille Le Royer, Alexander Zaslavsky, Sorin Cristoloveanu. 197-200 [doi]
- A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvementQi Li, Bo Wang, Tony T. Kim. 201-204 [doi]
- An advanced statistical compact model strategy for SRAM simulation at reduced VDDPlamen Asenov, Dave Reid, Scott Roy, Campbell Millar, Asen Asenov. 205-208 [doi]
- Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFETCarlos Navarro, Noel Rodriguez, Luca Donetti, Akiko Oliata, F. Gamiz, François Andrieu, Olivier Faynot, Claire Fenouillet-Béranger, Sorin Cristoloveanu. 209-212 [doi]
- The role of the temperature on the scattering mechanisms limiting the electron mobility in metal-oxide-semiconductor field-effect-transistors fabricated on (110) silicon-oriented wafersPhilippe Gaubert, Akinobu Teramoto, Shigetoshi Sugawa, Tadahiro Ohmi. 213-216 [doi]
- New parameter extraction method based on split C-V for FDSOI MOSFETsImed Ben Akkez, Antoine Cros, Claire Fenouillet-Béranger, Frédéric Boeuf, Q. Rafhay, Francis Balestra, G. Ghibaudo. 217-220 [doi]
- Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniquesChristoph Kerner, Ivan Ciofi, Thomas Chiarella, Stefaan Van Huylenbroeck. 221-225 [doi]
- A gate Modulated avalanche bipolar transistor in 130nm CMOS technologyRobert K. Henderson, Eric A. G. Webster, Richard J. Walker. 226-229 [doi]
- Low-noise and large-area CMOS SPADs with timing response free from slow tailsDanilo Bronzi, Federica A. Villa, Simone Bellisai, Bojan Markovic, Simone Tisa, Alberto Tosi, Franco Zappa, Sascha Weyers, Daniel Durini, Werner Brockherde, Uwe Paschen. 230-233 [doi]
- Extreme temperature 4H-SiC metal-semiconductor-metal ultraviolet photodetectorsWei-Cheng Lien, Albert P. Pisano, Dung-Sheng Tsai, Jr-Hau He, Debbie G. Senesky. 234-237 [doi]
- A silicon photomultiplier with >30% detection efficiency from 450-750nm and 11.6μm pitch NMOS-only pixel with 21.6% fill factor in 130nm CMOSEric A. G. Webster, Richard J. Walker, Robert K. Henderson, Lindsay Grant. 238-241 [doi]
- Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacksRomain Ritzenthaler, Tom Schram, Erik Bury, Jérôme Mitard, L.-Å. Ragnarsson, Guido Groeseneken, N. Horiguchi, A. Thean, A. Spessot, C. Caillat, V. Srividya, P. Fazan. 242-245 [doi]
- On the UTBB SOI MOSFET performance improvement in quasi-double-gate regimeValeria Kilchytska, Denis Flandre, François Andrieu. 246-249 [doi]
- An integration approach for graphene double-gate transistorsSam Vaziri, Anderson D. Smith, Christoph Henkel, Mikael Östling, Max C. Lemme, Grzegorz Lupina, Gunther Lippert, Jarek Dabrowski, Wolfgang Mehr. 250-253 [doi]
- MTJ-based implication logic gates and circuit architecture for large-scale spintronic stateful logic systemsHiwa Mahmoudi, Viktor Sverdlov, Siegfried Selberherr. 254-257 [doi]
- Resistive switching memory using titanium-oxide nanoparticle filmsEmanuele Verrelli, Dimitris Tsoukalas, Pascal Normand, Nikos Boukos, A. H. Kean. 258-261 [doi]
- An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETsPulkit Jain, John Keane, Chris H. Kim. 262-265 [doi]
- Unified characterization of RTN and BTI for circuit performance and variability simulationNuria Ayala, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, X. Aymerich. 266-269 [doi]
- Kink effect characterization in AlGaN/GaN HEMTs by DC and drain current transient measurementsLaurent Brunel, Nathalie Malbert, Arnaud Curutchet, Nathalie Labat, B. Lambert. 270-273 [doi]
- Random Telegraph Signal noise properties of HfOx RRAM in high resistive stateFrancesco M. Puglisi, Paolo Pavan, Andrea Padovani, Luca Larcher, Gennadi Bersuker. 274-277 [doi]
- On the impact of Ag doping on performance and reliability of GeS2-based Conductive Bridge MemoriesElisa Vianello, Carlo Cagli, Gabriel Molas, Emeline Souchier, P. Blaise, C. Carabasse, G. Rodriguez, V. Jousseaume, B. De Salvo, F. Longnos, F. Dahmani, P. Verrier, D. Bretegnier, J. Liebault. 278-281 [doi]
- Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and writeLeqi Zhang, Stefan Cosemans, Dirk J. Wouters, Guido Groeseneken, Malgorzata Jurczak. 282-285 [doi]
- Carbon-doped Ge2Sb2Te5 phase-change memory devices featuring reduced RESET current and power consumptionQuentin Hubert, Carine Jahan, Alain Toffoli, Gabriele Navarro, S. Chandrashekar, P. Noe, V. Sousa, L. Perniola, J.-F. Nodin, A. Persico, S. Maitrejean, A. Roule, E. Henaff, M. Tessaire, P. Zuliani, R. Annunziata, Gilles Reimbold, G. Pananakakis, B. De Salvo. 286-289 [doi]
- Transport properties of strained silicon nanowiresYann-Michel Niquet, Christophe Delerue, Viet Hung Nguyen, Christophe Krzeminski, Francois Triozon. 290-293 [doi]
- Tin nanowire field effect transistorLida Ansari, Giorgos Fagas, James C. Greer. 294-297 [doi]
- Effects of disorder on transport properties of extremely scaled graphene nanoribbonsMirko Poljak, Emil B. Song, Minsheng Wang, Tomislav Suligoj, Kang L. Wang. 298-301 [doi]
- High temperature behaviour of GaN-on-Si high power MISHEMT devicesDirk Wellekens, Rafael Venegas, Xuanwu Kang, Mohammed Zahid, Tian-Li Wu, Denis Marcon, Puneet Srivastava, Marleen Van Hove, Stefaan Decoutere. 302-305 [doi]
- High voltage low Ron in-situ SiN/Al0.35GaN0.65/GaN-on-Si power HEMTs operation up to 300°CAbel Fontserè, Amador Pérez-Tomás, Philippe Godignon, José Millán, J. M. Parsey, P. Moens. 306-309 [doi]
- Critical gate module process enabling the implementation of a 50A/600V AlGaN/GaN MOS-HEMTSameh G. Khalil, Rongming Chu, Ray Li, Danny Wong, Scott Newell, Xu Chen, M. Chen, D. Zehnder, S. Kim, A. Corrion, B. Hughes, K. Boutros, C. Namuduri. 310-313 [doi]
- Scaling of InAlN/GaN power transistorsDaniel Piedra, Hyung Seok Lee, Tomas Palacios, Xiang Gao, Shiping Guo. 314-317 [doi]
- Deterministic simulation of 3D and quasi-2D electron and hole systems in SiGe devicesChristoph Jungemann, Sung-Min Hong, Bernd Meinerzhagen, Anh-Tuan Pham. 318-321 [doi]
- A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETsDaniel Lizzit, Pierpaolo Palestri, David Esseni, Francesco Conzatti, Luca Selmi. 322-325 [doi]
- Electron transport in germanium junctionless nanowire transistorsPedram Razavi, Giorgos Fagas, Isabelle Ferain, Ran Yu, Samaresh Das. 326-329 [doi]
- Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETsTommaso Romeo, Luigi Pantisano, Eddy Simoen, Raymond Krom, M. Togo, N. Horiguchi, Jérôme Mitard, A. Thean, Guido Groeseneken, Cor Claeys, Felice Crupi. 330-333 [doi]
- Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETsChristoforos Theodorou, Eleftherios G. Ioannidis, Sébastien Haendler, Nicolas Planes, Franck Arnaud, Jalal Jomaah, Charalambos A. Dimitriadis, Gérard Ghibaudo. 334-337 [doi]
- On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETsEddy Simoen, Marc Aoulaiche, Anabela Veloso, M. Jurczak, Cor Claeys, L. Mendes Almeida, M. G. C. Andrade, A. Luque Rodriguez, J. A. Jimenez Tejada, C. Caillat, P. Fazan. 338-341 [doi]
- Effect of substrate bias on frequency dependence of MOSFET noise intensityKenji Ohmori, Ranga Hettiarachchi, Keisaku Yamada. 342-345 [doi]