External Links

    Journal: J. Solid-State Circuits

    Volume 58, Issue 9

    2403 -- 0Dennis Sylvester. New Associate Editor
    2404 -- 0Dennis Sylvester. New Associate Editor
    2405 -- 2406Yuriy M. Greshishchev. Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium
    2407 -- 2420Sidharth Thomas, Sam Razavian, Wei Sun, Benyamin Fallahi Motlagh, Anthony D. Kim, Yu Wu, Benjamin S. Williams, Aydin Babakhani. A 0.4-4 THz p-i-n Diode Frequency Multiplier in 90-nm SiGe BiCMOS
    2421 -- 2429Utku Soylu, Amirreza Alizadeh, Munkyo Seo, Mark J. W. Rodwell. 280-GHz Frequency Multiplier Chains in 250-nm InP HBT Technology
    2430 -- 2440Justin Romstadt, Ahmad Zaben, Hakan Papurcu, Pascal Stadler, Tobias Welling, Klaus Aufinger, Nils Pohl. A 117.5-155-GHz SiGe ×12 Frequency Multiplier Chain With Push-Push Doublers and a Gilbert Cell-Based Tripler
    2441 -- 2450Kevin W. Kobayashi, Paul Partyka, Tim Howle, Tony Sellas, Leonard Hayden. dc LFOM at 48 GHz
    2451 -- 2465Hao Wang 0079, Hamidreza Afzal, Omeed Momeni. A Highly Accurate and Sensitive mmWave Displacement-Sensing Doppler Radar With a Quadrature-Less Edge-Driven Phase Demodulator
    2466 -- 2477Francesco Tesolin, Simone Mattia Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
    2478 -- 2488Sumit Pratap Singh, Timo Rahkonen, Marko E. Leinonen, Aarno Pärssinen. max/2in Sub-THz/THz Frequencies
    2489 -- 2500Yiyu Shen, Martijn Hoogelander, Rob Bootsman, Morteza S. Alavi, Leo C. N. de Vreede. A Wideband Digital-Intensive Current-Mode Transmitter Line-Up
    2501 -- 2512Miao Meng, Manideep Dunna, Shihkai Kuo, Hans Chinghan Yu, Po-Han Peter Wang, Dinesh Bharadia, Patrick P. Mercier. A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range
    2513 -- 2525David Murphy, Dihang Yang, Hooman Darabi, Arya Behzad. A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise
    2526 -- 2542Zhong Gao, Martin Fritz, Gerd Spalink, Robert Bogdan Staszewski, Masoud Babaie. A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion
    2543 -- 2553Dan Shi, Ka-Meng Lei, Rui Paulo Martins, Pui-In Mak. 2 Resolution FoM in 65-nm CMOS
    2554 -- 2563Yuekang Guo, Jing Jin 0005, Xiaoming Liu 0008, Jianjun Zhou. A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization
    2564 -- 2574Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun. A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier
    2575 -- 2584Zhaonan Lu, Huaikun Ji, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan. A 1 V 1.07 μW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC
    2585 -- 2596Alexander S. Delke, Thomas J. Hoen, Anne-Johan Annema, Yanyu Jin, Jos Verlinden, Bram Nauta. A Single-Trim Frequency Reference System With 0.7 ppm/°C From -63 °C to 165 °C Consuming 210 μW at 70 MHz
    2597 -- 2606Xinling Yue, Sijun Du. A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting
    2607 -- 2618Peng Guo, Fabian Fool, Zu-yao Chang, Emile Noothout, Hendrik J. Vos, Johan G. Bosch, Nico de Jong, Martin D. Verweij, Michiel A. P. Pertijs. A 1.2-mW/Channel Pitch-Matched Transceiver ASIC Employing a Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3-D Ultrasound Imaging
    2619 -- 2631Tan-Tan Zhang, Hyunwoo Son, Jianming Zhao, Chun-Huat Heng, Yuan Gao 0011. A 26.6-119.3-μW 101.9-dB SNR Direct Digitization Bio-Impedance Readout IC
    2632 -- 2647Pouyan Keshavarzian, Karthick Ramu, Duy Tang, Carlos Weill, Francesco Gramuglia, Shyue Seng Tan, Michelle Tng, Louis Lim, Elgin Quek, Denis Mandich, Mario Stipcevic, Edoardo Charbon. A 3.3-Gb/s SPAD-Based Quantum Random Number Generator
    2648 -- 2658Xiangxing Yang, Nan Sun. A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion
    2659 -- 2667Yong-Un Jeong, Joo-Hyung Chae, Suhwan Kim. A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces

    Volume 58, Issue 8

    2127 -- 0Dennis Sylvester. New Associate Editor
    2128 -- 0Dennis Sylvester. New Associate Editor
    2129 -- 2140Hossein Razavi, Behzad Razavi. A Study of Injection Locking in Oscillators and Frequency Dividers
    2141 -- 2156Onur Memioglu, Yu Zhao, Behzad Razavi. A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation
    2157 -- 2172Mohammad Ali Montazerolghaem, Leo C. N. de Vreede, Masoud Babaie. A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications
    2173 -- 2188Zhen Yang, Kaixue Ma, Fanyi Meng, Bing Liu. OUT in 55-nm Bulk CMOS
    2189 -- 2201Johan Nguyen, Khaled Khalaf, Xinyan Tang, Steven Brebels, Kristof Vaesen, Mithlesh Shrivas, Piet Wambacq. Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS
    2202 -- 2213Abdelrahman H. Ahmed, Leonardo Vera, Lorenzo Iotti, Ruizhi Shi, Sudip Shekhar, Alexander V. Rylyakov. A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength
    2214 -- 2225Joep Zanen, Eric A. M. Klumperink, Bram Nauta. A Predistortion-Less Digital MIMO Transmitter With DTC-Based Quadrature Imbalance Compensation
    2226 -- 2238Longjie Zhong, Shubin Liu, Pengpeng Shang, Wenfei Cao, Zhangming Zhu. A 100- to- 10-kHz 5.4- to- 216- μW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for MEMS Capacitive Accelerometer
    2239 -- 2251Martin Lefebvre 0002, Denis Flandre, David Bol. A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI
    2252 -- 2266Yizhuo Wang, Jiahe Shi, Hao Xu 0005, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao 0001, Hao Min, Na Yan. Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL
    2267 -- 2277Soumen Mohapatra, Chung-Ching Lin, Subhanshu Gupta, Deukhyoun Heo. Low-Power Process and Temperature-Invariant Constant Slope-and-Swing Ramp-Based Phase Interpolator
    2278 -- 2287Fabio Severini, Iris Cusini, Francesca Madonini, Davide Brescia, Robin Camphausen, Álvaro Cuevas, Simone Tisa, Federica A. Villa. Spatially Resolved Event-Driven 24 × 24 Pixels SPAD Imager With 100% Duty Cycle for Low Optical Power Quantum Entanglement Detection
    2288 -- 2299Marcel Runge, Julius Edler, Tobias Kaiser, Kai Misselwitz, Friedel Gerfers. An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter
    2300 -- 2313Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, Il-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo. A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET
    2314 -- 2325Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae Kang Jung, Chulwoo Kim. A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces
    2326 -- 2336Qian Liu, Li Du, Yuan Du. A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects
    2337 -- 2348Chao Xie, Guangshu Zhao, Yuan Ma, Man Kay Law, Milin Zhang. Fully Integrated Frequency-Tuning Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting
    2349 -- 2359Travis Forbes, Benjamin Magstadt, Jesse Moody, Justine Saugen, Andrew Suchanek, Spencer Nelson. 2 Area Efficiency
    2360 -- 2371Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst. TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge
    2372 -- 2382Chengshuo Yu, Junjie Mu, Yuqi Su, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim. A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array
    2383 -- 2398Archisman Ghosh, Jose Maria Bermudo Mera, Angshuman Karmakar, Debayan Das, Santosh Ghosh, Ingrid Verbauwhede, Shreyas Sen. 2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom-Cook Multiplication

    Volume 58, Issue 7

    1823 -- 1824Makoto Nagata, Massimo Alioto. Guest Editorial IEEE 2022 European Solid-State Circuits Conference
    1825 -- 1837Chao Chen, Dan Huang, Yan Zhao, Yuemin Jin, Jun Yang 0006. An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3
    1838 -- 1849Daniel Krüger, Aoyang Zhang, Behdad Aghelnejad, Henry Hinton, Victor Marrugat Arnal, Yi-Qiao Song, Yiqiao Tang, Ka-Meng Lei, Jens Anders, Donhee Ham. A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging
    1850 -- 1859Si-Yi Li, Sheng-Cheng Lee, Sheng-Hsi Hung, Zheng-Lun Huang, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. A 4-40 V Wide Input Range Boost Converter With the Protection Re-Cycling Technique for 200 W High Power LiDAR System in a Long-Distance Object Detection
    1860 -- 1870Sehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung. Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices
    1871 -- 1884Adrian Kneip, Martin Lefebvre 0002, Julien Verecken, David Bol. 2 CIM-SRAM With Multi-Bit Analog Batch-Normalization
    1885 -- 1897Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo. A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity
    1898 -- 1912Naga Sasikanth Mannem, Jeongsoo Park, Elham Erfani, Edward Liu, Jeongseok Lee, Hua Wang 0006. A Reconfigurable Phase-Time Array Transmitter Achieving Keyless Secured Transmission and Multi-Receiver Localization for Low-Latency Joint Communication and Sensing
    1913 -- 1927Zekun Li, Jixin Chen, Huanbo Li, Jiayang Yu, Yuxiang Lu, Rui Zhou, Zhe Chen, Wei Hong 0002. A 220-GHz Sliding-IF Quadrature Transmitter and Receiver Chipset for High Data Rate Communication in 0.13-µm SiGe BiCMOS
    1928 -- 1944Reza Ehsani Alashti, Shahabeddin Mohin, Fatemeh Tavana, Mehrdad Sharif Bakhtiar. Digital to RF Wideband Multi-Standard Multi-Path Transmitter
    1945 -- 1958Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, AnDing Zhu. A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness
    1959 -- 1972Chao Li, Jinhua Guo, Pei Qin, Quan Xue. A Wideband Mode-Switching Quad-Core VCO Using Compact Multi-Mode Magnetically Coupled LC Network
    1973 -- 1986Sandeep Hari, Cody J. Ellington, Brian A. Floyd. A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz
    1987 -- 2004Alok Sethi, Rehman Akbar, Mikko Hietanen, Janne P. Aikio, Olli Kursu, Markku Jokinen, Marko E. Leinonen, Timo Rahkonen, Aarno Pärssinen. Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays
    2005 -- 2015Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim. A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces
    2016 -- 2027Gerd Kiene, Ramon W. J. Overwater, Alessandro Catania, Aishwarya Gunaputi Sreenivasulu, Paolo Bruschi, Edoardo Charbon, Masoud Babaie, Fabio Sebastiano. A 1-GS/s 6-8-b Cryo-CMOS SAR ADC for Quantum Computing
    2028 -- 2039Shuhao Fan, Qi Zhou, Ka-Meng Lei, Pui-In Mak, Rui Paulo Martins. 3 Field of View
    2040 -- 2052Chan Sam Park, Hyunjoong Kim, Kwangmuk Lee, Dae Sik Keum, Dong Pyo Jang, Jae-Joon Kim. A Baseline-Tracking Single-Channel I/Q Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring
    2053 -- 2063Zhuhao Li, Changgui Yang, Yunshan Zhang, Ting-Hsun Wang, Ziyi Chang, Boyu Zhu, Lin Zhou, Yuxuan Luo, Bin Su, Bo Zhao 0003. A 1 mm ×1 mm CGM System on Die Achieving 1.65-nA/mM In Vivo Resolution and 0-40-mM/L Detection Range With ΔΣ Backscatter Technique
    2064 -- 2074Kyu-Sang Park, Amr Khashaba, Ahmed E. AbdelRahman, Yongxin Li, Tianyu Wang 0006, Ruhao Xia, Nilanjan Pal, Pavan Kumar Hanumolu. A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From40 °C to 95 °C
    2075 -- 2086Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda. 2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
    2087 -- 2097Yan He, Dai Li, Zhanghao Yu, Kaiyuan Yang 0001. ASCH-PUF: A "Zero" Bit Error Rate CMOS Physically Unclonable Function With Dual-Mode Low-Cost Stabilization
    2098 -- 2108Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi. Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing
    2109 -- 2124Rishabh Sehgal, Tanmay Thareja, Shanshan Xie, Can Ni, Jaydeep P. Kulkarni. A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

    Volume 58, Issue 6

    1507 -- 0Dennis Sylvester. New Associate Editor
    1508 -- 1518Stephen Weinreich, Boris Murmann. A 0.6-1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer
    1519 -- 1534Paula Palacios, Mohamed Saeed, Renato Negra. Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS
    1535 -- 1551David Joseph Munzer, Naga Sasikanth Mannem, Jeongseok Lee, Hua Wang 0006. Broadband mm-Wave Current/Voltage Sensing-Based VSWR-Resilient True Power/Impedance Sensor Supporting Single-Ended Antenna Interfaces
    1552 -- 1571Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie. A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit
    1572 -- 1585Naga Sasikanth Mannem, Elham Erfani, Tzu-Yuan Huang, Hua Wang 0006. A mm-Wave Frequency Modulated Transmitter Array for Superior Resolution in Angular Localization Supporting Low-Latency Joint Communication and Sensing
    1586 -- 1596Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx. Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout
    1597 -- 1609Yu Zhao, Mahdi Forghani, Behzad Razavi. A 20-GHz PLL With 20.9-fs Random Jitter
    1610 -- 1622Qian Chen 0027, Chirn Chye Boon, Qing Liu 0005, Yuan Liang. A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS
    1623 -- 1635Amit Kumar Mishra, Yifei Li, Pawan Agarwal, Sudip Shekhar. Improving Linearity in CMOS Phase Interpolators
    1636 -- 1645Lingxin Meng, Yaopeng Hu, YiBo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan. A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC
    1646 -- 1656Yuyan Liu, Menglian Zhao, YiBo Zhao, Xiaopeng Yu, Nianxiong Nick Tan, Le Ye, Zhichao Tan. A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC
    1657 -- 1666Sujin Park, Hyungil Chae, SeongHwan Cho. rms Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS
    1667 -- 1680Keun-Mok Kim, Kyung-Sik Choi, Hyunki Jung, Byeonghun Yun, Jinglong Xu, Jinho Ko, Sang-Gug Lee 0001. A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency
    1681 -- 1692Xianbo Li, Hengbo Wang, Jianping Zhu, C. Patrick Yue. Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-Per-Second Optical Wireless Communication
    1693 -- 1705Peng Guo, Zu-yao Chang, Emile Noothout, Hendrik J. Vos, Johan G. Bosch, Nico de Jong, Martin D. Verweij, Michiel A. P. Pertijs. A Pitch-Matched Low-Noise Analog Front-End With Accurate Continuous Time-Gain Compensation for High-Density Ultrasound Transducer Arrays
    1706 -- 1718Inho Park, Jinwoo Jeon, Hyunjin Kim, Taehyeong Park, Junwon Jeong, Chulwoo Kim. A Thermoelectric Energy-Harvesting Interface With Dual-Conversion Reconfigurable DC-DC Converter and Instantaneous Linear Extrapolation MPPT Method
    1719 -- 1734Panagiotis G. Zarkos, Sidney Buchbinder, Christos G. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, Jake Whinnery, Pavan Bhargava, Vladimir Stojanovic. Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Applications in a Zero-Change 45-nm CMOS-SOI Process
    1735 -- 1745Qinjing Pan, Tianxiang Qu, Biao Tang, Fei Shan, Zhiliang Hong, Jiawei Xu 0001. A 0.5-mΩ/√Hz Dry-Electrode Bioimpedance Interface With Current Mismatch Cancellation and Input Impedance of 100 MΩ at 50 kHz
    1746 -- 1757Xianglong Bai, Yan Lu 0002, Chenchang Zhan, Rui Paulo Martins. A 6.78-MHz Wireless Power Transfer System With Inherent Wireless Phase Shift Control Without Feedback Data Sensing Coil
    1758 -- 1768Guigang Cai, Yan Lu 0002, Rui P. Martins. An SC-Parallel-Inductor Hybrid Buck Converter With Reduced Inductor Voltage and Current
    1769 -- 1781Jonghyun Oh, Young Ha Hwang, Jun-Eun Park, Mingoo Seok, Deog Kyoon Jeong. An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector
    1782 -- 1797Ivan Miro Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy. SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration
    1798 -- 1809Fengbin Tu, Zihan Wu 0006, Yiqi Wang 0005, Ling Liang, Liu Liu 0017, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie 0001, Shouyi Yin. TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes
    1810 -- 1819Sheng-Jung Yu, Yu-Chi Lee, Liang-Hsin Lin, Chia-Hsiang Yang. An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices

    Volume 58, Issue 5

    1199 -- 1200Hossein Hashemi 0001, Qun Jane Gu. Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium
    1201 -- 1211Ce Yang, Shiyu Su, Mike Shuo-Wei Chen. Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter
    1212 -- 1227Samir Nooshabadi, Parham Porsandeh Khial, Austin Fikes, Ali Hajimiri. A 28-GHz, Multi-Beam, Decentralized Relay Array
    1228 -- 1240Tzu-Yuan Huang, Boce Lin, Naga Sasikanth Mannem, Basem Abdelaziz Abdelmagid, Hua Wang 0006. A Time-Modulated Concurrent Steerable Multibeam MIMO Receiver Array With Spectral-Spatial Mapping Using One Beamformer and Single-Wire Interface
    1241 -- 1255Hongxin Tang, Huizhen Jenny Qian, Bingzheng Yang, Xun Luo. A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM
    1256 -- 1270Xiaohan Zhang, Sensen Li, Daquan Huang, Taiyun Chi. A Millimeter-Wave Three-Way Doherty Power Amplifier for 5G NR OFDM
    1271 -- 1284Kyumin Kwon, Omar A. B. Abdelatty, David D. Wentzloff. PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter
    1285 -- 1298Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Timothy F. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae Young Yang, Johanny Escober-Pelaez, Shuhei Yamada, Kenneth P. Foust, Brent R. Carlton. A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks
    1299 -- 1309Feng Qiu, Haoshen Zhu, Wenquan Che, Quan Xue. A K-Band Full 360° Phase Shifter Using Novel Non-Orthogonal Vector Summing Method
    1310 -- 1322Alper Karakuzulu, Wael Abdullah Ahmad, Dietmar Kissinger, Andrea Malignaggi. A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
    1323 -- 1336Hany Abolmagd, Raghav Subbaraman, Omid Esmaeeli, Yeswanth Guntupalli, Ahmad Sharkia, Dinesh Bharadia, Sudip Shekhar. A Hierarchical Self-Interference Canceller for Full-Duplex LPWAN Applications Achieving 52-70-dB RF Cancellation
    1337 -- 1349Kai Tang 0002, Chuanshi Yang, Yanshu Guo, Nan Wang, Yao Zhu, Ying Zhang, Eldwin Jiaqiang Ng, Joshua En-Yuan Lee, Zhongyuan Fang, Wensong Wang, Hanjun Jiang, Chun-Huat Heng, Yuanjin Zheng. A 107 pJ/b TX 260 pJ/b RX Ultralow-Power MEMS-Based Transceiver With Wake-Up in ISM-Bands for IoT Applications
    1350 -- 1361Tuomo Talala, Eetu Parkkinen, Ilkka Nissinen. CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy
    1362 -- 1375Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie. A Cryo-CMOS PLL for Quantum Computing Applications
    1376 -- 1385Sajjad Moazeni, Kevin Renehan, Eric H. Pollmann, Kenneth L. Shepard. An Integrated-Circuit Node for High-Spatiotemporal Resolution Time-Domain Near-Infrared Diffuse Optical Tomography Imaging Arrays
    1386 -- 1399Mohamed Megahed, Tejasvi Anand. A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS
    1400 -- 1413Min-Woo Ko, Hyunki Han, Hyun-Sik Kim. A Bipolar-Output Switched-Capacitor DC-DC Boost Converter With Residual-Energy-Recycling Regulation and Low Dropout Post-Filtering Techniques
    1414 -- 1424Woosong Jung, KwangHo Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog Kyoon Jeong. A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS
    1425 -- 1435Koen Goetschalckx, Fengfeng Wu, Marian Verhelst. DepFiN: A 12-nm Depth-First, High-Resolution CNN Processor for IO-Efficient Inference
    1436 -- 1449Bo Zhang, Shihui Yin, Minkyu Kim 0001, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok. PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference
    1450 -- 1461Xiangxing Yang, Keren Zhu 0001, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun. An In-Memory-Computing Charge-Domain Ternary CNN Classifier
    1462 -- 1471Zhengguo Shen, Weiwei Shan, Yuxuan Du, Ziyu Li, Jun Yang 0006. Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss
    1472 -- 1486Zhiting Lin, Zhongzhen Tong, Fangming Wang, Jin Zhang, Yue Zhao, Peng Sun, Tian Xu, Cheng Zhang, Xingwei Li, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao 0007, Junning Chen. In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations
    1487 -- 1495Chun-Yen Yao, Tsung-Yen Wu, Han-Chung Liang, Yu-Kai Chen, Tsung-Te Liu. A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing
    1496 -- 1504Gicheol Shin, Eunyoung Lee, Jongmin Lee, Yongmin Lee, Yoonmyung Lee. A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-Voltage, Low-Power Applications

    Volume 58, Issue 4

    895 -- 0Dennis Sylvester. New Associate Editor
    896 -- 0Dennis Sylvester. New Associate Editor
    897 -- 900Borivoje Nikolic, Mototsugu Hamada. Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits
    901 -- 914Zheng Li, Jian Pang, Yi Zhang 0092, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Yun Wang 0008, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Jeehoon Park, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada. A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station
    915 -- 928Yimai Peng, Gordy Carichner, Yejoong Kim, Li-Yu Chen, Rémy Tribhout, Benoît Piranda, Julien Bourgeois, David T. Blaauw, Dennis Sylvester. A High-Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter
    929 -- 938Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn. An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer
    939 -- 948Hanyue Li, Yuting Shen, Eugenio Cantatore, Pieter Harpe. m-C Integrator
    949 -- 960Xiaolin Yang, Marco Ballini, Chutham Sawigun, Wen-Yang Hsu, Jan-Willem Weijers, Jan Putzeys, Carolina Mora Lopez. An AC-Coupled 1st-Order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition
    961 -- 971Hyunchul Yoon, Changuk Lee, Taewoong Kim, Yigi Kwon, Youngcheol Chae. A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier
    972 -- 982Amy Whitcombe, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull. A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW
    983 -- 992Kunihiro Hatakeyama, Yu Okubo, Tomohiro Nakagome, Masahiro Makino, Hiroshi Takashima, Takahiro Akutsu, Takehide Sawamoto, Masanori Nagase, Tatsuo Noguchi, Shoji Kawahito. A Hybrid ToF Image Sensor for Long-Range 3D Depth Measurement Under High Ambient Light Conditions
    993 -- 1001Wei-Jhih Jian, Wei-Zen Chen. A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration
    1002 -- 1014Minxiang Gong, Hua Chen, Xin Zhang 0025, Rinkle Jain, Arijit Raychowdhury. A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer
    1015 -- 1024Luya Zhang, Ali M. Niknejad. GalEPR: A Galvanically Coupled Electron Paramagnetic Resonance Spectrometer for Deep Tissue Hypoxia Diagnosis
    1025 -- 1036Subhajit Ray, Peter R. Kinget. Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification
    1037 -- 1050Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton. A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference
    1051 -- 1061Yesin Ryu, Sung-Gi Ahn, Jae-Hoon Lee, Jaewon Park, Yong-Ki Kim, Hyochang Kim, Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung-Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Suk-Han Lee, Kyounghwan Lim, Jungyu Lee 0002, Jeong Hoan Park, Jae-Seung Jeong, Sunghwan Jo, Dajung Cho, Sooyoung Kim, Minsu Lee, Hyunho Kim, Minhwan Kim, Jae-San Kim, Jinah Kim, Hyun gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young-Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, Sangjoon Hwang, Jooyoung Lee. A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features
    1062 -- 1073Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen 0033, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson 0002, William J. Dally, C. Thomas Gray. A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
    1074 -- 1086Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin. A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links
    1087 -- 1093Yusung Kim 0002, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl. Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
    1094 -- 1105Yuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, Jian-Gang Jimmy Zhu. Non-Linear CNN-Based Read Channel for Hard Disk Drive With 30% Error Rate Reduction and Sequential 200-Mbits/s Throughput in 28-nm CMOS
    1106 -- 1116Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders 0001, Steven Hsu, Amit Agarwal 0001, Vivek De, Sanu K. Mathew. A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS
    1117 -- 1128Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy. An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS
    1129 -- 1141Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany. A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
    1142 -- 1159Jinseok Park, Seungchan Lee, Jonghoon Chun, Laurence Jeon, Songcheol Hong. A 28-GHz Four-Channel Beamforming Front-End IC With Dual-Vector Variable Gain Phase Shifters for 64-Element Phased Array Antenna Module
    1160 -- 1171Junyao Tang, Lei Zhao, Cheng Huang. A Wireless Hysteretic Controlled Wireless Power Transfer System With Enhanced Efficiency and Dynamic Response for Bioimplants
    1172 -- 1184Zhaowen Wang, Peter R. Kinget. A Very High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data Link Clocking
    1185 -- 1196Duhyun Jeon, Dongmin Lee, Dong Kyue Kim, Byong-Deok Choi. 2 Physical Unclonable Function Based on Contact Failure Probability With Bit Error Rate < 0.43 ppm After Preselection With 0.0177% Discard Ratio

    Volume 58, Issue 3

    587 -- 588Farhana Sheikh, Yan Lu 0002. Guest Editorial 2022 Custom Integrated Circuits Conference
    589 -- 599Xueyong Zhang, Arindam Basu. A 915-1220 TOPS/W, 976-1301 GOPS Hybrid In-Memory Computing Based Always-On Image Processing for Neuromorphic Vision Sensors
    600 -- 613Jaehoon Heo, Junsoo Kim, Sukbin Lim, Wontak Han, Joo-Young Kim 0001. T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training
    614 -- 623Zhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, Hoi-Jun Yoo. An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache
    624 -- 633Xiaofeng Guo, Run Chen, Zhenqi Chen, Bin Li 0007. A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier
    634 -- 646Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
    647 -- 661Zhixian Deng, Changxuan Han, Yifan Li, Huizhen Jenny Qian, Xun Luo. A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA
    662 -- 676Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo. A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET
    677 -- 690Mohammadreza Beikmirza, Yiyu Shen, Leo C. N. de Vreede, Morteza S. Alavi. A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter
    691 -- 704Bingzheng Yang, Huizhen Jenny Qian, Jie Zhou, Yiyang Shu, Xun Luo. Millimeter-Wave Quadrature Mixed-Mode Transmitter With Distributed Parasitic Canceling and LO Leakage Self-Suppression
    705 -- 719Tianshi Xie, Jianglin Zhu, Dragan Maksimovic, Hanh-Phuc Le. A Highly Integrated Hybrid DC-DC Converter With nH-Scale IPD Inductors
    720 -- 731Donghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha, Chul Kim, Minkyu Je. A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current
    732 -- 741Tuur Van Daele, Filip Tavernier. Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS
    742 -- 756Sandeep Reddy Kukunuru, Yashar Naeimi, Loai G. Salem. A Series-Parallel Switched-Photovoltaic DC-DC Converter
    757 -- 770Shenglong Zhuo, Tao Xia, Lei Zhao, Miao Sun, Yifan Wu, Lei Wang, Hengwei Yu, Jiqing Xu, Jier Wang, Zhihong Lin, Yuan Li, Lei Qiu 0002, Rui Bai, XueFeng Chen, Patrick Yin Chiang. Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling
    771 -- 784Dhruv Patel 0002, Alireza Sharif Bakhtiar, Tony Chan Carusone. A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes
    785 -- 795Yongxin Li, Nilanjan Pal, Tianyu Wang 0006, Mostafa Gamal Ahmed, Ahmed Abdelrahman, Mohamed Badr Younis, Kyu-Sang Park, Ruhao Xia, Pavan Kumar Hanumolu. A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator
    796 -- 805Tianxiang Qu, Qinjing Pan, Liheng Liu, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu 0001. A 1.8-GΩ Input-Impedance 0.15-μV Input-Referred-Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction
    806 -- 816Zhi-Heng Kang, Shen-Iuan Liu. A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation
    817 -- 826Soo-Hun Kim, Seong-Min Ko, Dong-Woo Jee. A Pixelated Monolithic CMOS PPG Sensor for Spatial Feature Acquisition
    827 -- 837Yongtae Lee, Byeonghwa Cho, Changuk Lee, Jongbaeg Kim, Youngcheol Chae. A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution
    838 -- 851Qijun Liu, Miguel Jimenez, Maria Eugenia Inda, Arslan Riaz, Timur Zirtiloglu, Anantha P. Chandrakasan, Timothy K. Lu, Giovanni Traverso, Phillip M. Nadeau, Rabia Tugce Yazicigil. A Threshold-Based Bioluminescence Detector With a CMOS-Integrated Photodiode Array in 65 nm for a Multi-Diagnostic Ingestible Capsule
    852 -- 866Ruiqi Guo, Zhiheng Yue, Xin Si, Hao Li, Te Hu, Limei Tang, Yabing Wang, Hao Sun, Leibo Liu, Meng-Fan Chang, Qiang Li 0021, Shaojun Wei, Shouyi Yin. TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization
    867 -- 876Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang 0006, Cheng Huang, Hao Cai. AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS
    877 -- 892Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang. A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

    Volume 58, Issue 2

    331 -- 0Dennis Sylvester. New Associate Editor
    332 -- 344Jiayang Yu, Jixin Chen, Peigen Zhou, Huanbo Li, Zuojun Wang, Zekun Li, Zhe Chen, Pinpin Yan, Debin Hou, Hao Gao 0001, Wei Hong 0002. SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS
    345 -- 356Ziyang Luo, Jin Liu 0004, Hoi Lee. A 40.68-MHz Active Rectifier With Cycle-Based On-/Off-Delay Compensation for High-Current Biomedical Implants
    357 -- 370Bingzheng Yang, Huizhen Jenny Qian, Tianyi Wang, Xun Luo. A CMOS Wideband Watt-Level 4096-QAM Digital Power Amplifier Using Reconfigurable Power-Combining Transformer
    371 -- 385Haikun Jia, Pingda Guan, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS
    386 -- 399Ruixing He, Yahya M. Tousi. A mm-Wave Signal Generation and Background Phase Alignment Technique for Scalable Arrays
    400 -- 410Minjae Kim, Hyun-Su Lee, Jisan Ahn, Hyung-Min Lee. A 13.56-MHz Wireless Power and Data Transfer System With Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive Voltage Regulation
    411 -- 427Wei Deng 0001, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang 0001, Baoyong Chi. A D-Band Joint Radar-Communication CMOS Transceiver
    428 -- 438Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka. An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs
    439 -- 450Daniel Wendler, Daniel De Dorigo, Mohammad Amayreh, Alexander Bleitner, Maximilian Marx 0002, Roman Willaredt, Yiannos Manoli. 2 Two-Step Incremental Delta-Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation
    451 -- 461Xiudeng Wang, Yinshui Xia, Zhangming Zhu, Ge Shi 0001, Huakang Xia, Yidie Ye, Zhidong Chen, Libo Qian, Lianxi Liu. Configurable Hybrid Energy Synchronous Extraction Interface With Serial Stack Resonance for Multi-Source Energy Harvesting
    462 -- 473Chunxiao Hu, Yun Yin, Tong Li, Yangzi Liu, Liang Xiong, Hongtao Xu. A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS
    474 -- 485Yuekang Guo, Jing Jin 0005, Xiaoming Liu 0008, Jianjun Zhou. A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction
    486 -- 496Bo-Hao Chen, Tzu-Ying Wu, Kuo-Lin Zheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. A Feedforward Controlled Digital Low-Dropout Regulator With Weight Redistribution Algorithm and Body Voltage Control for Improving Line Regulation With 99.99% Current Efficiency and 0.5-mV Output Voltage Ripple
    497 -- 507Yong-Hwa Wen, Tz-Wun Wang, Tzu-Hsien Yang, Sheng-Hsi Hung, Kuo-Lin Zheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. th Tracking Technique for 20-MHz Depletion-Mode GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors
    508 -- 519Nahmil Koo, Hyojun Kim, SeongHwan Cho. pp and T-CMRR of 105 dB in 180-nm CMOS
    520 -- 529Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang. A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator
    530 -- 542Yuncheng Lu, Van Loi Le, Tony Tae-Hyoung Kim. A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN
    543 -- 553Junjie Mu, Bongjin Kim. A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method
    554 -- 568Sumon Kumar Bose, Arindam Basu. A 389 TOPS/W, Always ON Region Proposal Integrated Circuit Using In-Memory Computing in 65 nm CMOS
    569 -- 581Thierry Tambe, En-Yu Yang, Glenn G. Ko, Yuji Chai, Coleman Hooper, Marco Donato, Paul N. Whatmough, Alexander M. Rush, David Brooks 0001, Gu-Yeon Wei. A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs

    Volume 58, Issue 12

    3291 -- 3295James F. Buckwalter, Alireza Zolfaghari, Drew A. Hall, Ke-Horng Chen, Dominique Morche. Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)
    3296 -- 3307Jiaxiang Li, Yun Yin, Hang Chen, Jie Lin, Yicheng Li, Xianglong Jia, Zhen Hu, Ziyu Liu, Xiuyin Zhang, Hongtao Xu. A Transformer-Based Quadrature Doherty Digital Power Amplifier With 4.1 W Peak Power in 28 nm Bulk CMOS
    3308 -- 3319Yiyang Shu, Xun Luo. Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance
    3320 -- 3337Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    3338 -- 3350Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi. A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
    3351 -- 3363Aravind Nagulu, Yi Zhuang, Mingyu Yuan, Sasank Garikapati, Harish Krishnaswamy. A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through Clock Boosting
    3364 -- 3379Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher Dennis Hull, Steven Callender, Stefano Pellerano. A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET
    3380 -- 3395Xi Fu, Dongwon You, Xiaolin Wang, Yun Wang 0008, Carolyn Jill Mayeda, Yuan Gao, Michihiro Ide, Yuncheng Zhang, Jun Sakamaki, Ashbir Aviat Fadila, Zheng Li, Jumpei Sudo, Makoto Higaki, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai 0009, Kenichi Okada, Atsushi Shirane. A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations
    3396 -- 3407Soroush Araei, Shahabeddin Mohin, Negar Reiskarimian. Harmonic-Resilient Fully Passive Mixer-First Receiver for Software-Defined Radios
    3408 -- 3420Wan Kim, Hyun-Gi Seok, Geunhaeng Lee, Sinyoung Kim, Jae-Keun Lee, Chanho Kim, Wonkang Kim, Wonjun Jung, Youngsea Cho, Seungyong Bae, Jongpil Cho, Hyuokju Na, Byoungjoong Kang, Honggul Han, HyeonUk Son, Suhyeon Lee, Dongsu Kim, Ji-Seon Paek, Seunghyun Oh, Jongwoo Lee, Sungung Kwak, Joonsuk Kim. A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process
    3421 -- 3432Hayden Bialek, Matthew L. Johnston, Arun Natarajan 0001. A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios
    3433 -- 3441Zhong Tang, Sining Pan, Milos Grubor, Kofi A. A. Makinwa. A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor With an Inaccuracy of ±0.15 °C (3σ) From - 55 °C to 125 °C
    3442 -- 3449Amirhossein Jouyaeian, Qinwen Fan, Udo Ausserlechner, Mario Motz, Kofi A. A. Makinwa. A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop
    3450 -- 3458Sining Pan, Xiaomeng An, Zheru Yu, Hui Jiang 0007, Kofi A. A. Makinwa. A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme
    3459 -- 3469Kyu-Sang Park, Nilanjan Pal, Yongxin Li, Ruhao Xia, Tianyu Wang 0006, Ahmed E. AbdelRahman, Pavan Kumar Hanumolu. A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C
    3470 -- 3480Huajun Zhang, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan. A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier
    3481 -- 3491Lixiong Du, Dong Yan, Dongsheng Brian Ma. 3 EMI Control for Switching Power ICs
    3492 -- 3502Tingxu Hu, Mo Huang, Rui Paulo Martins, Yan Lu 0002. A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors
    3503 -- 3518Casey Hardy, Hanh-Phuc Le. A Reconfigurable Single-Inductor Multi-Stage Hybrid Converter for 1-Cell Battery Chargers
    3519 -- 3529Yeon-Woo Jeong, Seung-Ju Lee, Se-un Shin. A Scalable N-Step Equally Split SSHI Rectifier for Piezoelectric Energy Harvesting With Low-Q Inductor
    3530 -- 3543Yanqiao Li, Bahlakoana Mabetha, Jason T. Stauth. A Modular Switched-Capacitor Chip-Stacking Drive Platform for kV-Level Electrostatic Actuators
    3544 -- 3554Seung-Ju Lee, Yeon-Woo Jeong, Se-un Shin. CF Calibration and Smooth Mode Transition
    3555 -- 3564Manxin Li, Calvin Yoji Lee, Praveen Kumar Venkatachala, Ahmed ElShater, Yuichi Miyahara, Kazuki Sobue, Koji Tomioka, Un-Ku Moon. A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting
    3565 -- 3575Hongshuai Zhang, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan. A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator
    3576 -- 3585Mingtao Zhan, Lu Jie 0008, Yi Zhong, Nan Sun 0001. A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor
    3586 -- 3597Hongzhi Zhao, Minglei Zhang, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan. A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC

    Volume 58, Issue 11

    2951 -- 0Dennis Sylvester. New Associate Editor
    2952 -- 2954Mehdi Kiani, Kaushik Sengupta. Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)
    2955 -- 2964Menghan Guo, Shoushun Chen, Zhe Gao, Wenlei Yang, Peter Bartkovjak, Qing Qin, Xiaoqin Hu, Dahai Zhou, Qiping Huang, Masayuki Uchiyama, Yoshiharu Kudo, Shimpei Fukuoka, Chengcheng Xu, Hiroaki Ebihara, Xueqing Wang, Peiwen Jiang, Bo Jiang, Bo Mu, Huan Chen, Jason Yang, TJ Dai, Andreas Suess. A Three-Wafer-Stacked Hybrid 15-MPixel CIS + 1-MPixel EVS With 4.6-GEvent/s Readout, In-Pixel TDC, and On-Chip ISP and ESP Function
    2965 -- 2975Byungchoul Park, Hyun-Seung Choi, Jinwoong Jeong, Taewoo Kim 0007, Myung-Jae Lee, Youngcheol Chae. A 113.3-dB Dynamic Range 600 Frames/s SPAD X-Ray Detector With Seamless Global Shutter and Time-Encoded Extrapolation Counter
    2976 -- 2989Kyeongho Eom, Minju Park, Han-Sol Lee, Seung-Beom Ku, Namju Kim, Seongkwang Cha, Yong-Sook Goo, Sohee Kim, Seong-Woo Kim, Hyung-Min Lee. A Low-Stimulus-Scattering Pixel-Sharing Sub-Retinal Prosthesis SoC With Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage Scaling
    2990 -- 3002Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas, Georges G. E. Gielen, Francky Catthoor, Marian Verhelst, Carolina Mora Lopez. An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing
    3003 -- 3019Fatemeh Aghlmand, Chelsea Hu, Saransh Sharma, Krishna K. Pochana, Richard M. Murray, Azita Emami. A 65-nm CMOS Fluorescence Sensor for Dynamic Monitoring of Living Cells
    3020 -- 3029Jinhai Lin, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak. A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM
    3030 -- 3043Craig Ives, Debjit Sarkar, Ali Hajimiri. Subtractive Photonics in Bulk CMOS
    3044 -- 3059Juhwan Yoo, Zijun Chen, Frank Arute, Shirin Montazeri, Marco Szalay, Catherine Erickson, Evan Jeffrey, Reza Fatemi, Marissa Giustina, Markus Ansmann, Erik Lucero, Julian Kelly, Joseph C. Bardin. Design and Characterization of a <4-mW/Qubit 28-nm Cryo-CMOS Integrated Circuit for Full Control of a Superconducting Quantum Processor Unit Cell
    3060 -- 3073Yanshu Guo, Qichun Liu, Yaoyu Li, Wenqiang Huang, Tian Tian, Siqi Zhang, Nan Wu, Songyao Tan, Ning Deng 0008, Zhihua Wang 0001, Hanjun Jiang, Tiefu Li, Yuanjin Zheng. A Polar-Modulation-Based Cryogenic Transmon Qubit State Controller in 28 nm Bulk CMOS for Superconducting Quantum Computing
    3074 -- 3088Emir Ali Karahan, Zheng Liu, Kaushik Sengupta. Deep-Learning-Based Inverse-Designed Millimeter-Wave Passives and Power Amplifiers
    3089 -- 3102Byeonghun Yun, Dae-Woong Park, Sang-Gug Lee 0001. max-Core and Transmission Line-Based Zero-Degree Power Combining Networks
    3103 -- 3112Zongming Duan, Bowen Wu, Yan Wang, Yun Fang, Yongjie Li, Yanhui Wu, Tao Zhang, Chuanming Zhu, Yuefei Dai, Lei Sang, Hao Gao 0001. A 76-81 GHz 2×8 MIMO Radar Transceiver With Broadband Fast Chirp Generation and 16-Antenna-in-Package Virtual Array
    3113 -- 3126Hamidreza Afzal, Cheng Li 0010, Omeed Momeni. A Highly Efficient 165-GHz 4FSK 17-Gb/s Transceiver System With Frequency Overlapping Architecture in 65-nm CMOS
    3127 -- 3137Zixiao Lin, Yan Lu 0002, Fangyu Mao, Chuang Wang 0004, Rui Paulo Martins. All Rivers Flow to the Sea: A High-Density Wireless Power Receiver With Split-Dual-Path and Hybrid-Quad-Path Step-Down Rectifying Conversion
    3138 -- 3149Enrico Genco, Carmine Garripoli, Jan-Laurens P. J. van der Steen, Gerwin H. Gelinck, Sahel Abdinia, Pieter Harpe, Eugenio Cantatore. An EMG Interface Comprising a Flexible a-IGZO Active Electrode Matrix and a 65-nm CMOS IC
    3150 -- 3163Rahul Gulve, Navid Sarhangnejad, Gairik Dutta, Motasem Sakr, Don Nguyen, Roberto Rangel, Wenzheng Chen, Zhengfan Xia, Mian Wei, Nikita Gusev, Esther Y. H. Lin, Xiaonong Sun, Leo Hanxu, Nikola Katic, Ameer M. S. Abdelhadi, Andreas Moshovos, Kiriakos N. Kutulakos, Roman Genov. 39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging
    3164 -- 3178Gyu-Wan Lim, Gyeong-Gu Kang, Hyunggun Ma, Moonjae Jeong, Hyun-Sik Kim. An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays
    3179 -- 3193Chenghao Zhang, Jiangbo Wei, Yong Chen 0005, Maliang Liu, Yintang Yang. 2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS
    3194 -- 3206Yunshan Zhang, Changgui Yang, Ziyi Chang, Zhuhao Li, Huan Gao, Yuxuan Luo, Kedi Xu 0001, Gang Pan 0001, Bo Zhao 0003. An 8-Shaped Antenna-Based Battery-Free Neural-Recording System Featuring 3 cm Reading Range and 140 pJ/bit Energy Efficiency
    3207 -- 3218Tingxu Hu, Mo Huang, Rui Paulo Martins, Yan Lu 0002. A 12-to-1 Flying Capacitor Cross-Connected Buck Converter With Inserted D > 0.5 Control for Fast Transient Response
    3219 -- 3230Caolei Pan, Wen-Liang Zeng, Chi-Seng Lam, Sai-Weng Sin, Chenchang Zhan, Rui Paulo Martins. A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications
    3231 -- 3241Indranil Bhattacharjee, Gajendranath Chowdary. A 0.45 mV/V Line Regulation, 0.6 V Output Voltage, Reference-Integrated, Error Amplifier-Less LDO With a 5-Transistor Regulation Core
    3242 -- 3252Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung. An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s
    3253 -- 3265Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim. A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links
    3266 -- 3274Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh. A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification
    3275 -- 3285Bing-Chen Wu, Wei-Ting Chen, Tsung-Te Liu. An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS

    Volume 58, Issue 10

    2671 -- 2674SeongHwan Cho, Joo-Young Kim 0001, Minoru Fujishima, Jun Zhou 0017. Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC)
    2675 -- 2684Chongsoo Jung, Hoyong Seong, Injun Choi, Sohmyung Ha, Minkyu Je. A Process-Scalable Ultra-Low-Voltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier
    2685 -- 2695Cong Huang, Hailong Jiao. 3MLS: An Ultra-Wide-Range Energy-Efficient Level Shifter With CCLS/CMLS Hybrid Structure
    2696 -- 2708Hyunjun Park, Woojoong Jung, Minsu Kim, Hyung-Min Lee. A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis Inverse Biasing
    2709 -- 2721Wenning Jiang, Yan Zhu 0001, Chixiao Chen, Hao Xu 0005, Qi Liu 0010, Ming Liu, Rui Paulo Martins, Chi-Hang Chan. A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier
    2722 -- 2732Shulin Zhao, Mingqiang Guo, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins, Sai-Weng Sin. A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward
    2733 -- 2744Jia-Sheng Huang, Shih-Che Kuo, Chia-Hung Chen. A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces
    2745 -- 2756Donguk Seo, Minsik Cho, Minhyeok Jeong, Gicheol Shin, Inhee Lee, David T. Blaauw, Yoonmyung Lee. An RC Delay-Based Pressure-Sensing System With Energy-Efficient Bit-Level Oversampling Techniques for Implantable IOP Monitoring Systems
    2757 -- 2766Dong-Hwi Choi, Dong-Woo Jee. A 1984-Pixels, 1.26 nW/Pixel Retinal Prosthesis Chip With Time-Domain In-Pixel Image Processing and Bipolar Stimulating Electrode Sharing
    2767 -- 2777Min-Yang Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh. A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision
    2778 -- 2789Kyeongwon Jeong, Gichan Yun, Jaesuk Choi, Injun Choi, Jeehoon Son, Jae Youn Hwang, Sohmyung Ha, Minkyu Je. A Wide-Bandwidth Ultrasound Receiver and On-Chip Ultrasound Transmitter for Ultrasound Capsule Endoscopy
    2790 -- 2800Han Wu 0003, Jeong Hoan Park, Rucheng Jiang, Jung Hwan Choi, Jerald Yoo. A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os
    2801 -- 2811Yao-Chia Liu, Wei-Zen Chen, Yuan-Sheng Lee, Yu-Hsiang Chen, Shawn Ming, Ying-Hsi Lin. A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement
    2812 -- 2825Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Juhyoung Lee, Hoi-Jun Yoo. SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit
    2826 -- 2838Richard Dorrance, Deepak Dasalukunte, Hechen Wang, Renzhi Liu, Brent R. Carlton. An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET
    2839 -- 2850Wang Ye, Linfang Wang, Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li, Jinshan Yue, Hongyang Hu, Xiaoxin Xu, Jianguo Yang, Jing Liu, Dashan Shang, Feng Zhang 0014, Jinghui Tian, Chunmeng Dou, Qi Liu 0010, Ming Liu. A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference
    2851 -- 2860Yudai Yamazaki, Jun Sakamaki, Jian Pang, Joshua Alvin, Zheng Li, Dongwon You, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada. A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD
    2861 -- 2873Yaqian Sun, Wei Deng 0001, Haikun Jia, Yejun He, Zhihua Wang 0001, Baoyong Chi. A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique
    2874 -- 2882Amirhossein Jouyaeian, Qinwen Fan, Roger Luis Brito Zamparette, Udo Ausserlechner, Mario Motz, Kofi A. A. Makinwa. A Hybrid Magnetic Current Sensor With a Multiplexed Ripple-Reduction Loop
    2883 -- 2896Haoyi Zhao, Fa Foster Dai. A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain Scale Alignment
    2897 -- 2906Chih-Cheng Chen, Yu-Hsiang Huang, John Carl Joel S. Marquez, Chih-Cheng Hsieh. A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive Voltage- Time-Voltage Converter
    2907 -- 2918Ahmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar. A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking
    2919 -- 2930Hui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto. Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design
    2931 -- 2945Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo. Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital-Analog Networks

    Volume 58, Issue 1

    8 -- 18Ahmad Khairi, Yoel Krupnik, Amir Laufer, Yoav Segal, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Sabag, Vitali Rahinski, Idan Lotan, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky Grafi, Udi Virobnik, Dror Lazar, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo, Peng Mike Li, Frank O'Mahony, Ariel Cohen 0001. A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels
    19 -- 29Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, YanDong He, Song Jia, Congcong Chen, Jiaqi Yu. A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS
    30 -- 44Arian Hashemi Talkhooncheh, Weiwei Zhang, Minwo Wang, David J. Thomson 0001, Martin Ebert, Ke Li 0008, Graham T. Reed, Azita Emami. A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators
    45 -- 56Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen. A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS
    57 -- 67Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi. A 56-GHz Fractional-N PLL With 110-fs Jitter
    68 -- 77Chi-Hsiang Huang 0001, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe 0001. Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains
    78 -- 89Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi. A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68
    90 -- 101Jae-Gon Lee, YounSik Choi, Hoyeon Jeon, Jong Jin Lee, Dongsuk Shin. Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC
    102 -- 110Brian T. Vanderpool, Phillip J. Restle, Eric Fluhr, Gregory S. Still, Francesco A. Campisano, Ian Charmichael, Eric Marz, Rahul Batra, Richard L. Willaman. Deterministic Frequency and Voltage Enhancements on the POWER10 Processor
    111 -- 123Sumeet Singh Nagi, Uneeb Rathore, Krutikesh Sahoo, Tim Ling, Subramanian S. Iyer, Dejan Markovic. A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration
    124 -- 140Yihong Zhu, Wenping Zhu, Chongyang Li, Min Zhu 0001, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu. RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems
    141 -- 154Saurav Maji, Utsav Banerjee, Samuel H. Fuller, Anantha P. Chandrakasan. A Threshold Implementation-Based Neural Network Accelerator With Power and Electromagnetic Side-Channel Countermeasures
    155 -- 166Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Uijong Song, Chang-Yeon Cho, Giyeong Ko, Hyunseok Hwang, Junseo Lee, Han-Sol Lee, Yong-Il Kwon, Kyungduck Seo, Taeseon Kim, Hyun-Wook Lim, Seongwook Song, Jae-Youl Lee, Sung-Ung Kwak. A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication
    167 -- 176Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang. A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction
    177 -- 188Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, Hoi-Jun Yoo. DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC
    189 -- 202Jun-Seok Park, Changsoo Park, Suknam Kwon, Taeho Jeon, Yesung Kang, Heonsoo Lee, Dongwoo Lee, James Kim, Hyeong-Seok Kim, YoungJong Lee, Sangkyu Park, Minseong Kim, Sanghyuck Ha, Jihoon Bang, Jinpyo Park, SukHwan Lim, Inyup Kang. A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC
    203 -- 215Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst. DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge
    216 -- 226Yuhao Ju, Jie Gu 0001. A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance
    227 -- 242Yang Wang 0089, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin. An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention
    243 -- 255Fengbin Tu, Yiqi Wang 0005, Zihan Wu 0006, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie 0001, Shouyi Yin. ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration
    256 -- 269Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Ji-Hwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Tae Sik Yun, Young Jun Koo, Jae-Seung Lee, Byung Kuk Yoon, Young-Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung-Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae Hyung Park, Jong-Chan Yun, Seonyeol Kim, Dong Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee 0002, Jieun Jang, Joohwan Cho. A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization
    270 -- 278Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho. A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM
    279 -- 290Daewoong Lee, Jaehyeok Baek, Hye-Jung Kwon, Daehyun Kwon, Chulhee Cho, Sang-Hoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun Young Park, Hyoung-Joo Kim, Ho-Seok Seol, Juhwan Kim, Jung-Bum Shin, Gil-Young Kang, Yong Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chanyong Lee, SeungSeob Lee, Taehoon Park, Chi Sung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-young Oh, Sangjoon Hwang, Kyung Suk Oh, Jung Hwan Choi, Jooyoung Lee. A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
    291 -- 302Dae-Han Kwon, Seongju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dongyoon Ka, Kyu-Dong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Guhyun Kim, Byeongju An, Jaewook Lee, Donguc Ko, Younggun Jun, Ilwoong Kim, Choungki Song, Ilkon Kim, Chanwook Park, Seho Kim, Chunseok Jeong, Euicheol Lim, Dongkyun Kim, Jieun Jang, Il Park 0001, Junhyun Chun, Joohwan Cho. A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application
    303 -- 315Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang. 8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices
    316 -- 328Jonghak Yuh, Yen-Lung Jason Li, Heguang Li, Yoshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Gwang Yeong Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, Taekeun Han, Masatoshi Okumura, Jiwen Liu, Jeongduk John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Akihiro Matsuda, Chen Chen, Indra K. V, V. S. N. K. Chaitanya G., Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, Farookh Moogat, In-Soo Yoon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Kosuke Yanagidaira, Takuyo Kodama, Ryo Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe. A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface
    runs on