David Esseni - researchr profile publications

researchr

You are not signed in
Sign in
Sign up

[Clear Filters]

Publications tagged power consumption

Power consumption and energy efficiency in the internetKerry Hinton, J. Baliga, Michael Z. Feng, Robert Ayre, Rodney S. Tucker. network, 25(2):6-12, 2011. [doi]

Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodologyAli Jahanian, Morteza Saheb Zamani, Hamid Safizadeh. integration, 44(2):123-135, 2011. [doi]

The driving force for development of IC and system in future: Reducing the power consumption and improving the ratio of performance to power consumptionYangyuan Wang. chinaf, 54(5):915-935, 2011. [doi]

Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk TechnologyMatteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi. IEEE Trans. VLSI Syst., 18(2), Feb 2010. [doi]

IP characterization methodology for fast and accurate power consumption estimation at transactional level modelMichel Rogers-Vallée, Marc-André Cantin, Laurent Moss, Guy Bois. iccd 2010: 534-541 [doi]

Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating TechniqueAntonin Hermanek, Michal Kunes, Milan Tichý. fpl 2010: 336-339 [doi]

Reducing disk power consumption in portable media playersMinseok Song, Wanhyung Ryu, Jeong Seop Sim. estimedia 2010: 81-89 [doi]

Power Consumption of Hardware Cryptography Platform for Wireless SensorPeter Pecho, Jan Nagy, Petr HanÃ¡cek. pdcat 2009: 318-323 [doi]

Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power ConsumptionSherif A. Tawfik, Volkan Kursun. jcsc, 17(6):1173-1191, 2008. [doi]

Applying Low Power Consumption Superconductive Device Technology to Real-Time Waveform Monitoring for Photonic NetworkMutsuo Hidaka, Michitaka Maruyama, Hideo Suzuki. saint 2008: 377-380 [doi]

Parallelism to reduce power consumption on FPGA spatiotemporal image processingWalid Atabany, Patrick Degenaar. iscas 2008: 1476-1479 [doi]

Power management techniques for very low consumption and EMI reduction in automotive applicationsEduardo Ribeiro da Silva, Ivan Carlos Ribeiro do Nascimento, Frank Herman Behrens, Marcos Mauricio Pelicia, Remerson Stein Kickhofel, Ricardo Maltione. sbcci 2008: 129-133 [doi]

Comparing throughput and power consumption in both sequential and reconfigurable processorsKevin K. Liu, Charles B. Cameron, Antal A. Sarkady. fpl 2008: 603-606 [doi]

Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAsSyed Zahid Ahmed, Julien Eydoux, Michael FernÃ¡ndez, Laurent Rouge, Gilles Sassatelli, Lionel Torres. reconfig 2008: 313-318 [doi]

Compression for Low Power Consumption in Battery-powered HandsetsMayumi Kato, Chia-Tien Dan Lo. dcc 2007: 386 [doi]

Performance and power consumption of computers using batch service with event and time counterYing-Wen Bai, Yung-Sen Cheng. pdcn 2007: 132-137

Power Consumption Forecast by Combining Neural Networks with Immune AlgorithmShuxia Yang. snpd 2007: 238-241 [doi]

ECC Hardware Coprocessors for 8-bit Systems and Power Consumption ConsiderationsGuido Bertoni, Luca Breveglieri, Matteo Venturi. itng 2006: 573-574 [doi]

Power Consumption in Handheld ComputersAssim Sagahyroon. apccas 2006: 1721-1724 [doi]

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and RepeatersTudor Murgan, O. Mitrea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner. vlsi 2006: 302-307 [doi]

Designing cryptographic key generators with low power consumptionM. Puczko, V. N. Yarmolik. delta 2006: 418-421 [doi]

Power Consumption Management on FPGAsAndrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña. conielecomp 2005: 240-245 [doi]

Methodology for high level estimation of FPGA power consumptionVijay Degalahal, Tim Tuan. aspdac 2005: 657-660 [doi]

Reducing the Power Consumption of FPGAs through RetimingRobert Fischer, Klaus Buchenrieder, Ulrich Nageldinger. ECBS 2005: 89-94 [doi]

Power Consumption Reduction Using Dynamic Control of Micro Processor PerformanceDavid Rios-Arambula, Aurélien Buhrig, Marc Renaudin. patmos 2005: 10-18 [doi]

Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSPMiguel Casas-Sanchez, Jose Rizo-Morente, Chris J. Bleakley. patmos 2005: 561-570 [doi]

Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area ConsumptionStephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel. patmos 2004: 392-401 [doi]

Power Consumption of Performance-Scaled SIMD ProcessorsAnteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat. patmos 2004: 532-540 [doi]

Reducing Power Consumption in Interconnection Networks by Dynamically Adjusting Link WidthMarina Alonso, Juan Miguel Martínez, Vicente Santonja, Pedro López. europar 2004: 882-890 [doi]

Reducing power consumption and enhancing performance by direct slave-to-slave and group communication in Bluetooth WPANsCarlos de M. Cordeiro, Sachin Abhyankar, Dharma P. Agrawal. cn, 45(2):119-141, 2004. [doi]

Minimizing power consumption and complexity in a programmable transmit filter bank for OFDMAlireza Mehrnia, Babak Daneshrad. islped 2004: 230-235 [doi]

On Transfer Function and Power Consumption Transient ResponseLipeng Cao. date 2004: 688-689 [doi]

Power consumption reduction in systems on Chip (SoCs)Christian Piguet. adt, 59(7-8):884-902, 2004. [doi]

Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path UnequalizationSonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida. patmos 2003: 151-160 [doi]

Speculating to reduce unnecessary power consumptionEnric Musoll. tecs, 2(4):509-536, 2003. [doi]

Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental ResultsJosep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez. patmos 2003: 80-89 [doi]

A method to reduce power consumption in pipelined A/D convertersLiviu Chiaburu, Svante Signell. iscas 2003: 845-848 [doi]

Impact of Code Compression on the Power Consumption in Embedded SystemsN. Kadri, S. Niar, A. R. Baba-Ali. csreaESA 2003: 197-203

A Computer That Puts On Your Thinking Cap / Vision Chip Slashes Power Consumption Laurianne McLaughlin, Terry Costlow. expert, 18(6):4-7, 2003. [doi]

Reduced Power Consumption for MPEG Decoding with LNSMark G. Arnold. asap 2002: 65-75 [doi]

Evaluating software s power consumptionH. Arafat Ali, Tahany A. Fergany, Reda A. Ammar. cata 2001: 88-93

Impact of Voltage Scaling on Glitch Power ConsumptionHenrik Eriksson, Per Larsson-Edefors. patmos 2000: 139-148 [doi]

Reducing Power Consumption of CMOS VLSI s through VDD and VTH ControlTakayasu Sakurai. isqed 2000: 417-424 [doi]

Reordering Memory Bus Transactions for Reduced Power ConsumptionBruce R. Childers, Tarun Nakra. lctrts 2001: 146-161 [doi]

Fuzzy Time-Series Model of Electric Power ConsumptionKazuhiro Ozawa, Takahide Niimura, Tomoaki Nakashima. jaciii, 4(3):188-194, 2000. [doi]

Power consumption reduction in high-speed Sigma-Delta bandpass modulatorsP. Cusinato, F. Stefani, A. Baschirotto. islped 2000: 55-60 [doi]

A non-iterative gate resizing algorithm for high reduction in power consumptionPatrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac. integration, 24(1):37-52, 1997. [doi]

A gate resizing technique for high reduction in power consumptionPatrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac. islped 1997: 281-286 [doi]

Minimization of chip size and power consumption of high-speed VLSI buffersD. Zhou, X. Y. Liu. ispd 1997: 186-191 [doi]

Probabilistic power consumption estimation in digital circuitsWolfgang Röthig, Elmar U. K. Melcher, Michel Dana. vlsi 1994: 231-240

runs on WebDSL