Table of Contents

• Clock domain crossing aware sequential clock gatingJianfeng Liu, Mi-Suk Hong, Kyung Tae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi, Abhishek Ranjan. 1-6 [doi]
• An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodesHehe Li, Yongpan Liu, Qinghang Zhao, Yizi Gu, Xiao Sheng, Guangyu Sun, Chao Zhang, Meng-Fan Chang, Rong Luo, Huazhong Yang. 7-12 [doi]
• Race to idle or not: balancing the memory sleep time with DVS for energy minimizationChenchen Fu, Minming Li, Chun Jason Xue. 13-18 [doi]
• Event-driven and sensorless photovoltaic system reconfiguration for electric vehiclesXue Lin, Yanzhi Wang, Massoud Pedram, Jaemin Kim, Naehyuck Chang. 19-24 [doi]
• Online binding of applications to multiple clock domains in shared FPGA-based systemsFarzad Samie, Lars Bauer, Chih-Ming Hsieh, Jörg Henkel. 25-30 [doi]
• Profiling-driven multi-cycling in FPGA high-level synthesisStefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Anderson. 31-36 [doi]
• Schedulability bound for integrated modular avionics partitionsJung-Eun Kim, Tarek F. Abdelzaher, Lui Sha. 37-42 [doi]
• Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systemsAnup Das 0001, Akash Kumar, Bharadwaj Veeravalli, Rishad Ahmed Shafik, Geoff V. Merrett, Bashir M. Al-Hashimi. 43-48 [doi]
• Formal analysis of the startup delay of SOME/IP service discoveryJan R. Seyler, Thilo Streichert, Michael Glaß, Nicolas Navet, Jürgen Teich. 49-54 [doi]
• Analysis of ethernet-switch traffic shapers for in-vehicle networking applicationsSivakumar Thangamuthu, Nicola Concer, Pieter J. L. Cuijpers, Johan J. Lukkien. 55-60 [doi]
• Real-time capable CAN to AVB ethernet gateway using frame aggregation and schedulingChristian Herber, Andre Richter, Thomas Wild, Andreas Herkersdorf. 61-66 [doi]
• Automatic extraction of assertions from execution traces of behavioural modelsAlessandro Danese, Tara Ghasempouri, Graziano Pravadelli. 67-72 [doi]
• A methodology for automated design of embedded bit-flips detectors in post-silicon validationPouya Taatizadeh, Nicola Nicolici. 73-78 [doi]
• Data mining diagnostics and bug MRIs for HW bug localizationMonica Farkash, Bryan G. Hickerson, Balavinayagam Samynathan. 79-84 [doi]
• RTL property abstraction for TLM assertion-based verificationNicola Bombieri, Riccardo Filippozzi, Graziano Pravadelli, Francesco Stefanni. 85-90 [doi]
• Low-cost checkpointing in automotive safety-relevant systemsCarles Hernández, Jaume Abella. 91-96 [doi]
• Uncertainty-aware reliability analysis and optimizationFaramarz Khosravi, Malte Müller, Michael Glaß, Jürgen Teich. 97-102 [doi]
• Efficient soft error vulnerability estimation of complex designsShahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher, Jacob Abraham. 103-108 [doi]
• Detection of illegitimate access to JTAG via statistical learning in chipXuanle Ren, Vítor Grade Tavares, R. D. (Shawn) Blanton. 109-114 [doi]
• Joint affine transformation and loop pipelining for mapping nested loop on CGRAsShouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei, Yike Guo. 115-120 [doi]
• Path selection based acceleration of conditionals in CGRAsShriHari RajendranRadhika, Aviral Shrivastava, Mahdi Hamzeh. 121-126 [doi]
• Hardware-assisted code obfuscation for FPGA soft microprocessorsMeha Kainth, Lekshmi Krishnan, Chaitra Narayana, Sandesh Gubbi Virupaksha, Russell Tessier. 127-132 [doi]
• Reliable information extraction for single trace attacksValentina Banciu, Elisabeth Oswald, Carolyn Whitnall. 133-138 [doi]
• Scandalee: a side-channel-based disassembler using local electromagnetic emanationsDaehyun Strobel, Florian Bache, David Oswald, Falk Schellenberg, Christof Paar. 139-144 [doi]
• Side-channel attacks from static power: when should we care?Santos Merino Del Pozo, François-Xavier Standaert, Dina Kamel, Amir Moradi. 145-150 [doi]
• Extrax: security extension to extract cache resident information for snoop-based external monitorsJinYong Lee, Yongje Lee, Hyungon Moon, Ingoo Heo, Yunheung Paek. 151-156 [doi]
• Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesisPham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung. 157-162 [doi]
• Interplay of loop unrolling and multidimensional memory partitioning in HLSAlessandro Cilardo, Luca Gallo. 163-168 [doi]
• Inter-tile reuse optimization applied to bandwidth constrained embedded acceleratorsMaurice Peemen, Bart Mesman, Henk Corporaal. 169-174 [doi]
• SelectDirectory: a selective directory for cache coherence in many-core architecturesYuan Yao, Guanhua Wang, Zhiguo Ge, Tulika Mitra, Wenzhi Chen, Naxin Zhang. 175-180 [doi]
• DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>sAshish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan. 181-186 [doi]
• Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cacheShouyi Yin, Jiakun Li, Leibo Liu, Shaojun Wei, Yike Guo. 187-192 [doi]
• A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systemsManil Dev Gomony, Jamie Garside, Benny Akesson, Neil C. Audsley, Kees G. W. Goossens. 193-198 [doi]
• Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checkingMingsong Chen, Daian Yue, Xiaoke Qin, Xin Fu, Prabhat Mishra. 199-204 [doi]
• A fast parallel sparse solver for SPICE-based circuit simulatorsXiaoming Chen, Yu Wang, Huazhong Yang. 205-210 [doi]
• MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulationXinke Chen, Guangfei Zhang, Huandong Wang, Ruiyang Wu, Peng Wu, Longbing Zhang. 211-216 [doi]
• Source level performance simulation of GPU coresChristoph Gerum, Oliver Bringmann, Wolfgang Rosenstiel. 217-222 [doi]
• Delay analysis of structural real-time workloadNan Guan, Yue Tang, Yang Wang, Wang Yi 0001. 223-228 [doi]
• Effective verification of low-level software with nested interruptsDaniel Kroening, Lihao Liang, Tom Melham, Peter Schrammel, Michael Tautschnig. 229-234 [doi]
• Platform-specific timing verification framework in model-based implementationBaekGyu Kim, Lu Feng, Linh T. X. Phan, Oleg Sokolsky, Insup Lee. 235-240 [doi]
• Architecture description language based retargetable symbolic executionAndreas Ibing. 241-246 [doi]
• Error recovery in digital microfluidics for personalized medicineMohamed Ibrahim, Krishnendu Chakrabarty. 247-252 [doi]
• A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platformsPaul Bogdan. 253-258 [doi]
• On-chip network-enabled many-core architectures for computational biology applicationsTurbo Majumder, Partha Pratim Pande, Ananth Kalyanaraman. 259-264 [doi]
• High-resolution online power monitoring for modern microprocessorsFabian Oboril, Jos Ewert, Mehdi Baradaran Tahoori. 265-268 [doi]
• Reducing energy consumption in microcontroller-based platforms with low design margin co-processorsAndres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez. 269-272 [doi]
• De-elastisation: from asynchronous dataflows to synchronous circuitsMahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards. 273-276 [doi]
• Automated feature localization for dynamically generated SystemC designsJannis Stoppe, Robert Wille, Rolf Drechsler. 277-280 [doi]
• Inductor optimization for active cell balancing using geometric programmingMatthias Kauer, Swaminathan Narayanaswamy, Martin Lukasiewycz, Sebastian Steinhorst, Samarjit Chakraborty. 281-284 [doi]
• Lightweight authentication for secure automotive networksPhilipp Mundhenk, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty. 285-288 [doi]
• Minimizing the number of process corner simulations during design verificationMichael Shoniker, Bruce F. Cockburn, Jie Han, Witold Pedrycz. 289-292 [doi]
• An approximate voting scheme for reliable computingKe Chen, Fabrizio Lombardi, Jie Han. 293-296 [doi]
• FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC designRochus Nowosielski, Lukas Gerlach, Stephan Bieband, Guillermo Payá Vayá, Holger Blume. 297-300 [doi]
• A unified hardware/software MPSoC system construction and run-time frameworkSam Skalicky, Andrew G. Schmidt, Sonia López, Matthew French. 301-304 [doi]
• 2: accelerator synthesis using algorithmic skeletons for rapid design space explorationShakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar, Henk Corporaal. 305-308 [doi]
• Assisted generation of frame conditions for formal modelsPhilipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille. 309-312 [doi]
• Towards a meta-language for the concurrency concern in DSLsJulien DeAntoni, Papa Issa Diallo, Ciprian Teodorov, Joël Champeau, Benoît Combemale. 313-316 [doi]
• Fast and accurate branch predictor simulationAntoine Faravelon, Nicolas Fournel, Frédéric Pétrot. 317-320 [doi]
• Comparative study of test generation methods for simulation acceleratorsWisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin-Sung Park, Sung-Boem Park, WooKyeong Jeong, Jae Cheol Son. 321-324 [doi]
• Using structural relations for checking combinationality of cyclic circuitsWan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang. 325-328 [doi]
• NFRs early estimation through software metricsAndrws Vieira, Pedro Faustini, Luigi Carro, Érika F. Cota. 329-332 [doi]
• Privacy-preserving functional IP verification utilizing fully homomorphic encryptionCharalambos Konstantinou, Anastasis Keliris, Michail Maniatakos. 333-338 [doi]
• Efficient software implementation of ring-LWE encryptionRuan de Clercq, Sujoy Sinha Roy, Frederik Vercauteren, Ingrid Verbauwhede. 339-344 [doi]
• Embedded HW/SW platform for on-the-fly testing of true random number generatorsBohan Yang, Vladimir Rozic, Nele Mentens, Wim Dehaene, Ingrid Verbauwhede. 345-350 [doi]
• An online thermal-constrained task scheduler for 3D multi-core processorsChien-Hui Liao, Charles H.-P. Wen, Krishnendu Chakrabarty. 351-356 [doi]
• A symbolic system synthesis approach for hard real-time systems based on coordinated SMT-solvingAlexander Biewer, Benjamin Andres, Jens Gladigau, Torsten Schaub, Christian Haubelt. 357-362 [doi]
• E-pipeline: elastic hardware/software pipelines on a many-core fabricXi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran. 363-368 [doi]
• Soft-error reliability and power co-optimization for GPGPUS register file using resistive memoryJingweijia Tan, Zhi Li 0016, Xin Fu. 369-374 [doi]
• Energy-efficient cache design in emerging mobile platforms: the implications and optimizationsKaige Yan, Xin Fu. 375-380 [doi]
• Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustmentJeremy Constantin, Lai Wang, Georgios Karakonstantis, Anupam Chattopadhyay, Andreas Burg. 381-386 [doi]
• Variability-aware dark silicon management in on-chip many-core systemsMuhammad Shafique, Dennis Gnad, Siddharth Garg, Jörg Henkel. 387-392 [doi]
• Systematic application of ISO 26262 on a SEooC: Support by applying a systematic reuse approachAlejandra Ruiz, Alberto Melzi, Tim Kelly. 393-396 [doi]
• Timing analysis of an avionics case study on complex hardware/software platformsFranck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoë R. Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla. 397-402 [doi]
• Silicon proof of the intelligent analog IP design flow for flexible automotive componentsT. Reich, H. D. B. Prautsch, U. Eichler, R. Buhl. 403-404 [doi]
• Fast optical simulation from a reduced set of impulse responses using SystemC-AMSFabien Teysseyre, David Navarro, Ian O'Connor, Francesco Cascio, Fabio Cenni, Olivier Guillaume. 405-409 [doi]
• Designer-level verification: an industrial experience storyStephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru. 410-411 [doi]
• Minimum current consumption transition time optimization methodology for low power CTSVibhu Sharma. 412-416 [doi]
• A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systemsMichail Mavropoulos, Georgios Keramidas, Dimitris Nikolos. 417-422 [doi]
• Temperature-aware software-based self-testing for delay faultsYing Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita. 423-428 [doi]
• Operational fault detection and monitoring of a memristor-based LUTT. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi. 429-434 [doi]
• Power-aware online testing of manycore systems in the dark silicon eraMohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi, Hannu Tenhunen. 435-440 [doi]
• Digital circuits reliability with in-situ monitors in 28nm fully depleted SOIM. Saliva, F. Cacho, V. Huard, X. Federspiel, D. Angot, A. Benhassain, A. Bravaix, L. Anghel. 441-446 [doi]
• Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cellElena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras. 447-452 [doi]
• Fault modeling in controllable polarity silicon nanowire circuitsHassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 453-458 [doi]
• Improved practical differential fault analysis of grain-128Prakash Dey, Abhishek Chakraborty, Avishek Adhikari, Debdeep Mukhopadhyay. 459-464 [doi]
• A score-based classification method for identifying hardware-trojans at gate-level netlistsMasaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa. 465-470 [doi]
• Hardware Trojan detection for gate-level ICs using signal correlation based clusteringBurçin Çakir, Sharad Malik. 471-476 [doi]
• Exploiting DRAM restore time variations in deep sub-micron scalingXianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang. 477-482 [doi]
• Adaptively tolerate power-gating-induced power/ground noise under process variationsZhe Wang, Xuan Wang, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong, Haoran Li, Rafael Kioji Vivas Maeda, Zhifei Wang. 483-488 [doi]
• Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memoriesAdam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg. 489-494 [doi]
• Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCsChristian Weis, Matthias Jung 0001, Peter Ehses, Cristiano Santos, Pascal Vivet, Sven Goossens, Martijn Koedam, Norbert Wehn. 495-500 [doi]
• Coherent crosstalk noise analyses in ring-based optical interconnectsLuan H. K. Duong, Mahdi Nikdast, Jiang Xu, Zhehui Wang, Yvain Thonnart, Sébastien Le Beux, Peng Yang, Xiaowen Wu, Zhifei Wang. 501-506 [doi]
• Enabling vertical wormhole switching in 3D NoC-bus hybrid systemsChanglin Chen, Marius Enachescu, Sorin Dan Cotofana. 507-512 [doi]
• A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architecturesAndrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono. 513-518 [doi]
• Sufficient response time analysis considering dependencies between rate-dependent tasksTimo Feld, Frank Slomka. 519-524 [doi]
• Engine control: task modeling and analysisAlessandro Biondi, Giorgio C. Buttazzo. 525-530 [doi]
• Evaluation of diverse compiling for software-fault detectionAndrea Höller, Nermin Kajtazovic, Tobias Rauter, Kay Römer, Christian Kreiner. 531-536 [doi]
• Worst-case communication time analysis of networks-on-chip with shared virtual channelsEberle A. Rambo, Rolf Ernst. 537-542 [doi]
• On the statistical memory architecture exploration and optimizationCharalampos Antoniadis, Georgios Karakonstantis, Nestor E. Evmorfopoulos, Andreas Peter Burg, George I. Stamoulis. 543-548 [doi]
• ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cellHiromitsu Awano, Masayuki Hiromoto, Takashi Sato. 549-554 [doi]
• Subpage programming for extending the lifetime of NAND flash memoryJung Hoon Kim, Sang-Hoon Kim, Jin-Soo Kim. 555-560 [doi]
• Optimized selection of reliable and cost-effective cyber-physical system architecturesNikunj Bajaj, Pierluigi Nuzzo, Michael Masin, Alberto L. Sangiovanni-Vincentelli. 561-566 [doi]
• Software assisted non-volatile register reduction for energy harvesting based cyber-physical systemMengying Zhao, Qing'an Li, Mimi Xie, Yongpan Liu, Jingtong Hu, Chun Jason Xue. 567-572 [doi]
• A re-entrant flowshop heuristic for online scheduling of the paper path in a large scale printerUmar Waqas, Marc Geilen, Jack Kandelaars, Lou J. Somers, Twan Basten, Sander Stuijk, Patrick Vestjens, Henk Corporaal. 573-578 [doi]
• MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systemsDaniel Münch, Michael Paulitsch, Oliver Hanka, Andreas Herkersdorf. 579-584 [doi]
• Comparison of multi-purpose cores of Keccak and AESPanasayya Yalla, Ekawat Homsirikamol, Jens-Peter Kaps. 585-588 [doi]
• On-line prediction of NBTI-induced aging ratesRafal Baranowski, Farshad Firouzi, Saman Kiamehr, Chang Liu, Mehdi Baradaran Tahoori, Hans-Joachim Wunderlich. 589-592 [doi]
• Retraining-based timing error mitigation for hardware neural networksJiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu. 593-596 [doi]
• Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuitsT. Berkin Cilingiroglu, Mahmoud Zangeneh, Aydan Uyar, W. Clem Karl, Janusz Konrad, Ajay Joshi, Bennett B. Goldberg, M. Selim Ünlü. 597-600 [doi]
• Fault-based attacks on the Bel-T block cipher familyPhilipp Jovanovic, Ilia Polian. 601-604 [doi]
• On the premises and prospects of timing speculationRong Ye, Feng Yuan, Jie Zhang, Qiang Xu. 605-608 [doi]
• Impact of interconnect multiple-patterning variability on SRAMsIoannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene. 609-612 [doi]
• Coherence based message prediction for optically interconnected chip multiprocessorsAnouk Van Laer, Chamath Ellawala, Muhammad Ridwan Madarbux, Philip M. Watts, Timothy M. Jones. 613-616 [doi]
• OpenMP and timing predictability: a possible union?Roberto Vargas, Eduardo Quiñones, Andrea Marongiu. 617-620 [doi]
• SAHARA: a security-aware hazard and risk analysis methodGeorg Macher, Harald Sporer, Reinhard Berlach, Eric Armengaud, Christian Kreiner. 621-624 [doi]
• Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuationSantanu Sarma, Nikil D. Dutt, P. Gupta, Nalini Venkatasubramanian, Alexandru Nicolau. 625-628 [doi]
• Occupancy detection via iBeacon on Android devices for smart building managementA. Corna, L. Fontana, A. A. Nacci, Donatella Sciuto. 629-632 [doi]
• A neural machine interface architecture for real-time artificial lower limb controlJason Kane, Qing Yang, Robert Hernandez, Willard Simoneau, Matthew Seaton. 633-636 [doi]
• The human intranet: where swarms and humans meetJan M. Rabaey. 637-640 [doi]
• Efficient attacks on robust ring oscillator PUF with enhanced challenge-response setPhuong Ha Nguyen, Durga Prasad Sahoo, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay. 641-646 [doi]
• A robust authentication methodology using physically unclonable functions in DRAM arraysMaryam S. Hashemian, Bhanu Pratap Singh, Francis G. Wolff, Daniel J. Weyer, Steve Clay, Christos A. Papachristou. 647-652 [doi]
• A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristicsArunkumar Vijayakumar, Sandip Kundu. 653-658 [doi]
• Asymmetric underlapped FinFET based robust SRAM design at 7nm nodeA. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy. 659-664 [doi]
• Quality configurable reduce-and-rank for energy efficient approximate computingArnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan. 665-670 [doi]
• Ultra-low-power ECG front-end design based on compressed sensingHossein Mamaghanian, Pierre Vandergheynst. 671-676 [doi]
• GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy gamesTony Casagrande, Nagarajan Ranganathan. 677-682 [doi]
• A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clustersFrancesco Conti 0001, Luca Benini. 683-688 [doi]
• Eliminating intra-warp conflict misses in GPUBin Wang, Zhuo Liu, Xinning Wang, Weikuan Yu. 689-694 [doi]
• RNA: a reconfigurable architecture for hardware neural accelerationFengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei. 695-700 [doi]
• ApproxANN: an approximate computing framework for artificial neural networkQian Zhang, Ting Wang, Ye Tian, Feng Yuan, Qiang Xu. 701-706 [doi]
• DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOSMichael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini. 707-712 [doi]
• A small non-volatile write buffer to reduce storage writes in smartphonesMungyu Son, Sungkwang Lee, KyungHo Kim, Sungjoo Yoo, Sunggu Lee. 713-718 [doi]
• Clustering-based multi-touch algorithm framework for the tracking problem with a large number of pointsShih-Lun Huang, Sheng-Yi Hung, Chung-Ping Chen. 719-724 [doi]
• A low energy 2D adaptive median filter hardwareErcan Kalali, Ilker Hamzaoglu. 725-729 [doi]
• Adaptive on-the-fly application performance modeling for many coresSebastian Kobbe, Lars Bauer, Jörg Henkel. 730-735 [doi]
• Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraintsEdoardo Paone, Francesco Robino, Gianluca Palermo, Vittorio Zaccaria, Ingo Sander, Cristina Silvano. 736-741 [doi]
• Enabling multi-threaded applications on hybrid shared memory manycore architecturesTushar Rawat, Aviral Shrivastava. 742-747 [doi]
• Computing approximately, and efficientlySwagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan. 748-751 [doi]
• Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principlesGuru Prakash Arumugam, Prashanth Srikanthan, John Augustine, Krishna V. Palem, Eli Upfal, Ayush Bhargava, Parishkrati, Sreelatha Yenugula. 752-757 [doi]
• Designing inexact systems efficiently using elimination heuristicsShyamsundar Venkataraman, Akash Kumar, Jeremy Schlachter, Christian C. Enz. 758-763 [doi]
• Opportunities for energy efficient computing: a study of inexact general purpose processors for high-performance and big-data applicationsPeter D. Düben, Jeremy Schlachter, Parishkrati, Sreelatha Yenugula, John Augustine, Christian C. Enz, Krishna V. Palem, T. N. Palmer. 764-769 [doi]
• Introduction to hardware trojan detection methodsJulien Francq, Florian Frick. 770-775 [doi]
• New testing procedure for finding insertion sites of stealthy hardware trojansSophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. 776-781 [doi]
• Hardware trojan detection by delay and electromagnetic measurementsXuan Thuy Ngo, Ingrid Exurville, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Jean-Baptiste Rigaud, Bruno Robisson. 782-787 [doi]
• A high efficiency hardware trojan detection technique based on fast SEM imagingFranck Courbon, Philippe Loubet-Moundi, Jacques J. A. Fournier, Assia Tria. 788-793 [doi]
• Mixed wire and surface-wave communication fabrics for decentralized on-chip multicastingAmmar Karkar, Kin-Fai Tong, Terrence S. T. Mak, Alexandre Yakovlev. 794-799 [doi]
• 2-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCsRimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich. 800-805 [doi]
• Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfigurationMarco Balboni, José Flich, Davide Bertozzi. 806-811 [doi]
• Axilog: language support for approximate hardware designAmir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan. 812-817 [doi]
• Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behaviorLaura A. Rozo Duque, Jose M. Monsalve Diaz, Chengmo Yang. 818-823 [doi]
• ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuitsFlorian Kriebel, Semeen Rehman, Duo Sun, Pau Vilimelis Aceituno, Muhammad Shafique, Jörg Henkel. 824-829 [doi]
• Energy minimization for fault tolerant scheduling of periodic fixed-priority applications on multiprocessor platformsQiushi Han, Ming Fan, Linwei Niu, Gang Quan. 830-835 [doi]
• DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan testsSatya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti. 836-841 [doi]
• A scan partitioning algorithm for reducing capture power of delay-fault LBISTNan Li, Elena Dubrova, Gunnar Carlsson. 842-847 [doi]
• Architecture of ring-based redundant TSV for clustered faultsWei-Hen Lo, Kang Chi, TingTing Hwang. 848-853 [doi]
• Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chipPai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu. 854-859 [doi]
• Spiking neural network with RRAM: can we use it for real-world application?Tianqi Tang, Lixue Xia, Boxun Li, Rong Luo, Yiran Chen, Yu Wang, Huazhong Yang. 860-865 [doi]
• Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technologyYusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara. 866-871 [doi]
• STT MRAM-Based PUFsElena Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto. 872-875 [doi]
• Spatial and temporal granularity limits of body biasing in UTBB-FDSOIJohannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel. 876-879 [doi]
• A hardware implementation of a radial basis function neural network using stochastic logicYuan Ji, Feng Ran, Cong Ma, David J. Lilja. 880-883 [doi]
• SODA: software defined FPGA based accelerators for big dataChao Wang, Xi Li, Xuehai Zhou. 884-887 [doi]
• Dynamic reconfigurable puncturing for secure wireless communicationLiang Tang, Jude Angelo Ambrose, Akash Kumar, Sri Parameswaran. 888-891 [doi]
• QR-decomposition architecture based on two-variable numeric function approximationJochen Rust, Frank Ludwig, Steffen Paul. 892-895 [doi]
• In-place memory mapping approach for optimized parallel hardware interleaver architecturesSaeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani. 896-899 [doi]
• Maximizing common idle time on multi-core processors with shared memoryChenchen Fu, Yingchao Zhao, Minming Li, Chun Jason Xue. 900-903 [doi]
• Maximizing IO performance via conflict reduction for flash memory storage systemsQiao Li, Liang Shi, Congming Gao, Kaijie Wu, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 904-907 [doi]
• A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessorsAbbas Mazloumi, Mehdi Modarressi. 908-911 [doi]
• Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog coresJulius von Rosen, Markus Meissner, Lars Hedrich. 912-915 [doi]
• Power-efficient accelerator allocation in adaptive dark silicon many-core systemsMuhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel. 916-919 [doi]
• Thermal-aware floorplanning for partially-reconfigurable FPGA-based systemsDavide Pagano, Mikel Vuka, Marco Rabozzi, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio. 920-923 [doi]
• Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnectsShi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng. 924-927 [doi]
• Analog neuromorphic computing enabled by multi-gate programmable resistive devicesVehbi Calayir, Mohamed Darwish, Jeffrey A. Weldon, Larry Pileggi. 928-931 [doi]
• An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognitionYuhao Wang, Hantao Huang, Leibin Ni, Hao Yu, Mei Yan, Chuliang Weng, Wei Yang, Junfeng Zhao. 932-935 [doi]
• HLC: software-based half-level-cell flash memoryHan-Yi Lin, Jen-Wei Hsieh. 936-941 [doi]
• AHEAD: automated framework for hardware accelerated iterative data analysisEbrahim M. Songhori, Azalia Mirhoseini, Xuyang Lu, Farinaz Koushanfar. 942-947 [doi]
• Design method for multiplier-less two-variable numeric function approximationJochen Rust, Steffen Paul. 948-953 [doi]
• A thermal stress-aware algorithm for power and temperature management of MPSoCsMehdi Kamal, Arman Iranfar, Ali Afzali-Kusha, Massoud Pedram. 954-959 [doi]
• Predictive dynamic thermal and power management for heterogeneous mobile platformsGaurav Singla, Gurinderjit Kaur, Ali K. Unver, Ümit Y. Ogras. 960-965 [doi]
• Power-efficient control of thermoelectric coolers considering distributed hot spotsMohammad Javad Dousti, Massoud Pedram. 966-971 [doi]
• DSP based programmable FHD HEVC decoderSangjo Lee, Joonho Song, Wonchang Lee, Doo-Hyun Kim, Jaehyun Kim, Shihwa Lee. 972-973 [doi]
• Accelerating complex brain-model simulations on GPU platformsH. A. Du Nguyen, Zaid Al-Ars, Georgios Smaragdos, Christos Strydis. 974-979 [doi]
• A packet-switched interconnect for many-core systems with BE and RT serviceRunan Ma, Zhida Hui, Axel Jantsch. 980-983 [doi]
• Reducing trace size in multimedia applications endurance testsSerge Vladimir Emteu Tchagou, Alexandre Termier, Jean-Fraçnois Méhaut, Brice Videau, Miguel Santana, René Quiniou. 984-985 [doi]
• Exploration and design of embedded systems including neural algorithmsJean-Marc Philippe, Alexandre Carbon, Olivier Brousse, Michel Paindavoine. 986-991 [doi]
• A new distributed framework for integration of district energy data from heterogeneous devicesFrancesco G. Brundu, Edoardo Patti, Andrea Acquaviva, Michelangelo Grosso, Gaetano Rasconà, Salvatore Rinaudo, Enrico Macii. 992-993 [doi]
• Spintronic devices as key elements for energy-efficient neuroinspired architecturesNicolas Locatelli, Adrien F. Vincent, Alice Mizrahi, Joseph S. Friedman, Damir Vodenicarevic, Joo-Von Kim, Jacques-Olivier Klein, Weisheng Zhao, Julie Grollier, Damien Querlioz. 994-999 [doi]
• Giant spin hall effect (GSHE) logic design for low power applicationYaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li, Yiran Chen. 1000-1005 [doi]
• Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigmTakahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki. 1006-1011 [doi]
• Potential applications based on NVM emerging technologiesSophiane Senni, Raphael Martins Brum, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard. 1012-1017 [doi]
• From device to system: cross-layer design exploration of racetrack memoryGuangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, YiNan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang. 1018-1023 [doi]
• Efficient bit error rate estimation for high-speed link by Bayesian model fusionChenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li, Chenjie Gu. 1024-1029 [doi]
• Fast deployment of alternate analog test using Bayesian model fusionJohn Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li. 1030-1035 [doi]
• Bordersearch: an adaptive identification of failure regionsMarkus Dobler, Manuel Harrant, Monica Rafaila, Georg Pelz, Wolfgang Rosenstiel, Martin Bogdan. 1036-1041 [doi]
• A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuitsHugo R. Gonçalves, Xin Li, Miguel V. Correia, Vitor Tavares, John M. Carulli Jr., Kenneth M. Butler. 1042-1047 [doi]
• Bytecode-to-C ahead-of-time compilation for Android Dalvik virtual machineHyeong-Seok Oh, Ji Hwan Yeo, Soo-Mook Moon. 1048-1053 [doi]
• A basic linear algebra compiler for embedded processorsNikolaos Kyrtatas, Daniele G. Spampinato, Markus Püschel. 1054-1059 [doi]
• VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon eraNishit Ashok Kapadia, Sudeep Pasricha. 1060-1065 [doi]
• Transparent acceleration of program execution using reconfigurable hardwareNuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso. 1066-1071 [doi]
• Accelerating arithmetic kernels with coherent attached FPGA coprocessorsHeiner Giefers, Raphael Polig, Christoph Hagleitner. 1072-1077 [doi]
• Transparent offloading of computational hotspots from binary code to Xeon PhiMarvin Damschen, Heinrich Riebler, Gavin Vaz, Christian Plessl. 1078-1083 [doi]
• Transparent linking of compiled software and synthesized hardwareDavid B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica. 1084-1089 [doi]
• PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolationA. Psarras, I. Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. 1090-1095 [doi]
• Rate-based vs delay-based control for DVFS in NoCMario R. Casu, Paolo Giaccone. 1096-1101 [doi]
• NoC-enabled multicore architectures for stochastic analysis of biomolecular reactionsTurbo Majumder, Xian Li, Paul Bogdan, Partha Pande. 1102-1107 [doi]
• Optimization of quantum computer architecture using a resource-performance simulatorMuhammad Ahsan, Jungsang Kim. 1108-1113 [doi]
• Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixersChi-Mei Huang, Chia-Hung Liu, Juinn-Dar Huang. 1114-1119 [doi]
• Thermal aware design method for VCSEL-based on-chip optical interconnectHui Li, Alain Fourmigue, Sébastien Le Beux, Xavier Letartre, Ian O'Connor, Gabriela Nicolescu. 1120-1125 [doi]
• Dynamic power and performance back-annotation for fast and accurate functional hardware simulationDongwook Lee, Lizy K. John, Andreas Gerstlauer. 1126-1131 [doi]
• Fast and precise cache performance estimation for out-of-order executionRoeland Douma, Sebastian Altmeyer, Andy D. Pimentel. 1132-1137 [doi]
• A calibration based thermal modeling technique for complex multicore systemsDevendra Rai, Lothar Thiele. 1138-1143 [doi]
• Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applicationsFanshu Jiao, Sergio Montano, Alex Doboli. 1144-1149 [doi]
• A CNN-inspired mixed signal processor based on tunnel transistorsBehnam Sedighi, Indranil Palit, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier. 1150-1155 [doi]
• Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extractionNuno C. Lourenço, Ricardo Martins, Nuno Horta. 1156-1161 [doi]
• Initial transient response of oscillators with long settling timeHans Georg Brachtendorf, Kai Bittner. 1162-1167 [doi]
• Quick error detection tests with fast runtimes for effective post-silicon validation and debugDavid Lin, Eswaran S, Sharad Kumar, Eric Rentschler, Subhasish Mitra. 1168-1173 [doi]
• GPU-accelerated small delay fault simulationEric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich. 1174-1179 [doi]
• Fault simulation with parallel exact critical path tracing in multiple core environmentMaksim Gorev, Raimund Ubar, Sergei Devadze. 1180-1185 [doi]
• On the automatic generation of SBST test programs for in-field testAndreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker. 1186-1191 [doi]
• A comprehensive study of monolithic 3D cell on cell design using commercial 2D toolOlivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, A. Fustier, Julien Michallet, Olivier Faynot, Ogun Turkyilmaz, Jean-Frédéric Christmann, Sebastien Thuries, Fabien Clermidy. 1192-1196 [doi]
• Monolithic 3D integration: a path from concept to realityMax M. Shulaker, Tony F. Wu, Mohamed M. Sabry, Hai Wei, H.-S. Philip Wong, Subhasish Mitra. 1197-1202 [doi]
• A ultra-low-power FPGA based on monolithically integrated RRAMsPierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli. 1203-1208 [doi]
• PWL: a progressive wear leveling to minimize data migration overheads for nand flash devicesFu-Hsin Chen, Ming-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo. 1209-1212 [doi]
• Towards trustable storage using SSDs with proprietary FTLXiaotong Cui, Minhui Zou, Liang Shi, Kaijie Wu. 1213-1216 [doi]
• User-specific skin temperature-aware DVFS for smartphonesBegum Egilmez, Gokhan Memik, Seda Ogrenci Memik, Oguz Ergin. 1217-1220 [doi]
• Formal probabilistic analysis of distributed dynamic thermal managementShafaq Iqtedar, Osman Hasan, Muhammad Shafique, Jörg Henkel. 1221-1224 [doi]
• A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing toolEngin Afacan, Gönenç Berkol, Ali Emre Pusane, Günhan Dündar, I. Faik Baskaya. 1225-1228 [doi]
• Feature selection for alternate test using wrappers: application to an RF LNA case studyManuel J. Barragan, Gildas Leger. 1229-1232 [doi]
• Improving SIMD code generation in QEMUSheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu. 1233-1236 [doi]
• Reuse distance analysis for locality optimization in loop-dominated applicationsChristakis Lezos, Grigoris Dimitroulakos, Konstantinos Masselos. 1237-1240 [doi]
• TAPP: temperature-aware application mapping for NoC-based many-core processorsDi Zhu, Lizhong Chen, Timothy Mark Pinkston, Massoud Pedram. 1241-1244 [doi]
• Malleable NoC: dark silicon inspired adaptable Network-on-ChipHaseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran. 1245-1248 [doi]
• Topology identification for smart cells in modular batteriesSebastian Steinhorst, Martin Lukasiewycz. 1249-1252 [doi]
• LVS check for photonic integrated circuits: curvilinear feature extraction and validationRuping Cao, Julien Billoudet, John Ferguson, Lionel Couder, John Cayo, Alexandre Arriordaz, Ian O'Connor. 1253-1256 [doi]
• FP-scheduling for mode-controlled dataflow: a case studyAlok Lele, Orlando Moreira, Kees van Berkel. 1257-1260 [doi]
• Ageing simulation of analogue circuits and systems using adaptive transient evaluationFelix Salfelder, Lars Hedrich. 1261-1264 [doi]
• A tool for the assisted design of charge redistribution SAR ADCsStefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita. 1265-1268 [doi]
• Detection of asymmetric aging-critical voltage conditions in analog power-down modeMichael Zwerger, Helmut E. Graeb. 1269-1272 [doi]
• High performance single supply CMOS inverter level up shifter for multi: supply voltages domainsJosé C. García, Juan A. Montiel-Nelson, Javier Sosa, Saeid Nooshabadi. 1273-1276 [doi]
• Exploring the impact of functional test programs re-used for power-aware testingA. Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda. 1277-1280 [doi]
• A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoCHsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee. 1281-1284 [doi]
• Fault diagnosis in designs with extreme low pin test data compressorsSubhadip Kundu, Parthajit Bhattacharya, Rohit Kapur. 1285-1288 [doi]
• Optimizing dynamic trace signal selection using machine learning and linear programmingCharlie Shucheng Zhu, Sharad Malik. 1289-1292 [doi]
• Gait analysis for fall prediction using hierarchical textile-based capacitive sensor arraysRebecca Baldwin, Stan Bobovych, Ryan Robucci, Chintan Patel, Nilanjan Banerjee. 1293-1298 [doi]
• HReRAM: a hybrid reconfigurable resistive random-access memoryMiguel Angel Lastras-Montaño, Amirali Ghofrani, Kwang-Ting Cheng. 1299-1304 [doi]
• nCode: limiting harmful writes to emerging mobile NVRAM through code swappingKan Zhong, Duo Liu, Linbo Long, Xiao Zhu, Weichen Liu, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 1305-1310 [doi]
• System level exploration of a STT-MRAM based level 1 data-cacheManu Perumkunnil Komalan, Christian Tenllado, José Ignacio Gómez Perez, Francisco Tirado Fernández, Francky Catthoor. 1311-1316 [doi]
• High performance AXI-4.0 based interconnect for extensible smart memory cubesErfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini. 1317-1322 [doi]
• The federated scheduling of constrained-deadline sporadic DAG task systemsSanjoy Baruah. 1323-1328 [doi]
• Run and be safe: mixed-criticality scheduling with temporary processor speedupPengcheng Huang, Pratyush Kumar, Georgia Giannopoulou, Lothar Thiele. 1329-1334 [doi]
• Multi-core fixed-priority scheduling of real-time tasks with statistical deadline guaranteeTianyi Wang, Linwei Niu, Shaolei Ren, Gang Quan. 1335-1340 [doi]
• Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processingEunhyeok Park, Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Sunggu Lee. 1341-1346 [doi]
• Power minimization for data center with guaranteed QoSShuo Liu, Soamar Homsi, Ming Fan, Shaolei Ren, Gang Quan, Shangping Ren. 1347-1352 [doi]
• Energy-aware cooling for hot-water cooled supercomputersChristian Conficoni, Andrea Bartolini, Andrea Tilli, Giampietro Tecchiolli, Luca Benini. 1353-1358 [doi]
• Hybrid adaptive clock management for FPGA processor accelerationAlexandru Gheolbanoiu, Lucian Petrica, Sorin Cotofana. 1359-1364 [doi]
• A scalable and high-density FPGA architecture with multi-level phase change memoryChunan Wei, Ashutosh Dhar, Deming Chen. 1365-1370 [doi]
• FPGA accelerated DNA error correctionAnand Ramachandran, Yun Heo, Wen-mei W. Hwu, Jian Ma, Deming Chen. 1371-1376 [doi]
• Fast eye diagram analysis for high-speed CMOS circuitsSeyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan. 1377-1382 [doi]
• Statistical library characterization using belief propagation across multiple technology nodesLi Yu, Sharad Saxena, Christopher Hess, Ibrahim M. Elfadel, Dimitri A. Antoniadis, Duane S. Boning. 1383-1388 [doi]
• Combining adaptive alternate test and multi-siteGildas Leger. 1389-1394 [doi]
• A method for the estimation of defect detection probability of analog/RF defect-oriented testsJohn Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas. 1395-1400 [doi]
• Automated rectification methodologies to functional state-space unreachabilityRyan Berryhill, Andreas G. Veneris. 1401-1406 [doi]
• Over-approximating loops to prove properties using bounded model checkingPriyanka Darke, Bharti Chimdyalwar, R. Venkatesh, Ulka Shrotri, Ravindra Metta. 1407-1412 [doi]
• Automatic extraction of micro-architectural models of communication fabrics from register transfer level designsSebastiaan J. C. Joosten, Julien Schmaltz. 1413-1418 [doi]
• GALS synthesis and verification for xMAS modelsFrank P. Burns, Danil Sokolov, Alexandre Yakovlev. 1419-1424 [doi]
• Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE modelH. Li, Z. Jiang, P. Huang, Y. Wu, H. Y. Chen, B. Gao, X. Y. Liu, J. F. Kang, H.-S. P. Wong. 1425-1430 [doi]
• Impact of process-variations in STTRAM and adaptive boosting for robustnessSeyedhamidreza Motaman, Swaroop Ghosh, Nitin Rathi. 1431-1436 [doi]
• Device/circuit/architecture co-design of reliable STT-MRAMZoha Pajouhi, Xuanyao Fong, Kaushik Roy. 1437-1442 [doi]
• Sub-10 nm FinFETs and Tunnel-FETs: from devices to systemsAnkit Sharma, A. Arun Goud, Kaushik Roy. 1443-1448 [doi]
• A new approximate adder with low relative error and correct sign calculationJunjun Hu, Weikang Qian. 1449-1454 [doi]
• Towards binary circuit models that faithfully capture physical solvabilityMatthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid. 1455-1460 [doi]
• A coupling area reduction technique applying ODC shiftingYi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu. 1461-1466 [doi]
• A general design of stochastic circuit and its synthesisZheng Zhao, Weikang Qian. 1467-1472 [doi]
• Paper, pen and ink: an innovative system and software framework to assist writing rehabilitationLeonardo Guardati, Filippo Casamassima, Elisabetta Farella, Luca Benini. 1473-1478 [doi]
• An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmissionMasoud Shahshahani Amirhossein, Paolo Motto Ros, Alberto Bonanno, Marco Crepaldi, Maurizio Martina, Danilo Demarchi, Guido Masera. 1479-1484 [doi]
• A pulsed-index technique for single-channel, low-power, dynamic signalingShahzad Muzaffar, Jerald Yoo, Ayman Shabra, Ibrahim Abe M. Elfadel. 1485-1490 [doi]
• SAPPHIRE: an always-on context-aware computer vision system for portable devicesSwagath Venkataramani, Victor Bahl, Xian-Sheng Hua, Jie Liu, Jin Li, Matthai Philipose, Bodhi Priyantha, Mohammed Shoaib. 1491-1496 [doi]
• Approximate associative memristive memory for energy-efficient GPUsAbbas Rahimi, Amirali Ghofrani, Kwang-Ting Cheng, Luca Benini, Rajesh K. Gupta. 1497-1502 [doi]
• Platform-aware dynamic configuration support for efficient text processing on heterogeneous systemMi Sun Park, Omesh Tickoo, Vijaykrishnan Narayanan, Mary Jane Irwin, Ravi Iyer. 1503-1508 [doi]
• A deblocking filter hardware architecture for the high efficiency video coding standardCláudio Machado Diniz, Muhammad Shafique, Felipe Vogel Dalcin, Sergio Bampi, Jörg Henkel. 1509-1514 [doi]
• MatEx: efficient transient and peak temperature computation for compact thermal modelsSantiago Pagani, Jian-Jia Chen, Muhammad Shafique, Jörg Henkel. 1515-1520 [doi]
• Distributed reinforcement learning for power limited many-core system performance optimizationZhuo Chen, Diana Marculescu. 1521-1526 [doi]
• An energy-efficient virtual channel power-gating mechanism for on-chip networksAmirhossein Mirhosseini, Mohammad Sadrosadati, Ali Fakhrzadehgan, Mehdi Modarressi, Hamid Sarbazi-Azad. 1527-1532 [doi]
• M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processorsYoung-geun Kim, Minyong Kim, Jae Min Kim, Sung Woo Chung. 1533-1538 [doi]
• Towards systematic design of 3D pNML layoutsRobert Perricone, Yining Zhu, Katherine M. Sanders, Xiaobo Sharon Hu, Michael T. Niemier. 1539-1542 [doi]
• DESTINY: a tool for modeling emerging 3D NVM and eDRAM cachesMatt Poremba, Sparsh Mittal, Dong Li, Jeffrey S. Vetter, Yuan Xie. 1543-1546 [doi]
• Big-data streaming applications scheduling with online learning and concept drift detectionKarim Kanoun, Mihaela van der Schaar. 1547-1550 [doi]
• Design flow and run-time management for compressed FPGA configurationsChristophe Huriaux, Antoine Courtay, Olivier Sentieys. 1551-1554 [doi]
• Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulationWael Dghais, Jonathan Rodriguez. 1555-1558 [doi]
• On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADCOsman Emir Erol, Sule Ozev, Chandra K. H. Suresh, Rubin A. Parekhji, Lakshmanan Balasubramanian. 1559-1562 [doi]
• Logical equivalence checking of asynchronous circuits using commercial toolsArash Saifhashemi, Hsin-Ho Huang, Priyanka Bhalerao, Peter A. Beerel. 1563-1566 [doi]
• May-happen-in-parallel analysis of ESL models using UPPAAL model checkingChe-Wei Chang, Rainer Dömer. 1567-1570 [doi]
• Verifying synchronous reactive systems using lazy abstractionKumar Madhukar, Mandayam Srivas, Björn Wachter, Daniel Kroening, Ravindra Metta. 1571-1574 [doi]
• Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computingRangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan. 1575-1578 [doi]
• Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing techniqueJi Li, Qing Xie, Yanzhi Wang, Shahin Nazarian, Massoud Pedram. 1579-1582 [doi]
• SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encodingHong-Yan Su, Chih-Hao Hsu, Yih-Lang Li. 1583-1586 [doi]
• Timing verification for adaptive integrated circuitsRohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu. 1587-1590 [doi]
• A robust approach for process variation aware mask optimizationJian Kuang 0001, Wing-Kai Chow, Evangeline F. Y. Young. 1591-1594 [doi]
• FastTree: a hardware KD-tree construction acceleration engine for real-time ray tracingXingyu Liu, Yangdong Deng, Yufei Ni, Zonghui Li. 1595-1598 [doi]
• Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systemsChristian Brugger, Javier Alejandro Varela, Norbert Wehn, Songyin Tang, Ralf Korn. 1599-1602 [doi]
• Accurate electrothermal modeling of thermoelectric generatorsMohammad Javad Dousti, Antonio Petraglia, Massoud Pedram. 1603-1606 [doi]
• Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnectQing Xie, Younghyun Kim, Donkyu Baek, Yanzhi Wang, Massoud Pedram, Naehyuck Chang. 1607-1610 [doi]
• An ultra-low power dual-mode ECG monitor for healthcare and wellnessDaniele Bortolotti, Mauro Mangia, Andrea Bartolini, Riccardo Rovatti, Gianluca Setti, Luca Benini. 1611-1616 [doi]
• Solving DQBF through quantifier eliminationKarina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker. 1617-1622 [doi]
• Formal verification of sequential Galois field arithmetic circuits using algebraic geometryXiaojun Sun, Priyank Kalla, Tim Pruss, Florian Enescu. 1623-1628 [doi]
• A universal macro block mapping scheme for arithmetic circuitsXing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu. 1629-1634 [doi]
• Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checkingKhaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria. 1635-1640 [doi]
• An effective triple patterning aware grid-based detailed routing approachZhiqing Liu, Chuangwen Liu, Evangeline F. Y. Young. 1641-1646 [doi]
• Simultaneous transistor pairing and placement for CMOS standard cellsAng Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang, Rung-Bin Lin. 1647-1652 [doi]
• A TSV noise-aware 3-D placerYu-Min Lee, Chun Chen, Jiaxing Song, Kuan-Te Pan. 1653-1658 [doi]
• Identifying redundant inter-cell margins and its application to reducing routing congestionWoohyun Chung, Seongbo Shim, Youngsoo Shin. 1659-1664 [doi]
• Models for deterministic execution of real-time multiprocessor applicationsPeter Poplavko, Dario Socci, Paraskevas Bourgos, Saddek Bensalem, Marius Bozga. 1665-1670 [doi]
• Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computationLiliana Andrade, Torsten Maehne, Alain Vachoux, Cédric Ben Aoun, François Pêcheux, Marie-Minerve Louërat. 1671-1676 [doi]
• Formal consistency checking over specifications in natural languagesRongjie Yan, Chih-Hong Cheng, Yesheng Chai. 1677-1682 [doi]
• Tackling the bottleneck of delay tables in 3D ultrasound imagingA. Ibrahim, P. Hager, Andrea Bartolini, Federico Angiolini, M. Arditi, Luca Benini, Giovanni De Micheli. 1683-1688 [doi]
• Integrated CMOS receiver for wearable coil arrays in MRI applicationsBenjamin Sporrer, Luca Bettini, Christian Vogt, Andreas Mehmann, Jonas Reber, Josip Marjanovic, David O. Brunner, Thomas Burger, Klaas P. Pruessmann, Gerhard Tröster, Qiuting Huang. 1689-1694 [doi]
• Tactile prosthetics in WiseSkinJ. Farserotu, Jean-Dominique Decotignie, J. Baborowski, P.-N. Volpe, C. R. Quirós, V. Kopta, Christian C. Enz, S. Lacour, H. Michaud, R. Martuzzi, V. Koch, H. Huang, T. Li, C. Antfolk. 1695-1697 [doi]
• The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systemsOliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh. 1698-1707 [doi]
• Multi/many-core programming: where are we standing?Jerónimo Castrillón, Lothar Thiele, Lars Schor, Weihua Sheng, Ben Juurlink, Mauricio Alvarez Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers. 1708-1717 [doi]
• Memristor based computation-in-memory architecture for data-intensive applicationsSaid Hamdioui, Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Koen Bertels, Henk Corporaal, Hailong Jiao, Francky Catthoor, Dirk Wouters, Linn Eike, Jan van Lunteren. 1718-1725 [doi]
• The future of electronics, semiconductors, and design in Europe: panelMarco Casale-Rossi, Giovanni De Micheli, Jalal Bagherli, Thierry Collette, Antun Domic, Horst Symanzik, Hossein Yassaie. 1726-1728 [doi]