Abstract is missing.
- Variability modeling and variability-aware design in deep submicron integrated circuitsFlorentin Dartu, Anirudh Devgan, Noel Menezes. 1 [doi]
- On-chip power distribution grids with multiple supply voltages for high performance integrated circuitsMikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny. 2-7 [doi]
- Low power test generation for path delay faults using stability functionsMahilchi Milir Vaseekar Kumar, Spyros Tragoudas. 8-12 [doi]
- Physical limitations on the bit-rate of on-chip interconnectsNoha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail. 13-19 [doi]
- Interconnect delay minimization through interlayer via placement in 3-D ICsVasilis F. Pavlidis, Eby G. Friedman. 20-25 [doi]
- Thermal aware cell-based full-chip electromigration reliability analysisSyed M. Alam, Donald E. Troxel, Carl V. Thompson. 26-31 [doi]
- Accounting for the skin effect during repeater insertionDaniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors. 32-37 [doi]
- Characterization of the impact of interconnect design on the capacitive load driven by a global clock distributionGerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti. 38-43 [doi]
- Instruction scheduling using ::::MAX-MIN:::: ant system optimizationGang Wang, Wenrui Gong, Ryan Kastner. 44-49 [doi]
- A unified processor architecture for RISC & VLIW DSPTay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen. 50-55 [doi]
- Zero clustering: an approach to extend zero compression to instruction cachesKimish Patel, Enrico Macii, Massimo Poncino. 56-59 [doi]
- A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technologyAlireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede. 60-63 [doi]
- PIM lite: a multithreaded processor-in-memory prototypeShyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler. 64-69 [doi]
- Characterizing the VCO jitter due to the digital simultaneous switching noiseTian Xia, Peilin Song, Hao Zheng. 70-73 [doi]
- Exact minimum-width transistor placement without dual constraint for CMOS cellsTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. 74-77 [doi]
- High-diagnosability online built-in self-test of FPGAs via iterative bootstrappingVishal Suthar, Shantanu Dutt. 78-83 [doi]
- An improved direct boundary element method for substrate coupling resistance extractionXiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong. 84-87 [doi]
- Generating decision regions in analog measurement spacesHaralampos-G. D. Stratigopoulos, Yiorgos Makris. 88-91 [doi]
- Integer linear programming based energy optimization for banked DRAMsOzcan Ozturk, Mahmut T. Kandemir. 92-95 [doi]
- Slack borrowing in flip-flop based sequential circuitsAmit Jain, David Blaauw. 96-101 [doi]
- On equivalence checking and logic synthesis of circuits with a common specificationEugene Goldberg. 102-107 [doi]
- Quantum-dot cellular automata SPICE macro modelRui Tang, Fengming Zhang, Yong-Bin Kim. 108-111 [doi]
- Causal probabilistic input dependency learning for switching model in VLSI circuitsNirmal Ramalingam, Sanjukta Bhanja. 112-115 [doi]
- Area-efficient two-dimensional architectures for finite field inversion and divisionZhiyuan Yan, Dilip V. Sarwate. 116-121 [doi]
- 2.5GHz PLL with current matching charge-pump for 10Gbps transmitter designJaehong Ko, Wookwan Lee, Soo-Won Kim. 122-125 [doi]
- The oct-touched tile: a new architecture for shape-based routingNing Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani. 126-129 [doi]
- System level design language extensions for timed/untimed digital-analog combined system designYu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita. 130-133 [doi]
- Noise-tolerant high fan-in dynamic CMOS circuit designWalid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi. 134-137 [doi]
- Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizerLei Yang, Cherry Wakayama, C.-J. Richard Shi. 138-142 [doi]
- Improved multilevel routing with redundant via placement for yield and reliabilityHailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou. 143-146 [doi]
- An FPGA design of AES encryption circuit with 128-bit keysHui Qin, Tsutomu Sasao, Yukihiro Iguchi. 147-151 [doi]
- High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completionEun-Gu Jung, Jeong-Gun Lee, Sang-Hoon Kwak, Kyoung-Sun Jhang, Jeong-A. Lee, Dong-Soo Har. 152-155 [doi]
- Fixed-outline floorplanning based on common subsequenceRong Liu, Sheqin Dong, Xianlong Hong. 156-159 [doi]
- Interconnect capacitance extraction for system LCD circuitsYoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa. 160-163 [doi]
- Two-prime RSA immune cryptosystem and its FPGA implementationYing Yang, Zine-Eddine Abid, Wei Wang. 164-167 [doi]
- A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICsSushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural. 168-171 [doi]
- Digital cell macro-model with regular substrate template and EKV based MOSFET modelYulei Weng, Alex Doboli. 172-175 [doi]
- Untestable fault identification through enhanced necessary value assignmentsVishnu C. Vimjam, Manan Syal, Michael S. Hsiao. 176-181 [doi]
- Test set enhancement for quality transition faults using function-based methodsStelios Neophytou, Maria K. Michael, Spyros Tragoudas. 182-187 [doi]
- Two dimensional reordering of functional test data for compression by ATEHamidreza Hashempour, Fabrizio Lombardi. 188-192 [doi]
- Diagnosing multiple transition faults in the absence of timing informationJiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour. 193-196 [doi]
- An EFSM-based approach for functional ATPGFranco Fummi, Cristina Marconcini, Graziano Pravadelli. 197-200 [doi]
- Tile-based design of a serial memory in QCAVamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi. 201-206 [doi]
- Multi-GHz SiGe design methodologies for reconfigurable computingKuan Zhou, John F. McDonald. 207-212 [doi]
- Low-power circuits using dynamic threshold devicesPaul Beckett. 213-216 [doi]
- QCA channel routing with wire crossing minimizationBrian Stephen Smith, Sung Kyu Lim. 217-220 [doi]
- A new algorithm for layout of dark field alternating phase shifting masksQinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai. 221-224 [doi]
- Research and development for seamless mobilityVida Ilderem. 225 [doi]
- DIP: a double-interval-based dynamic voltage scaling scheme for dynamic priority-based task scheduling systemsSookyoung Kim, Thomas L. Martin. 226-231 [doi]
- Energy optimization in memory address bus structure for application-specific systemsLiang Deng, Martin D. F. Wong. 232-237 [doi]
- Fine-grain leakage optimization in SRAM based FPGAsSomsubhra Mondal, Seda Ogrenci Memik. 238-243 [doi]
- A sensitivity analysis of low-power repeater insertionYuantao Peng, Xun Liu. 244-247 [doi]
- An effective and efficient ATPG-based combinational equivalence checkerRonald P. Lajaunie, Michael S. Hsiao. 248-253 [doi]
- Forward image computation with backtracing ATPG and incremental state-set constructionKameshwar Chandrasekar, Michael S. Hsiao. 254-259 [doi]
- Verification of behavioral descriptions by combining symbolic simulation and automatic reasoningGhiath Al Sammane, Dominique Borrione, Remy Chevallier. 260-263 [doi]
- Utilizing don t care states in SAT-based bounded sequential problemsSean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler. 264-269 [doi]
- Energy management in software-controlled multi-level memory hierarchiesOzcan Ozturk, Mahmut T. Kandemir. 270-275 [doi]
- Exploring the energy efficiency of cache coherence protocols in single-chip multi-processorsMirko Loghi, Martin Letis, Luca Benini, Massimo Poncino. 276-281 [doi]
- Load elimination for low-power embedded processorsGokhan Memik, Mahmut T. Kandemir, Arindam Mallik. 282-285 [doi]
- An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designsChin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu. 286-290 [doi]
- A VLSI array processing oriented fast fourier transform algorithm and hardware implementationZhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto. 291-295 [doi]
- A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approachKamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi. 296-301 [doi]
- A complete methodology for an accurate static noise analysisCristiano Forzan, Davide Pandini. 302-307 [doi]
- A new approach to the use of satisfiability in false path detectionFelipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. 308-311 [doi]
- Optimization objectives and models of variation for statistical gate sizingMatthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown. 313-316 [doi]
- An empirical study of crosstalk in VDSM technologiesShahin Nazarian, Massoud Pedram, Emre Tuncer. 317-322 [doi]
- A hardware/software codesign approach for programmable IO devicesKuan Jen Lin, Shih Hao Huang, Shih Wen Chen. 323-327 [doi]
- Analysis and design of soft-error hardened latchesSrivathsan Krishnamohan, Nihar R. Mahapatra. 328-331 [doi]
- Clock skew bounds estimation under power supply and process variationsHailin Jiang, Kai Wang, Malgorzata Marek-Sadowska. 332-336 [doi]
- Tool integration using the web-services approachJoão Daniel Togni, Renato P. Ribas, Maria Lúcia Blanck Lisbôa, André Inácio Reis. 337-340 [doi]
- VLSI CAD tool protection by birthmarking design solutionsLin Yuan, Gang Qu, Ankur Srivastava. 341-344 [doi]
- A continuous time markov decision process based on-chip buffer allocation methodologySankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Eugene A. Feinberg. 345-348 [doi]
- The G:::4:::-FET: a universal and programmable logic gateAmir Fijany, Farrokh Vatan, Mohammad Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil. 349-352 [doi]
- Using data compression in an MPSoC architecture for improving performanceOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin. 353-356 [doi]
- Dual-transition glitch filtering in probabilistic waveform power estimationFei Hu, Vishwani D. Agrawal. 357-360 [doi]
- SOFTENIT: a methodology for boosting the software content of system-on-chip designsAbhishek Mitra, Marcello Lajolo, Kanishka Lahiri. 361-366 [doi]
- Low-overhead state-retaining elements for low-leakage MTCMOS designPietro Babighian, Luca Benini, Alberto Macii, Enrico Macii. 367-370 [doi]
- Enhancing error resilience for reliable compression of VLSI test dataHamidreza Hashempour, Luca Schiano, Fabrizio Lombardi. 371-376 [doi]
- Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMsPrassanna Sithambaram, Alberto Macii, Enrico Macii. 377-380 [doi]
- Total leakage optimization strategies for multi-level cachesRobert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge. 381-384 [doi]
- Design of a cell library for asynchronous microenginesGaurav Gulati, Erik Brunvand. 385-389 [doi]
- Moment-driven coupling-aware routing methodologyAmitava Bhaduri, Ranga Vemuri. 390-395 [doi]
- New algorithms for carry propagationJohannes Grad, James E. Stine. 396-399 [doi]
- Exploiting PSL standard assertions in a theorem-proving-based verification environmentYoungsik Kim, Parija Sule, Nazanin Mansouri. 400-403 [doi]
- Increasing design space of the instruction queue with tag codingJunwei Zhou, Andrew Mason. 404-407 [doi]
- Characterization of monotonic static CMOS gates in a 65nm technologyAli Bastani, Charles A. Zukowski. 408-411 [doi]
- An analysis of the robustness of CMOS delay elementsSrivathsan Krishnamohan, Nihar R. Mahapatra. 412-415 [doi]
- A first look at the interplay of code reordering and configurable cachesAnn Gordon-Ross, Frank Vahid, Nikil Dutt. 416-421 [doi]
- FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networksAbdallah Merhebi, Otmane Aït Mohamed. 422-425 [doi]
- VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp inputSoroush Abbaspour, Hanif Fatemi, Massoud Pedram. 426-430 [doi]
- 1-V 7-mW dual-band fast-locked frequency synthesizerVikas Sharma, Chien-Liang Chen, Chung-Ping Chen. 431-435 [doi]
- Increasing the energy efficiency of pipelined circuits via slack redistributionSrivathsan Krishnamohan, Nihar R. Mahapatra. 436-441 [doi]
- Adaptive digital techniques to suppress quantization noise of Sigma Delta analog to digital convertersBahar Jalali Farahani, Mohammed Ismail. 442-445 [doi]
- Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routingAjay Joshi, Jeffrey A. Davis. 446-451 [doi]
- LiPaR: A light-weight parallel router for FPGA-based networks-on-chipBalasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri. 452-457 [doi]
- 3D module placement for congestion and power noise reductionJacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh. 458-461 [doi]
- A novel buffer circuit for energy efficient signaling in dual-VDD systemsHimanshu Kaul, Dennis Sylvester. 462-467 [doi]
- Energy recovery clocked dynamic logicMatthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy. 468-471 [doi]
- Adaptive gate biasing: a new solution for body-driven current mirrorsStephen C. Terry, Mohommad M. Mojarradi, Benjamin J. Blalock, Jesse A. Richmond. 472-477 [doi]
- A high speed and leakage-tolerant domino logic for high fan-in gatesFarshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi. 478-481 [doi]
- Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuitsAnuradha Agarwal, Glenn Wolfe, Ranga Vemuri. 482-487 [doi]
- A congestion-driven placement framework with local congestion predictionQinghua Liu, Malgorzata Marek-Sadowska. 488-493 [doi]
- Reticle floorplanning of flexible chips for multi-project wafersMeng-Chiou Wu, Rung-Bin Lin. 494-497 [doi]
- A study of tighter lower bounds in LP relaxation based placementQingzhou (Ben) Wang, Devang Jariwala, John Lillis. 498-502 [doi]