Abstract is missing.
- Steering/Advisory Committee [doi]
- Conference at a Glance [doi]
- Technical Subcommittees [doi]
- Welcome Notes [doi]
- Organizing Committee [doi]
- Design of sub-90nm Circuits and Design MethodologiesAnirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi. 3-4 [doi]
- Modeling and Design of Chip-Package InterfaceAnirudh Devgan, Luca Daniel, Byron Krauter, Lei He. 6 [doi]
- IP Creation and Use What Roadblocks are Ahead or it is Just Clear and Bumpy Road?Pallab K. Chatterjee. 7-9 [doi]
- Enabling True Design for ManufacturabilityJohn Kibarian. 15 [doi]
- Recent Progress and Remaining Challenges in Pattern Transfer Technologies for Advanced Chip DesignsAshok K. Sinha. 17 [doi]
- Shifting Perspective on DFMJoseph Sawicki. 19 [doi]
- Toward Quality EDA Tools and Tool Flows Through High-Performance ComputingAaron N. Ng, Igor L. Markov. 22-27 [doi]
- Noise Library Characterization for Large Capacity Static Noise Analysis ToolsAlex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda. 28-34 [doi]
- Two-Dimensional Layout Migration by Soft Constraint SatisfactionQianying Tang, Jianwen Zhu. 35-39 [doi]
- Domain Strategy and Coverage Metric for ValidationLuo Chun, Yang Jun, Shi Longxing, Wu XuFan, Zhang Yu. 40-45 [doi]
- Power Supply Noise-Aware Scheduling and Allocation for DSP SynthesisDongku Kang, Yiran Chen, Kaushik Roy. 48-53 [doi]
- Reducing Power Consumption during TLB Lookups in a PowerPC Embedded ProcessorShivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman. 54-58 [doi]
- TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling TechniqueKee-Jong Kim, Chris H. Kim, Kaushik Roy. 59-64 [doi]
- Error Analysis for the Support of Robust Voltage ScalingDavid Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner. 65-70 [doi]
- Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFETBhavana Jharia, Sankar Sarkar, R. P. Agarwal. 72-76 [doi]
- Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI CircuitsAfshin Abdollahi, Farzan Fallah, Massoud Pedram. 77-82 [doi]
- Controlled-Load Limited Switch Dynamic Logic CircuitJayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown. 83-87 [doi]
- Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk MinimizationHarmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka. 88-93 [doi]
- Charge-Based Core and the Model Architecture of BSIM5Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu. 96-101 [doi]
- Integration Of Design For Manufacturability (DFM) Practices In Design FlowsLionel Riviere-Cazaux, Kevin Lucas, Jon Fitch. 102-106 [doi]
- How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon ResultsCarlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles. 107-112 [doi]
- Leakage Current Modeling in PD SOI CircuitsMini Nanua, David Blaauw, Chanhee Oh. 113-117 [doi]
- A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA CompanyJasjeet Kaur. 118-122 [doi]
- Issues and Challenges in Ramp to ProductionArun Shrimali, Anand Venkitachalam, Ravi Arora. 123-127 [doi]
- A Technique for Designing Totally Self-Checking Domino Logic CircuitsC. K. Tang, Parag K. Lala, James Patrick Parkerson. 128-132 [doi]
- Early Assessment of Leakage Power for System Level DesignC. Talarico, B. Pillilli, K. L. Vakati, J. M. Wang. 133-136 [doi]
- Technology Mapping for Reliability Enhancement in Logic SynthesisZhaojun Wo, Israel Koren. 137-142 [doi]
- Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor ArraysDiaaEldin Khalil, Mohamed Dessouky, Vincent Bourguet, Marie-Minerve Louërat, Andreia Cathelin, Hani Ragai. 143-147 [doi]
- Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance AddersBehnam Amelifard, Farzan Fallah, Massoud Pedram. 148-152 [doi]
- Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect ArchitectureAtsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda. 153-158 [doi]
- Testing for Resistive Shorts in FPGA InterconnectsHaixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong. 159-163 [doi]
- TED Thermo Electrical Designer: A New Physical Design Verification ToolEwa Sokolowska, M. Barszcz, Bozena Kaminska. 164-168 [doi]
- A Fast Lithography Verification Framework for Litho-Friendly Layout DesignYong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong. 169-174 [doi]
- Gate-Level Mitigation Techniques for Neutron-Induced Soft Error RateHarmander Deogun, Dennis Sylvester, David Blaauw. 175-180 [doi]
- Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal LayerHua Xiang, Kai-Yuan Chao, Martin D. F. Wong. 181-186 [doi]
- Design of a 10-bit TSMC 0.25um CMOS Digital to Analog ConverterJ. Huynh, B. Ngo, M. Pham, Lili He. 187-192 [doi]
- A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoCR. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh. 193-196 [doi]
- Design and Evaluation of a Security Scheme for Sensor NetworksKhadija Stewart, Themistoklis Haniotakis, Spyros Tragoudas. 197-201 [doi]
- A Minimum Cut Based Re-Synthesis ApproachM. Welling, Spyros Tragoudas, Haibo Wang. 202-207 [doi]
- Analysis for Complex Power Distribution Networks Considering Densely Populated ViasYoung-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong. 208-212 [doi]
- Buffer Planning Algorithm Based on Partial Clustered FloorplanningYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng. 213-219 [doi]
- IP Quality: A Design, Not a Verification ProblemMichael Keating. 220-224 [doi]
- Reseeding-Based Test Set Embedding with Reduced Test SequencesEmmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos. 226-231 [doi]
- Reduced Test Application Time Based on Reachability AnalysisThemistoklis Haniotakis, Spyros Tragoudas, G. Pani. 232-237 [doi]
- Using MUXs Network to Hide Bunches of Scan ChainsYinhe Han, Yu Hu, Huawei Li, Xiaowei Li. 238-243 [doi]
- BIST-Guided ATPGAhmad A. Al-Yamani, Edward J. McCluskey. 244-249 [doi]
- Dynamic Test Compaction for Bridging FaultsIrith Pomeranz, Sudhakar M. Reddy. 250-255 [doi]
- A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical PolishingXin Wang, Charles Chiang, Jamil Kawa, Qing Su. 258-263 [doi]
- Standard Cell Printability Grading and Hot Spot DetectionMichel Côté, Philippe Hurat. 264-269 [doi]
- Performance Driven OPC for Mask Cost ReductionPuneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang. 270-275 [doi]
- Meeting Nanometer DPM Requirements Through DFTJay Jahangiri, David Abercrombie. 276-282 [doi]
- Parametric Yield Analysis and Constrained-Based Supply Voltage OptimizationRahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown. 284-290 [doi]
- Power-Delay Metrics Revisited for 90nm CMOS TechnologyDipanjan Sengupta, Resve A. Saleh. 291-296 [doi]
- Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary AlgorithmJustin Gregg, Tom W. Chen. 297-302 [doi]
- Electromigration Reliability Comparison of Cu and Al InterconnectsSyed M. Alam, Frank L. Wei, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel. 303-308 [doi]
- Combining System Level Modeling with Assertion Based VerificationAnat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal, Lyes Benalycherif, Romain Kamdem, Younes Lahbib. 310-315 [doi]
- Low Voltage Test in Place of Fast Clock in DDSI Delay TestHaihua Yan, Gefu Xu, Adit D. Singh. 316-320 [doi]
- Functional Verification of Networked Embedded SystemsNicola Bombieri, Franco Fummi, Graziano Pravadelli. 321-326 [doi]
- Functions for Quality Transition Fault TestsMaria K. Michael, Stelios Neophytou, Spyros Tragoudas. 327-332 [doi]
- Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution SystemsMikhail Popovich, Eby G. Friedman. 334-339 [doi]
- P/G Pad Placement Optimization: Problem Forumulation for Best IR DropAishwarya Dubey. 340-345 [doi]
- Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated CircuitsNavin Srivastava, Xiaoning Qi, Kaustav Banerjee. 346-351 [doi]
- Power Grid Planning for Microprocessors and SOCSQing K. Zhu, David Ayers. 352-356 [doi]
- A Power-Aware GALS Architecture for Real-Time Algorithm-Specific TasksAnimesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy. 358-363 [doi]
- An ILP Formulation for Reliability-Oriented High-Level SynthesisSuleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung. 364-369 [doi]
- Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical DerivationsHaixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong. 370-374 [doi]
- Reliability-Centric Hardware/Software Co-DesignSuleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung. 375-380 [doi]
- Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICEXiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael Talmor, Z. Gur, Joseph B. Bernstein. 382-389 [doi]
- Modeling Layout Effects for Sensitivity-Based Analog Circuit OptimizationHenry H. Y. Chan, Zeljko Zilic. 390-395 [doi]
- In-Circuit Self-Tuning of Clock LatenciesKambiz Rahimi, Chris Diorio. 396-401 [doi]
- Statistical Analysis of Clock Skew Variation in H-Tree StructureMasanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera. 402-407 [doi]
- Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and CircuitsSaibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy. 410-415 [doi]
- Design For Degradation : CAD Tools for Managing Transistor Degradation MechanismsAnanth Somayaji Goda, Gautam Kapila. 416-420 [doi]
- A Practical Transistor-Level Dual Threshold Voltage Assignment MethodologyPuneet Gupta, Andrew B. Kahng, Puneet Sharma. 421-426 [doi]
- Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in EnvironmentOleg Semenov, H. Sarbishaei, Manoj Sachdev. 427-432 [doi]
- Built-In-Self-Testing Techniques for Programmable Capacitor ArraysAmit Laknaur, Haibo Wang. 434-439 [doi]
- A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADCDaniela De Venuto, Grazia Marchione, Leonardo Reyneri. 440-447 [doi]
- A Built-In Self-Test Scheme for Differential Ring OscillatorsLampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni. 448-452 [doi]
- Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan PartitioningSwarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy. 453-458 [doi]
- Nanoelectronics: Evolution or Revolution?Mark S. Lundstrom, Philip Wong, Kazuo Yano. 459 [doi]
- Plenary Session 2PLech Józwiak, Kaustav Banerjee. 461 [doi]
- Quality and EDAAki Fujimura. 463-463 [doi]
- IP Quality: A New Model that Faces Methodology and Management ChallengesKurt A. Wolf. 465-465 [doi]
- SoC Engineering Trends as Impacted by New Applications and System Level RequirementsBernard Candaele. 467-467 [doi]
- ASLIC: A Low Power CMOS Analog Circuit Design AutomationJihyun Lee, Yong-Bin Kim. 470-475 [doi]
- Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC ModelsYuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk. 476-481 [doi]
- A Mask Reuse Methodology for Reducing System-on-a-Chip CostSubhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin. 482-487 [doi]
- Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFETSaibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy. 490-495 [doi]
- Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and TemperatureXiaojun Li, Joerg D. Walter, Joseph B. Bernstein. 496-502 [doi]
- Predicting and Designing for the Impact of Process Variations and Mismatch on the Trim Range and Yield of Bandgap ReferencesVishal Gupta, Gabriel A. Rincón-Mora. 503-508 [doi]
- Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOSNorman G. Gunther, Emad Hamadeh, Darrell Niemann, Iliya Pesic, Mahmud Rahman. 510-515 [doi]
- Modeling Within-Die Spatial Correlation Effects for Process-Design Co-OptimizationPaul Friedberg, Yu Cao, Jason Cain, Ruth Wang, Jan M. Rabaey, Costas J. Spanos. 516-521 [doi]
- Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process VariationsVishak Venkatraman, Wayne Burleson. 522-527 [doi]
- A Comprehensive Methodology for Noise Characterization of ASIC Cell LibrariesSreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan. 530-535 [doi]
- Sensitivity-Based Gate Delay Propagation in Static Timing AnalysisShahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin. 536-541 [doi]
- Fast Decap Allocation Algorithm For Robust On-Chip Power DeliveryZhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong. 542-547 [doi]
- Clock trees: differential or single ended?Deepak C. Sekar. 548-553 [doi]
- Exploring the Challenges in Creating a High-Quality Mainstream Design Solution for System-in-Package (SiP) DesignBill McCaffrey. 556-561 [doi]
- Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP)Anru Wang, Wayne Wei-Ming Dai. 562-566 [doi]
- This paper presents a cost-effective area-IO DRAM A CAD Tool and AlgorithmsChung-Seok (Andy) Seo, Abhijit Chatterjee, Nan M. Jokerst. 567-572 [doi]
- Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave ApproachMeigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen. 573-578 [doi]
- Current Calculation on VLSI Signal InterconnectsMuzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong. 580-585 [doi]
- Dummy Filling Methods for Reducing Interconnect Capacitance and Number of FillsAtsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda. 586-591 [doi]
- Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect CircuitsVinita V. Deodhar, Jeffrey A. Davis. 592-597 [doi]
- Interconnect Delay and Slew Metrics Using the First Three MomentsJiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye. 598-602 [doi]
- Passive Hierarchical Model Order Reduction and Realization of RLCM CircuitsPu Liu, Zhenyu Qi, Sheldon X.-D. Tan. 603-608 [doi]
- Reticle Floorplanning and Wafer Dicing for Multiple Project WafersMeng-Chiou Wu, Rung-Bin Lin. 610-615 [doi]
- Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC DesignJingyu Xu, Xianlong Hong, Tong Jing, Yang Yang. 616-621 [doi]
- Wire Planning with Bounded Over-the-Block WiresHua Xiang, I-Min Liu, Martin D. F. Wong. 622-627 [doi]
- Floorplanning with Consideration of White Space Resource Distribution for Repeater PlanningSong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng. 628-633 [doi]
- Thermal-Aware Floorplanning Using Genetic AlgorithmsWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin. 634-639 [doi]
- Joint Equalization and Coding for On-Chip Bus CommunicationSrinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan. 642-647 [doi]
- A More Effective C::EFF::Sani R. Nassif, Zhuo Li. 648-653 [doi]
- An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing AnalysisChung-Kuan Tsai, Malgorzata Marek-Sadowska. 654-661 [doi]
- Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder FilterAli Zahabi, Omid Shoaei, Yarallah Koolivand. 662-667 [doi]
- Design Considerations for Low-Power Ultra Wideband ReceiversPayam Heydari. 668-673 [doi]
- A New Method for Design of Robust Digital CircuitsDinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd. 676-681 [doi]
- Staggered Twisted-Bundle Interconnect for Crosstalk and Delay ReductionHao Yu, Lei He. 682-687 [doi]
- Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric VariationsWei Ling, Yvon Savaria. 688-693 [doi]
- Impact of Interconnect Process Variations on Memory Performance and DesignAndres Teene, Bob Davis, R. Castagnetti, J. Brown, S. Ramesh. 694-699 [doi]