D. Michael Miller - researchr alias

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Viewing Publication 1 - 91 from 91

2021

Descending Order Transformation-based Synthesis of MVL Reversible CircuitsD. Michael Miller, Gerhard W. Dueck. ismvl 2021: 107-112 [doi]

Function translations and search-based transformation for MVL reversible circuit synthesisD. Michael Miller, Gerhard W. Dueck. SCP, 212:102704, 2021. [doi]

2020

Search-Based Transformation Synthesis for 3-Valued Reversible CircuitsD. Michael Miller, Gerhard W. Dueck. RC 2020: 218-236 [doi]

A Spectral Algorithm for 3-valued Function Equivalence ClassificationD. Michael Miller, Mathias Soeken. mvl, 34(3-4):203-221, 2020. [doi]

Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal TransformsKaitlin N. Smith, Mitchell A. Thornton, D. Michael Miller. ismvl 2020: 259-264 [doi]

2019

A Hybrid Method for Spectral Translation Equivalent Boolean FunctionsMathias Soeken, Eleonora Testa, D. Michael Miller. pacrim 2019: 1-6 [doi]

2018

A Spectral Algorithm for Ternary Function ClassificationD. Michael Miller, Mathias Soeken. ismvl 2018: 198-203 [doi]

2016

QMDDs: Efficient Quantum Function Representation and ManipulationPhilipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler. tcad, 35(1):86-99, 2016. [doi]

An extension of transformation-based reversible and quantum circuit synthesisMathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller. iscas 2016: 2290-2293 [doi]

A Fast Symbolic Transformation Based Algorithm for Reversible Logic SynthesisMathias Soeken, Gerhard W. Dueck, D. Michael Miller. RC 2016: 307-321 [doi]

Embedding of Large Boolean Functions for Reversible LogicMathias Soeken, Robert Wille, Oliver Keszocze, D. Michael Miller, Rolf Drechsler. jetc, 12(4):41, 2016. [doi]

Using SPIN to Check Simulink Stateflow ModelsChikatoshi Yamada, D. Michael Miller. ijndc, 4(1):65-74, 2016. [doi]

Using SPIN to Check Simulink Stateflow ModelsChikatoshi Yamada, D. Michael Miller. ijndc, 4(3):193-202, 2016. [doi]

2015

Using QMDD in Numerical Methods for Solving Linear Differential Equations via Walsh FunctionsRadomir S. Stankovic, D. Michael Miller. ismvl 2015: 182-188 [doi]

Using SPIN to check Simulink Stateflow modelsChikatoshi Yamada, D. Michael Miller. ACISicis 2015: 161-166 [doi]

Using SPIN to Check Nondeterministic Simulink Stateflow ModelsChikatoshi Yamada, D. Michael Miller. ismvl 2015: 145-151 [doi]

2014

Reversible, Information-Preserving Logic and Its ApplicationMartin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller. mvl, 23(3-4):379-406, 2014.

Mapping NCV Circuits to Optimized Clifford+T CircuitsD. Michael Miller, Mathias Soeken, Rolf Drechsler. RC 2014: 163-175 [doi]

Trading off circuit lines and gate costs in the synthesis of reversible logicRobert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler. integration, 47(2):284-294, 2014. [doi]

2012

High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation?Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski. mvl, 20(1-2):89-120, 2012. [doi]

Recent Developments on Mapping Reversible Circuits to Quantum Gate LibrariesD. Michael Miller, Zahra Sasanian. ised 2012: 17-22 [doi]

Reducing Reversible Circuit Cost by Adding LinesD. Michael Miller, Robert Wille, Rolf Drechsler. mvl, 19(1-3):185-201, 2012. [doi]

Mapping a Multiple-control Toffoli Gate Cascade to an Elementary Quantum Gate CircuitZahra Sasanian, D. Michael Miller. mvl, 18(1):83-98, 2012. [doi]

Reversible and Quantum Circuit Optimization: A Functional ApproachZahra Sasanian, D. Michael Miller. RC 2013: 112-124 [doi]

Realizing reversible circuits using a new class of quantum gatesZahra Sasanian, Robert Wille, D. Michael Miller. dac 2012: 36-41 [doi]

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate CircuitsMathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler. ismvl 2012: 173-178 [doi]

Equivalence Checking of Reversible CircuitsRobert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler. mvl, 19(4):361-378, 2012. [doi]

Synthesis of Semi-Classical Quantum CircuitsShigeru Yamashita, Shin-ichi Minato, D. Michael Miller. mvl, 18(1):99-114, 2012. [doi]

2011

Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat DissipationMartin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller. ismvl 2011: 131-138 [doi]

Elementary Quantum Gate Realizations for Multiple-Control Toffoli GatesD. Michael Miller, Robert Wille, Zahra Sasanian. ismvl 2011: 288-293 [doi]

Transforming MCT Circuits to NCVW CircuitsZahra Sasanian, D. Michael Miller. RC 2012: 77-88 [doi]

2010

Reducing Reversible Circuit Cost by Adding LinesD. Michael Miller, Robert Wille, Rolf Drechsler. ismvl 2010: 217-222 [doi]

Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian GroupsStanislav Stankovic, Jaakko Astola, D. Michael Miller, Radomir S. Stankovic. ismvl 2010: 307-312 [doi]

2009

2008

On the Data Structure Metrics of Quantum Multiple-Valued Decision DiagramsDavid Y. Feinstein, Mitchell A. Thornton, D. Michael Miller. ismvl 2008: 138-143 [doi]

Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic CircuitsDavid Y. Feinstein, Mitchell A. Thornton, D. Michael Miller. date 2008: 1378-1381 [doi]

Quantum Circuit Simplification and Level CompactionDmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne. tcad, 27(3):436-444, 2008. [doi]

Multiple Valued Logic - Concepts and RepresentationsD. Michael Miller, Mitchell Aaron Thornton. Volume 12 of Synthesis lectures on digital circuits and systems, Morgan & Claypool Publishers, 2008. [doi]

Quantum Logic Implementation of Unary Arithmetic OperationsMitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller. ismvl 2008: 202-207 [doi]

An efficient verification of quantum circuits under a practical restrictionShigeru Yamashita, Shin-ichi Minato, D. Michael Miller. IEEEcit 2008: 873-879 [doi]

DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical RestrictionShigeru Yamashita, Shin-ichi Minato, D. Michael Miller. ieicet, 91-A(12):3793-3802, 2008. [doi]

2007

Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuitsDmitri Maslov, D. Michael Miller. iet-cdt, 1(2):98-104, 2007. [doi]

Techniques for the synthesis of reversible Toffoli networksDmitri Maslov, Gerhard W. Dueck, D. Michael Miller. todaes, 12(4):42, 2007. [doi]

Multiple Valued Logic: Concepts and RepresentationsD. Michael Miller, Mitchell A. Thornton. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2007. [doi]

Variable Reordering and Sifting for QMDDD. Michael Miller, David Y. Feinstein, Mitchell A. Thornton. ismvl 2007: 10 [doi]

QMDD Minimization Using Sifting for Variable ReorderingD. Michael Miller, David Y. Feinstein, Mitchell A. Thornton. mvl, 13(4-6):537-552, 2007. [doi]

2006

QMDD: A Decision Diagram Structure for Reversible and Quantum CircuitsD. Michael Miller, Mitchell A. Thornton. ismvl 2006: 30 [doi]

A Decision Diagram Package for Reversible and Quantum Circuit SimulationD. Michael Miller, Mitchell A. Thornton, David Goodman. cec 2006: 2428-2435 [doi]

Synthesis of Quantum Multiple-Valued CircuitsD. Michael Miller, Dmitri Maslov, Gerhard W. Dueck. mvl, 12(5-6):431-450, 2006. [doi]

2005

Toffoli network synthesis with templatesDmitri Maslov, Gerhard W. Dueck, D. Michael Miller. tcad, 24(6):807-817, 2005. [doi]

Synthesis of Fredkin-Toffoli reversible networksDmitri Maslov, Gerhard W. Dueck, D. Michael Miller. tvlsi, 13(6):765-769, 2005. [doi]

Quantum Circuit Simplification Using TemplatesDmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck. date 2005: 1208-1213 [doi]

2004

A Synthesis Method for MVL Reversible LogiD. Michael Miller, Gerhard W. Dueck, Dmitri Maslov. ismvl 2004: 74-80 [doi]

Computation of Discrete Function Chrestenson Spectrum Using Cayley Color GraphsMitchell A. Thornton, D. Michael Miller. mvl, 10(2):189-202, 2004. [doi]

2003

2002

2001

Spectral techniques in VLSI CADMitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller. Kluwer, 2001.

2000

TOP: An Algorithm for Three-Level Optimization of PLDsElena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio. date 2000: 751 [doi]

Logic Synthesis of Controllers for B-Ternary Asynchronous SystemsYasunori Nagata, D. Michael Miller, Masao Mukaidono. ismvl 2000: 402 [doi]

1999

B-ternary Logic Based Asynchronous MicropipelineYasunori Nagata, D. Michael Miller, Masao Mukaidono. ismvl 1999: 214-219 [doi]

1998

An improved method for computing a generalized spectral coefficientD. Michael Miller. tcad, 17(3):233-238, 1998. [doi]

Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAsYasunori Nagata, D. Michael Miller, Masao Mukaidono. ismvl 1998: 38 [doi]

1996

Multiple-Valued Decision Diagrams with Symmetric Variable NodesD. Michael Miller, Noriaki Muranaka. ismvl 1996: 242-247 [doi]

A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETsNoriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller. ismvl 1996: 92-97 [doi]

Notes on Complexity of the lookup-table minimization problem for FPGA technology mapping Shujian Zhang, D. Michael Miller, Jon C. Muzio. tcad, 15(12):1588-1590, 1996. [doi]

1995

Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faultsShujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller. et, 7(3):209-221, 1995. [doi]

1994

Spectral Transformation of Multiple-Valued Decision DiagramsD. Michael Miller. ismvl 1994: 89-96

Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type FaultsShujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller. iscas 1994: 69-72

1993

Multiple-Valued Logic Design ToolsD. Michael Miller. ismvl 1993: 2-11

Decimal Addition and Subtraction Units Using the ::::p::::-Valued Decimal Signed-Digit Number RepresentationNoriaki Muranaka, Shigeru Imanishi, D. Michael Miller. ismvl 1993: 228-233

1992

Autocorrelation Techniques for Multi-Bit Decoder PLAsR. Tomczuk, D. Michael Miller. ismvl 1992: 355-364

BIST Generators for Sequential FaultsShujian Zhang, Rod Byrne, D. Michael Miller. iccd 1992: 260-263

1990

RCM-MVL: A Recursive Consensus MVL Minimization AlgorithmGerhard W. Dueck, D. Michael Miller. ismvl 1990: 136-143

Estimating aliasing in CA and LFSR based signature registersD. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod. iccd 1990: 157-160 [doi]

The analysis of one-dimensional linear cellular automata and their aliasing propertiesMicaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller. tcad, 9(7):767-778, 1990. [doi]

1984

Spectral Fault Signatures for Single Stuck-At Faults in Combinational NetworksD. Michael Miller, Jon C. Muzio. TC, 33(8):765-769, 1984.

1983

Spectral Fault Signatures for Internally Unate Combinational NetworksD. Michael Miller, Jon C. Muzio. TC, 32(11):1058-1062, 1983.

1980

A class of two-place three-valued unary generatorsD. Michael Miller, Jon C. Muzio. ndjfl, 21(1):148-154, 1980. [doi]

1976

A ternary universal decision elementD. Michael Miller, Jon C. Muzio. ndjfl, 17(4):632-637, 1976. [doi]

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