Abstract is missing.
- Welcome!Laura Chizuko Fujino. 1 [doi]
- ReflectionsLaura Chizuko Fujino. 4 [doi]
- Session 1 overview: Plenary sessionAnantha Chandrakasan, Bram Nauta. 6-7 [doi]
- "Architecting the future through heterogeneous computing"Lisa T. Su. 8-11 [doi]
- "Smart life solutions" from home to cityYoshiyuki Miyabe. 12-17 [doi]
- Continuing to shrink: Next-generation lithography - Progress and prospectsMartin van den Brink. 20-25 [doi]
- Session 2 overview: Ultra-high-speed transceivers and equalizersKen Chang, Hisakatsu Yamaguchi. 26-27 [doi]
- The evolution of technologyCarver Mead. 26 [doi]
- A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOSSamir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada. 28-29 [doi]
- A 66Gb/s 46mW 3-tap decision-feedback equalizer in 65nm CMOSYue Lu, Elad Alon. 30-31 [doi]
- A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOSBharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Huang, Afshin Momtaz, Jun Cao. 32-33 [doi]
- A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOSBo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz. 34-35 [doi]
- 32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOSYoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura. 36-37 [doi]
- A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOSAmr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang. 38-39 [doi]
- 32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFEYuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura. 40-41 [doi]
- A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOSKwangMo Jung, Amir Amirkhany, Kambiz Kaviani. 42-43 [doi]
- Session 3 overview: ProcessorsSe-Hyun Yang, Eric Fluhr. 44-45 [doi]
- 5.5GHz system z microprocessor and multi-chip moduleJames D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Shum, Donald W. Plass, Charles F. Webb. 46-47 [doi]
- 3.6GHz 16-core SPARC SoC processor in 28nmJason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios Konstadinidis, Lance Kwong, Robert Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King Yen. 48-49 [doi]
- Processor with side-channel attack resistanceJen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee. 50-51 [doi]
- Jaguar: A next-generation low-power x86-64 coreTeja Singh, Joshua Bell, Shane Southard. 52-53 [doi]
- Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processorWeiwu Hu, Yifu Zhang, Liang Yang, Bao-Xia Fan, Yunji Chen, Shi-Qiang Zhong, Huandong Wang, Zichu Qi, Pengyu Wang, Xiang Gao, Xu Yang, Bin Xiao, Hongsheng Wang, Zongren Yang, Liqiong Yang, Shuai Chen. 54-55 [doi]
- A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution arrayPeng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu. 56-57 [doi]
- Bandwidth and power management of glueless 8-socket SPARC T5 systemVenkatram Krishnaswamy, Dawei Huang, Sebastian Turullols, Jinuk Luke Shin. 58-59 [doi]
- th generation 16-core SPARC64 processor for mission-critical UNIX serverRyuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada. 60-61 [doi]
- Session 4 overview: Harvesting & wireless powerJae-Youl Lee, Saska Lindfors. 62-63 [doi]
- A resonant regulating rectifier (3R) operating at 6.78 MHz for a 6W wireless charger with 86% efficiencyJun-Han Choi, Sung-Ku Yeo, Chang-Byong Park, Seho Park, Jeong Seok Lee, Gyu-Hyeong Cho. 64-65 [doi]
- A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devicesYan Lu, Xing Li, Wing-Hung Ki, Chi-Ying Tsui, C. Patrick Yue. 66-67 [doi]
- A 400nW single-inductor dual-input-tri-output DC-DC buck-boost converter with maximum power point tracking for indoor photovoltaic energy harvestingKin Wai Roy Chew, Zhuochao Sun, Howard Tang, Liter Siek. 68-69 [doi]
- An adaptive load-line tuning IC for photovoltaic module integrated mobile device with 470µs transient time, over 99% steady-state accuracy and 94% power conversion efficiencyWen-Chuen Liu, Yi-Hsiang Wang, Tai-Haur Kuo. 70-71 [doi]
- A 3.4mW photovoltaic energy-harvesting charger with integrated maximum power point tracking and battery managementTsung-Heng Tsai, Kai Chen. 72-73 [doi]
- A self-biased 5-to-60V input voltage and 25-to-1600µW integrated DC-DC buck converter with fully analog MPPT algorithm reaching up to 88% end-to-end efficiencyStefano Stanzione, Chris van Liempd, Rob van Schaijk, Yasuyuki Naito, Refet Firat Yazicioglu, Chris Van Hoof. 74-75 [doi]
- A 1µW-to-1mW energy-aware interface IC for piezoelectric harvesting with 40nA quiescent current and zero-bias active rectifiersChris van Liempd, Stefano Stanzione, Younis Allasasmeh, Chris Van Hoof. 76-77 [doi]
- A single-inductor 0.35µm CMOS energy-investing piezoelectric harvesterDongwon Kwon, Gabriel A. Rincón-Mora. 78-79 [doi]
- Session 5 overview: RF techniquesMike Keaveney, Joe Golat. 80-81 [doi]
- SAW-less analog front-end receivers for TDD and FDDIvan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello. 82-83 [doi]
- Simultaneous spatial and frequency-domain filtering at the antenna inputs achieving up to +10dBm out-of-band/beam P1dBAmir Ghaffari, Eric A. M. Klumperink, Frank E. van Vliet, Bram Nauta. 84-85 [doi]
- A phase-noise and spur filtering technique using reciprocal-mixing cancellationMohyee Mikhemar, David Murphy, Ahmad Mirzaei, Hooman Darabi. 86-87 [doi]
- A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifierMaryam Fathi, David K. Su, Bruce A. Wooley. 88-89 [doi]
- A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applicationsKohei Onizuka, Shigehito Saigusa, Shoji Otaka. 90-91 [doi]
- A new TX leakage-suppression technique for an RFID receiver using a dead-zone amplifierSang-Sung Lee, Jaeheon Lee, In-Young Lee, Sang-Gug Lee, Jinho Ko. 92-93 [doi]
- th-order complex analog memory polynomial predistorter for wireless infrastructure RF amplifiersFrederic Roger. 94-95 [doi]
- Session 6 overview: Emerging medical and sensor technologies technology directions subcommitteeDavid Ruffieux, Yogesh K. Ramadass. 96-97 [doi]
- An 87mA·min iontophoresis controller IC with dual-mode impedance sensor for patch-type transdermal drug delivery systemKiseok Song, Unsoo Ha, Jaehyuk Lee, Kyeongryeol Bong, Hoi-Jun Yoo. 98-99 [doi]
- A 1.83µJ/classification nonlinear support-vector-machine-based patient-specific seizure classification SoCMuhammad Awais Bin Altaf, Judyta Tillak, Yonatan Kifle, Jerald Yoo. 100-101 [doi]
- Through-silicon-via-based double-side integrated microsystem for neural sensing applicationsChih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong. 102-103 [doi]
- 1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand controlHiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai. 104-105 [doi]
- A 4b ADC manufactured in a fully-printed organic complementary technology including resistorsSahel Abdinia, Mohamed Benwadih, Romain Coppard, Stéphanie Jacob, Giorgio Maiellaro, Giuseppe Palmisano, Mariantonietta Rizzo, Antonino Scuderi, Francesca Tramontana, Arthur H. M. van Roermund, Eugenio Cantatore. 106-107 [doi]
- An organic VCO-based ADC for quasi-static signals achieving 1LSB INL at 6b resolutionDaniele Raiteri, Pieter van Lieshout, Arthur H. M. van Roermund, Eugenio Cantatore. 108-109 [doi]
- A 1024×8 700ps time-gated SPAD line sensor for laser raman spectroscopy and LIBS in space and rover-based planetary explorationYuki Maruyama, Jordana Blacksberg, Edoardo Charbon. 110-111 [doi]
- Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETsMax M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra. 112-113 [doi]
- Session 7 overview: Optical transceivers and silicon photonicsIchiro Fujimori, Masafumi Nogawa. 114-115 [doi]
- A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penaltyGeorgios Kalogerakis, Tim Moran, Thelinh Nguyen, Gilles Denoyer. 116-117 [doi]
- A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnectsTakashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka. 118-119 [doi]
- 100Gb/s ethernet chipsets in 65nm CMOS technologyJhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee. 120-121 [doi]
- A blind baud-rate ADC-based CDRClifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura. 122-123 [doi]
- A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiverCheng Li, Rui Bai, Ayman Shafik, Ehsan Zhian Tabasy, Geng Tang, Chao Ma, Chin-Hui Chen, Zhen Peng, Marco Fiorentino, Patrick Chiang, Samuel Palermo. 124-125 [doi]
- A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOIBenjamin Moss, Chen Sun, Michael Georgas, Jeff Shainline, Jason Orcutt, Jonathan Leu, Mark Wade, Yu-Hsin Chen, Kareem Nammari, Xiaoxi Wang, Hanqing Li, Rajeev J. Ram, Milos Popovic, Vladimir Stojanovic. 126-127 [doi]
- A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13µm CMOSXiaotie Wu, Bipin Dama, Prakash Gothoskar, Peter Metz, Kal Shastri, Sanjay Sunder, Jan Van der Spiegel, Yifan Wang, Mark Webster, Will Wilson. 128-129 [doi]
- Optical receivers using DFE-IIR equalizationJonathan Proesel, Alexander Rylyakov, Clint Schow. 130-131 [doi]
- A 10Gb/s 6Vpp differential modulator driver in 0.18µm SiGe-BiCMOSYi Zhao, Leonardo Vera, John R. Long, David L. Harame. 132-133 [doi]
- Session 8 overview: Millimeter-wave techniquesUllrich R. Pfeiffer, Gabriel M. Rebeiz. 134-135 [doi]
- A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOSZheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, Payam Heydari. 136-137 [doi]
- A 260GHz broadband source with 1.1mW continuous-wave radiated power and EIRP of 15.7dBm in 65nm CMOSRuonan Han, Ehsan Afshari. 138-139 [doi]
- A 260GHz amplifier with 9.2dB gain and -3.9dBm saturated power in 65nm CMOSOmeed Momeni. 140-141 [doi]
- A 0.7W fully integrated 42GHz power amplifier with 10% PAE in 0.13µm SiGe BiCMOSWei Tai, L. Richard Carley, David S. Ricketts. 142-143 [doi]
- A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude controlFrancis Caster, Leland Gilreath, Shiji Pan, Zheng Wang, Filippo Capolino, Payam Heydari. 144-145 [doi]
- A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOSPang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee. 146-147 [doi]
- A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearizationYaoming Sun, Miroslav Marinkovic, Gunter Fischer, Wolfgang Winkler, Wojciech Debski, Stefan Beer, Thomas Zwick, Mekdes G. Girma, Juergen Hasch, Christoph Scheytt. 148-149 [doi]
- A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of -193.5dBc/HzQiyang Wu, Tony Quach, Aji Mattamana, Salma Elabd, Steven R. Dooley, Jamin J. McCue, Pompei L. Orlando, Gregory L. Creech, Waleed Khalil. 150-151 [doi]
- Session 9 overview: Mobile application processors and media acceleratorsMichael Polley, Yongha Park. 152-153 [doi]
- 28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processorYoungmin Shin, Ken Shin, Prashant Kenkare, Rajesh Kashyap, Hoi-Jin Lee, Dongjoo Seo, Brian Millar, Yohan Kwon, Ravi Iyengar, Min-Su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, WooKyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae Cheol Son, Seung Ho Hwang. 154-155 [doi]
- A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processorMasaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori. 156-157 [doi]
- A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOSTay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang. 158-159 [doi]
- 72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia applicationYongha Park, Chang-Hyo Yu, Kilwhan Lee, Hyunsuk Kim, Youngeun Park, Chun-Ho Kim, Yunseok Choi, Jinhong Oh, Changhoon Oh, Gurnrack Moon, Sangduk Kim, HoRang Jang, Jin-Aeon Lee, Chinhyun Kim, Sungho Park. 160-161 [doi]
- A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applicationsChao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha Chandrakasan. 162-163 [doi]
- Reconfigurable processor for energy-scalable computational photographyRahul Rithe, Priyanka Raina, Nathan Ickes, Srikanth V. Tenneti, Anantha P. Chandrakasan. 164-165 [doi]
- A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOSDongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David Blaauw, Dennis Sylvester. 166-167 [doi]
- A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognitionJunyoung Park, Injoon Hong, Gyeonghoon Kim, Youchang Kim, KyuHo Lee, Seongwook Park, Kyeongryeol Bong, Hoi-Jun Yoo. 168-169 [doi]
- Session 10 overview: Analog techniquesJafar Savoj, Chris Mangelsdorf. 170-171 [doi]
- A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker toleranceMilad Darvishi, Ronan A. R. van der Zee, Bram Nauta. 172-173 [doi]
- A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOSMassoud Tohidian, Iman Madadi, Robert Bogdan Staszewski. 174-175 [doi]
- A multi-path chopper-stabilized capacitively coupled operational amplifier with 20V-input-common-mode range and 3µV offsetQinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa. 176-177 [doi]
- 2 14nV/√Hz chopper instrumentation amplifier with automatic differential-pair matchingIppei Akita, Makoto Ishida. 178-179 [doi]
- A 4Ω 2.3W class-D audio amplifier with embedded DC-DC boost converter, current-sensing ADC and DSP for adaptive speaker protectionMarco Berkhout, Lutsen Dooper, Benno Krabbenborg, John Somberg. 180-181 [doi]
- A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent currentJianlong Chen, Sasi Kumar Arunachalam, Todd Brooks, Iuri Mehr, Felix Cheung, Hariprasath Venkatram. 182-183 [doi]
- A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stabilityArun Paidimarri, Danielle Griffith, Alice Wang, Anantha P. Chandrakasan, Gangadhar Burra. 184-185 [doi]
- A 63, 000 Q-factor relaxation oscillator with switched-capacitor integrated error feedbackYing Cao, Paul Leroux, Wouter De Cock, Michiel Steyaert. 186-187 [doi]
- A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platformsDong-Woo Jee, Dennis Sylvester, David Blaauw, Jae-Yoon Sim. 188-189 [doi]
- Session 11 overview: Emerging memory and wireless technologyFu-Lung Hsueh, Shinichiro Mutoh. 190-191 [doi]
- A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systemsMasood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan. 192-193 [doi]
- Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gatingMasanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu. 194-195 [doi]
- A versatile timing microsystem based on wafer-level packaged XTAL/BAW resonators with sub-µW RTC mode and programmable HF clocksDavid Ruffieux, Nicola Scolari, Frédéric Giroud, Thanh-Chau Le, Silvio Dalla Piazza, Felix Staub, Kai Zoschke, Charles Alix Manier, Hermann Oppermann, James Dekker, Tommi Suni, Giorgio Allegato. 196-197 [doi]
- Microwave amplification with nanomechanical resonatorsFrancesco Massel, Tero T. Heikkila, Juha-Matti Pirkkalainen, Sung-Un Cho, Heini Saloniemi, Pertti J. Hakonen, Mika A. Sillanpaa. 198-199 [doi]
- A 0.15mm-thick non-contact connector for MIPI using vertical directional couplerWataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda. 200-201 [doi]
- 1.2Gb/s 3.9pJ/b mono-phase pulse-modulation inductive-coupling transceiver for mm-range board-to-board communicationHyunwoo Cho, Unsoo Ha, Taehwan Roh, Dongchurl Kim, Jeahyuck Lee, Yunje Oh, Hoi-Jun Yoo. 202-203 [doi]
- Retrodirective transponder array with universal on-sheet reference for wireless mobile sensor networks without battery or oscillatorHaruki Fukuda, Takahide Terada, Tadahiro Kuroda. 204-205 [doi]
- A scalable 2.9mW 1Mb/s eTextiles body area network transceiver with remotely powered sensors and bi-directional data communicationNachiket V. Desai, Jerald Yoo, Anantha P. Chandrakasan. 206-207 [doi]
- Session 12 overview: Non-volatile memory solutionsJin-Man Han, Daniele Vimercati. 208-209 [doi]
- 2 2-layer 32Gb ReRAM memory device in 24nm technologyTz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Sravanti Addepalli, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Saurabh Joshi 0002, Achal Kathuria, Vincent Lai, Deep Masiwal, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Ronald Yin, Liping Peng, Jang Yong Kang, Sharon Huynh, Huijuan Wang, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Takahiko Hara, Hirofumi Inoue, Luca Fasoli, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader. 210-211 [doi]
- 40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for dataTakashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi. 212-213 [doi]
- A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda. 214-215 [doi]
- Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOSMihail Jefremow, Thomas Kern, Wolf Allers, Christian Peters, Jan Otterstedt, Othmane Bahlous, Karl Hofmann, Robert Allinger, Stephan Kassenetter, Doris Schmitt-Landsiedel. 216-217 [doi]
- A 128Gb 3b/cell NAND flash design using 20nm planar-cell technologyG. Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, A. D'Alessandro, L. De Santis, D. Di Cicco, W. Di Francesco, M. L. Gallese, G. Gallo, M. Incarnati, C. Lattaro, A. Macerola, G. G. Marotta, V. Moschiano, D. Orlandi, F. Paolini, S. Perugini, L. Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, G. Santin, E. Sirizotti, A. Smaniotto, U. Siciliani, M. Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, M. Helm, R. Ghodsi. 218-219 [doi]
- Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAMAkifumi Kawahara, Ken Kawai, Yuuichirou Ikeda, Yoshikazu Katoh, Ryotaro Azuma, Yuhei Yoshimoto, Kouhei Tanabe, Zhiqiang Wei, Takeki Ninomiya, Koji Katayama, Ryutaro Yasuhara, Shunsaku Muraoka, Atsushi Himeno, Naoki Yoshikawa, Hideaki Murase, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono. 220-221 [doi]
- A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engineKin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang. 222-223 [doi]
- Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technologyHung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Jonathan Chang, Sreedhar Natarajan, Luan C. Tran. 224-225 [doi]
- Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applicationsShuhei Tanakamaru, Masafumi Doi, Ken Takeuchi. 226-227 [doi]
- Session 13 overview: High-performance wirelessBrian A. Floyd, Kenichi Okada. 228-229 [doi]
- A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applicationsTakayuki Tsukizawa, Naganori Shirakata, Tadashi Morita, Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka, Yoshinori Shirakawa, Naoya Yosoku, Akira Yamamoto, Ryosuke Shiozaki, Noriaki Saito. 230-231 [doi]
- A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combiningJiashu Chen, Lu Ye, Diane Titz, Fred Gianesello, Romain Pilard, Andreia Cathelin, Fabien Ferrero, Cyril Luxey, Ali M. Niknejad. 232-233 [doi]
- A 50mW-TX 65mW-RX 60GHz 4-element phased-array transceiver with integrated antennas in 65nm CMOSLingkai Kong, Dongjin Seo, Elad Alon. 234-235 [doi]
- A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communicationVojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti, Steven Brebels, Wim Van Thillo, Kristof Vaesen, Bertrand Parvais, Vadim Issakov, Mike Libois, Michiaki Matsuo, John R. Long, Charlotte Soens, Piet Wambacq. 236-237 [doi]
- A mixed-signal 32-coefficient RX-FFE 100-coefficient DFE for an 8Gb/s 60GHz receiver in 65nm LP CMOSChintan Thakkar, Nathan Narevsky, Christopher D. Hull, Elad Alon. 238-239 [doi]
- A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOSMichele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani. 240-241 [doi]
- A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOSChang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ta-Shun Chu. 242-243 [doi]
- A digital single-wire multiswitch (DSWM) channel-stacking IC in 45nm CMOS for satellite outdoor unitsWeinan Gao, Bill Huff, Kendal Hess, Didier Coulibaly, Costantino Pala, Jiang Cao, Jaspreet Bhatia, Mikko Waltari, Lior Levin, Cyrille Cathelin, Thierry Nouvet, Nitin Nidhi, Rahul M. Kodkani, Ryuji Maeda, Damian Costa, Jason McFee, Reza Moazzam, Herve Vincent, Philippe Durieux. 244-245 [doi]
- Session 14 overview: Digital PLLs and building blocksAnthony Hill, Atsuki Inoue. 246-247 [doi]
- 2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuitsWei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. 248-249 [doi]
- 2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning rangeWooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog Kyoon Jeong. 250-251 [doi]
- An all-digital PLL using random modulation for SSC generation in 65nm CMOSNicola Da Dalt, Peter Pridnig, Werner Grollitsch. 252-253 [doi]
- 2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converterTae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park. 254-255 [doi]
- A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on timeTejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu. 256-257 [doi]
- 3D clock distribution using vertically/horizontally-coupled resonatorsYasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda. 258-259 [doi]
- All-digital hybrid temperature sensor network for dense thermal monitoringSeungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim. 260-261 [doi]
- A 95fJ/b current-mode transceiver for 10mm on-chip interconnectSeon-Kyoo Lee, Seung Hun Lee, Dennis Sylvester, David Blaauw, Jae-Yoon Sim. 262-263 [doi]
- Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOSSeongjong Kim, Inyong Kwon, David Fick, MyungBo Kim, Yen-Po Chen, Dennis Sylvester. 264-265 [doi]
- Session 15 overview: Data converter techniquesMichael Perrott, Geert Van der Plas. 266-267 [doi]
- A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizerYun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu. 268-269 [doi]
- A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise ReductionPieter Harpe, Eugenio Cantatore, Arthur H. M. van Roermund. 270-271 [doi]
- A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noiseTakashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho. 272-273 [doi]
- A 1V 14b self-timed zero-crossing-based incremental ΔΣ ADCChao Chen, Zhichao Tan, Michiel A. P. Pertijs. 274-275 [doi]
- A 6.3µW 20b incremental zoom-ADC with 6ppm INL and 1µV offsetYoungcheol Chae, Kamran Souri, Kofi A. A. Makinwa. 276-277 [doi]
- A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stabilityRoddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee. 278-279 [doi]
- A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOSChang-Yuan Liou, Chih-Cheng Hsieh. 280-281 [doi]
- Adaptive cancellation of gain and nonlinearity errors in pipelined ADCsYuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song. 282-283 [doi]
- Session 16 overview: Biomedical circuits & systemsFirat Yazicioglu, Taechan Kim. 284-285 [doi]
- A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure controlWei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu. 286-287 [doi]
- An implantable 455-active-electrode 52-channel CMOS neural probeCarolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic, Robert Puers, Refet Firat Yazicioglu, Georges G. E. Gielen. 288-289 [doi]
- A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOSDong Han, Yuanjin Zheng, Ramamoorthy Rajkumar, Gavin Dawe, Minkyu Je. 290-291 [doi]
- 24-channel dual-band wireless neural recorder with activity-dependent power consumptionSrinjoy Mitra, Jan Putzeys, Francesco Paolo Battaglia, Carolina Mora Lopez, Marleen Welkenhuysen, Cyriel M. A. Pennartz, Chris Van Hoof, Refet Firat Yazicioglu. 292-293 [doi]
- 2 1024-channel high-compliance-voltage SoC for epiretinal prosthesesKuanfu Chen, Yi-Kai Lo, Wentai Liu. 294-295 [doi]
- 2/pixel 512-channel self-calibrating epiretinal prosthesis in 65nm CMOSManuel Monge, Mayank Raj, Meisam Honarvar Nazari, Jay Han-Chieh Chang, Yu Zhao, James D. Weiland, Mark S. Humayun, Yu-Chong Tai, Azita Emami-Neyestanak. 296-297 [doi]
- A near-field-communication (NFC) enabled wireless fluorimeter for fully implantable biosensing applicationsAndrew David Dehennis, Marko Mailand, David Grice, Stefan Getzlaff, Arthur E. Colvin. 298-299 [doi]
- An integrated magnetic spectrometer for multiplexed biosensingConstantine Sideris, Ali Hajimiri. 300-301 [doi]
- A 20µW intra-cardiac signal-processing IC with 82dB bio-impedance measurement dynamic range and analog feature extraction for ventricular fibrillation detectionSunyoung Kim, Long Yan, Srinjoy Mitra, Masato Osawa, Yasunari Harada, Kosei Tamiya, Chris Van Hoof, Refet Firat Yazicioglu. 302-303 [doi]
- Session 17 overview: High-performance DRAM interfacesYasuhiro Takai, James Sung. 304-305 [doi]
- A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systemsKambiz Kaviani, Michael Bucher, Bruce Su, Barry Daly, Bill Stonecypher, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Pravin Kumar Venkatesan, Fred Heaton, Ravi Kollipara, Yi Lu, Chris J. Madden, John C. Eble, Lei Luo, Nhat Nguyen. 306-307 [doi]
- A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RXSoo-Min Lee, Jong-Hoon Kim, Jong-Sam Kim, Yunsaing Kim, Hyunbae Lee, Jae-Yoon Sim, Hong June Park. 308-309 [doi]
- A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOSMarcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf. 310-311 [doi]
- An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interfaceJunyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim. 312-313 [doi]
- Session 18 overview: Advanced embedded SRAMMichael Clinton, Atsushi Kawasumi. 314-315 [doi]
- A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applicationsJonathan Chang, Yen-Huei Chen, Hank Cheng, Wei-Min Chan, Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang. 316-317 [doi]
- An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/accessMahmut E. Sinangil, Anantha P. Chandrakasan. 318-319 [doi]
- A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuitFumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa. 320-321 [doi]
- A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reductionHarold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad I. Younus. 322-323 [doi]
- 7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processorJohn Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner. 324-325 [doi]
- Session 19 overview: Wireless transceivers for smart devicesSven Mattisson, Koji Takinam. 326-327 [doi]
- A fully integrated 2×2 b/g and 1×2 a-band MIMO WLAN SoC in 45nm CMOS for multi-radio ICRakesh Kumar, T. Krishnaswamy, Gireesh Rajendran, Debapriya Sahu, Apu Sivadas, Murali Nandigam, Saravana Ganeshan, Srihari Datla, Anand Kudari, Hemant Bhasin, Meghna Agrawal, Subramanian Narayan, Yogesh Dharwekar, Robin Garg, Vimal Edayath, Thirunaavukkarassu Suseela, Vikram Jayaram, Shankar Ram, Vidhya Murugan, Anil Kumar, Subhashish Mukherjee, Nagaraj Dixit, Eran Nussbaum, Joel Dror, Nir Ginzburg, Asaf EvenChen, Asaf Maruani, Swaminathan Sankaran, Venkatesh Srinivasan, Vijay Rentala. 328-329 [doi]
- A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOSLu Ye, Jiashu Chen, Lingkai Kong, Philippe Cathelin, Elad Alon, Ali M. Niknejad. 330-331 [doi]
- A 24.7dBm all-digital RF transmitter for multimode broadband applications in 40nm CMOSChao Lu, Hua Wang, C. H. Peng, Ankush Goel, SangWon Son, Paul C. P. Liang, Ali Niknejad, H. C. Hwang, George Chien. 332-333 [doi]
- 2 radio in 40nm CMOSChun-Geik Tan, Fei Song, Tieng Yi Choke, Ming Kong, De-Cheng Song, Chee-Hong Yong, Weimin Shu, Zong Hua You, Yi-Hsien Lin, Osama Shana'a. 334-335 [doi]
- A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregationLars Sundström, Martin Anderson, Roland Strandberg, Staffan Ek, Jim Svensson, Fenghao Mu, Thomas Olsson, Imad ud Din, Leif R. Wilhelmsson, Daniel Eckerbert, Sven Mattisson. 336-337 [doi]
- A multiband 40nm CMOS LTE SAW-less modulator with -60dBc C-IM3Mark Ingels, Yoshikazu Furuta, Xiaoqiang Zhang, Sungwoo Cha, Jan Craninckx. 338-339 [doi]
- An LTE transmitter using a class-A/B power mixerPaolo Rossi, Nicola Codega, Danilo Gerna, Antonio Liscidini, Daniele Ottini, Yong He, Alberto Pirola, Enrico Sacchi, Gregory Uehara, Chao Yang, Rinaldo Castello. 340-341 [doi]
- 2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOSJie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C. P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, Robert Bogdan Staszewski. 342-343 [doi]
- Session 20 overview: Frequency generationMarc Tiebout, Jing-Hong Conan Zhan. 344-345 [doi]
- A 2.5-to-3.3GHz CMOS Class-D VCOLuca Fanori, Pietro Andreani. 346-347 [doi]
- Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOMMasoud Babaie, Robert Bogdan Staszewski. 348-349 [doi]
- A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extensionEnrico Mammei, Enrico Monaco, Andrea Mazzanti, Francesco Svelto. 350-351 [doi]
- A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOSWanghua Wu, Xuefei Bai, Robert Bogdan Staszewski, John R. Long. 352-353 [doi]
- A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOSXiang Yi, Chirn Chye Boon, Hang Liu, Jia-fu Lin, Jian Cheng Ong, Wei Meng Lim. 354-355 [doi]
- A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N dividerRoberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt. 356-357 [doi]
- A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tunersZhangwen Tang, Xiongxiong Wan, Minggui Wang, Jie Liu. 358-359 [doi]
- Session 21 overview: Power convertersWing-Hung Ki, Marco Berkhout. 360-361 [doi]
- An 82.4% efficiency package-bondwire-based four-phase fully integrated buck converter with flying capacitor for area reductionCheng Huang, Philip K. T. Mok. 362-363 [doi]
- An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiencyPatrick Riehl, Paul Fowers, Hao-Ping Hong, Michael Ashburn. 364-365 [doi]
- A CMOS dual-switching power-supply modulator with 8% efficiency improvement for 20MHz LTE Envelope Tracking RF power amplifiersMuhammad Hassan, Peter M. Asbeck, Lawrence E. Larson. 366-367 [doi]
- 90.6% efficient 11MHz 22W LED driver using GaN FETs and burst-mode controller with 0.96 power factorSaurav Bandyopadhyay, Bob Neidorff, Dave Freeman, Anantha P. Chandrakasan. 368-369 [doi]
- A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolutionSuyoung Bang, Allan Wang, Bharan Giridhar, David Blaauw, Dennis Sylvester. 370-371 [doi]
- 2 at 73% efficiencyHanh-Phuc Le, John Crossley, Seth Sanders, Elad Alon. 372-373 [doi]
- A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitorsDina El-Damak, Saurav Bandyopadhyay, Anantha P. Chandrakasan. 374-375 [doi]
- A soft self-commutating method using minimum control circuitry for multiple-string LED driversJunsik Kim, Jiyong Lee, Shihong Park. 376-377 [doi]
- Session 22 overview: Sensors & displaysAaron Partridge, Young-Sun Na. 378-379 [doi]
- A fully differential charge-balanced accelerometer for Electronic Stability ControlVladimir P. Petkov, Ganesh K. Balachandran, Jochen Beintner. 380-381 [doi]
- 2 AC-biased MEMS microphone interface with 58dBA SNRSelcuk Ersoy, Robert H. M. van Veldhoven, Fabio Sebastiano, Klaus Reimann, Kofi A. A. Makinwa. 382-383 [doi]
- A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizerMohammad Alhawari, Nadya Albelooshi, Michael H. Perrott. 384-385 [doi]
- A micropower battery current sensor with ±0.03% (3σ) inaccuracy from -40 to +85°CSaleh Heidary Shalmany, Dieter Draxelmayr, Kofi A. A. Makinwa. 386-387 [doi]
- A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing techniqueHyungcheol Shin, Seunghoon Ko, Hongjae Jang, Ilhyun Yun, Kwyro Lee. 388-389 [doi]
- A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panelsJunhyeok Yang, Sang-Hui Park, Jung Min Choi, Hyunsik Kim, Changbyung Park, Seung-Tak Ryu, Gyu-Hyeong Cho. 390-391 [doi]
- A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDsHyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho. 392-393 [doi]
- A [10°C; 70°C] 640×480 17µm pixel pitch TEC-less IR bolometer imager with below 50mK and below 4V power supplyBertrand Dupont, Antoine Dupret, Sebastien Becker, Antoine Hamelin, Fabrice Guellec, Pierre Imperinetti, Wilfried Rabaud. 394-395 [doi]
- 3D volumetric ultrasound imaging with a 32×32 CMUT array integrated with front-end ICs using flip-chip bonding technologyAnshuman Bhuyan, Jung Woo Choe, Byung-chul Lee, Ira O. Wygant, Amin Nikoozadeh, Ömer Oralkan, Butrus T. Khuri-Yakub. 396-397 [doi]
- Session 23 overview: Short-reach links, XCVR techniques, & PLLsGerrit den Besten, Koichi Yamaguchi. 398-399 [doi]
- A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOIYong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman. 400-401 [doi]
- A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOSMozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper. 402-403 [doi]
- A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applicationsJohn W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, C. Thomas Gray. 404-405 [doi]
- A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signalingKen'ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno. 406-407 [doi]
- An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOSMarcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf. 408-409 [doi]
- An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection schemeJi-Hwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, Lee-Sup Kim. 410-411 [doi]
- A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOSKanupriya Bhardwaj, Sriram Narayan, Sergey Shumarayev, Thomas Lee. 412-413 [doi]
- A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timingI-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh. 414-415 [doi]
- A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentationTsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn. 416-417 [doi]
- Session 24 overview: Energy-aware digital designWim Dehaene, Masaya Sumita. 418-419 [doi]
- A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processingDaisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa. 420-421 [doi]
- A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gatingYoun Sung Park, Yaoyu Tao, Zhengya Zhang. 422-423 [doi]
- Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technologyPhilippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard. 424-425 [doi]
- Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOSJian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang. 426-427 [doi]
- A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOSPaul N. Whatmough, Shidhartha Das, David M. Bull. 428-429 [doi]
- Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOSMario Konijnenburg, Yeongojn Cho, Maryam Ashouei, Tobias Gemmeke, Changmoo Kim, Jos Hulzink, Jan Stuyt, Mookyung Jung, Jos Huisken, Soojung Ryu, Jungwook Kim, Harmke de Groot. 430-431 [doi]
- An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitionsSteven Bartling, Sudhanshu Khanna, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams. 432-433 [doi]
- A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturingSatoshi Takaya, Makoto Nagata, Atsushi Sakai, Takashi Kariya, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda. 434-435 [doi]
- Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuitsHiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. 436-437 [doi]
- Session 25 overview: Energy-efficient wirelessShouhei Kousai, Gangadhar Burra. 438-439 [doi]
- A 45nm CMOS near-field communication radio with 0.15A/m RX sensitivity and 4mA current consumption in card emulation modeYogesh Darwhekar, Evgeniy Braginskiy, Koby Levy, Abhishek Agrawal, Vikas Singh, Ronen Issac, Ofer Blonskey, Ofer Adler, Yoav Benkuzari, Matan Ben-Shachar, Srikanth Manian, Apu Sivadas, Subhashish Mukherjee, Gangadhar Burra, Nir Tal, Yariv Shlivinski, Guy Bitton, Sreekiran Samala. 440-441 [doi]
- An ultra-low-power 9.8GHz crystal-less UWB transceiver with digital baseband integrated in 0.18µm BiCMOSJonathan K. Brown, Kuo-Ken Huang, Elnaz Ansari, Ryan R. Rogel, Yoonmyung Lee, David D. Wentzloff. 442-443 [doi]
- A self-duty-cycled and synchronized UWB receiver SoC consuming 375pJ/b for -76.5dBm sensitivity at 2Mb/sBaradwaj Vigraham, Peter R. Kinget. 444-445 [doi]
- A 1.9nJ/b 2.4GHz multistandard (Bluetooth Low Energy/Zigbee/IEEE802.15.6) transceiver for personal/body-area networksYao-Hong Liu, Xiongchuan Huang, Maja Vidojkovic, Ao Ba, Pieter Harpe, Guido Dolmans, Harmke de Groot. 446-447 [doi]
- 2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOSZhicheng Lin, Pui-In Mak, Rui Paulo Martins. 448-449 [doi]
- A 110pJ/b multichannel FSK/GMSK/QPSK/p/4-DQPSK transmitter with phase-interpolated dual-injection DLL-based synthesizer employing hybrid FIRSan-Jeow Cheng, Yuan Gao, Wei-Da Toh, Yuanjin Zheng, Minkyu Je, Chun-Huat Heng. 450-451 [doi]
- A 5.5mW IEEE-802.15.6 wireless body-area-network standard transceiver for multichannel electro-acupuncture applicationHyungwoo Lee, Kwonjoon Lee, Sunjoo Hong, Kiseok Song, Taehwan Roh, Joonsung Bae, Hoi-Jun Yoo. 452-453 [doi]
- Wideband UHF ISM-band transceiver supporting multichannel reception and DSSS modulationJan van Sinderen, Gerben W. de Jong, Frank Leong, Xin He, Melina Apostolidou, Harish Kundur Subramaniyan, Robert Rutten, Jan Niehof, Jos Verlinden, Hao Wang, Anton Hoogstraate, Ka Chun Kwok, Rene Verlinden, Reinier Hoogendoorn, Dennis Jeurissen, Anton Salfelner, Ewald Bergler, Javier M. Velandia Torres, Christopher J. Haji-Michael, Thomas Unterweger, Esa Tarvainen, Martin Posch, Reinhold Schmidt, Markus Stattmann, Jacek Tyminski, Patrick Jean, Sébastien Darfeuille, Olivier Aymard, Alexis le Grontec, Claire Boucey, Christophe Kelma, Guillaume Monnerie. 454-455 [doi]
- A 1.6mW 300mV-supply 2.4GHz receiver with -94dBm sensitivity for energy-harvesting applicationsFan Zhang, Keping Wang, Jabeom Koo, Yasunori Miyahara, Brian P. Otis. 456-457 [doi]
- A super-regenerative radio on plastic based on thin-film transistors and antennas on large flexible sheets for distributed communication linksLiechao Huang, Warren Rieutort-Louis, Yingzhe Hu, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma. 458-459 [doi]
- Session 26 overview: High-speed data convertersBoris Murmann, Tetsuya Iizuka. 460-461 [doi]
- A 10.3GS/s 6b flash ADC for 10G Ethernet applicationsShwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos. 462-463 [doi]
- An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOSErwin Janssen, Kostas Doris, Athon Zanikopoulos, Alessandro Murroni, Gerard Van der Weide, Yu Lin, Ludo Alvado, Frederic Darthenay, Yannick Fregeais. 464-465 [doi]
- A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correctionBrian Setterberg, Ken Poulton, Sourja Ray, Dan J. Huber, Valentin Abramzon, Guenter Steinbach, John P. Keane, Bernd Wuppermann, Mathew Clayson, Matthew Martin, Rizwan Pasha, Edda Peeters, Annemie Jacobs, Filip Demarsin, Adnan Al-Adnani, Peter Brandt. 466-467 [doi]
- A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOSLukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici. 468-469 [doi]
- An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancementHyeok-Ki Hong, Hyun-Wook Kang, Barosaim Sung, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, Seung-Tak Ryu. 470-471 [doi]
- A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOSRon Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi. 472-473 [doi]
- A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidthWei-te Lin, Tai-Haur Kuo. 474-475 [doi]
- Session 27 overview: Image sensorsRobert Johansson, Shoji Kawahito. 476-477 [doi]
- A 3.4µW CMOS image sensor with embedded feature-extraction algorithm for motion-triggered object-of-interest imagingJaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon. 478-479 [doi]
- A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregationGyouho Kim, Mahmood Barangi, Zhiyoong Foo, Nathaniel Ross Pinckney, Suyoung Bang, David Blaauw, Dennis Sylvester. 480-481 [doi]
- A rolling-shutter distortion-free 3D stacked image sensor with -160dB parasitic light sensitivity in-pixel storage nodeJun Aoki, Yoshiaki Takemoto, Kenji Kobayashi, Naofumi Sakaguchi, Mitsuhiro Tsukimura, Naohiro Takazawa, Hideki Kato, Toru Kondo, Haruhisa Saito, Yuichi Gomi, Yoshitaka Tadaki. 482-483 [doi]
- A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensorShunichi Sukegawa, Taku Umebayashi, Tsutomu Nakajima, Hiroshi Kawanobe, Ken Koseki, Isao Hirota, Tsutomu Haruta, Masanori Kasai, Koji Fukumoto, Toshifumi Wakano, Keishi Inoue, Hiroshi Takahashi, Takashi Nagano, Yoshikazu Nitta, Teruo Hirayama, Noriyuki Fukushima. 484-485 [doi]
- An 8×16-pixel 92kSPAD time-resolved sensor with on-pixel 64ps 12b TDC and 100MS/s real-time energy histogramming in 0.13µm CIS technology for PET/MRI applicationsLeo Huf Campos Braga, Leonardo Gasparini, Lindsay Grant, Robert K. Henderson, Nicola Massari, Matteo Perenzoni, David Stoppa, Richard J. Walker. 486-487 [doi]
- A 0.18µm CMOS SoC for a 100m-range 10fps 200×96-pixel time-of-flight depth sensorCristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Masaru Ogawa, Manabu Kagami. 488-489 [doi]
- 3D camera based on linear-mode gain-modulated avalanche photodiodesOlga Shcherbakova, Lucio Pancheri, Gian-Franco Dalla Betta, Nicola Massari, David Stoppa. 490-491 [doi]
- A 3D vision 2.1Mpixel image sensor for single-lens camera systemsShinzo Koyama, Kazutoshi Onozawa, Keisuke Tanaka, Yoshihisa Kato. 492-493 [doi]
- A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADCJun Deguchi, Fumihiko Tachibana, Makoto Morimoto, Masayoshi Chiba, Takeshi Miyaba, Hideki Tanaka, Kyoichi Takenaka, Satoshi Funayama, Kunihiko Amano, Kazuhide Sugiura, Ryuta Okamoto, Shouhei Kousai. 494-495 [doi]
- F1: Advanced RF transceiver design techniquesAlbert Jerng, Yorgos Palaskas, Eric A. M. Klumperink, Didier Belot, Songcheol Hong, Brian A. Floyd. 500-501 [doi]
- F2: VLSI power-management techniques: Principles and applicationsLeland Chang, Shannon Morton, Ken Chang, Leland Chang, Jin-Man Han, Piero Malcovati, Shannon Morton, Vladimir Stojanovic. 502-503 [doi]
- F3: Emerging technologies for wireline communicationElad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi. 504-505 [doi]
- F4: Scientific imagingMakoto Ikeda, Ehsan Afshari, Yusuke Oike, David Ruffieux, Johannes Solhusvik, Albert Theuwissen. 506-507 [doi]
- F5: Frequency generation and clock distributionAntonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner. 508-509 [doi]
- F6: Mixed-signal/RF design and modeling in next-generation CMOSBoris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu. 510-511 [doi]
- ES1: Student research previewJan Van der Spiegel. 512 [doi]
- ES2: "batteries not included." - How little is enough for real energy autonomy?Minkyu Je, Axel Thomsen, Axel Thomsen, Minkyu Je. 513 [doi]
- EP1: Antiques from the innovations atticTrudy Stetzler, Anantha Chandrakasan, Bram Nauta. 514 [doi]
- ES3: High-speed communications on 4 wheels: What's in your next car?Nicola Da Dalt, Ajith Amerasekera. 515 [doi]
- EP2: You're hired! The top 25 interview questions for circuit designersMichael P. Flynn, John Khoury. 516 [doi]
- EP3: Empowering the killer SoC applications of 2020Shekhar Borkar, Uming Ko, Ali Keshavarzi, Ali Keshavarzi, Eugenio Cantatore. 517 [doi]
- RF blocks for wireless transceiversWilly Sansen, Hooman Darabi, John R. Long, Ali Hajimiri, Ali Niknejad. 518 [doi]
- International technical program committeeBram Nauta, Trudy Stetzler. 525-526 [doi]