Anand Raghunathan - researchr alias

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2011

2010

Special session 11B: Hot topic hardware security: Design, test and verification issuesSwarup Bhunia, Anand Raghunathan. vts 2010: 349 [doi]

Best-effort semantic document search on GPUsSurendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi. asplos 2010: 86-93 [doi]

Best-effort computing: re-thinking parallel software and hardwareSrimat T. Chakradhar, Anand Raghunathan. dac 2010: 865-870 [doi]

Variation-Aware System-Level Power AnalysisSaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. tvlsi, 18(8):1173-1184, 2010. [doi]

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiencyVinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar. dac 2010: 555-560 [doi]

A Secure User Interface for Web Applications Running Under an Untrusted Operating SystemChunxiao Li, Anand Raghunathan, Niraj K. Jha. IEEEcit 2010: 865-870 [doi]

Exploiting the forgiving nature of applications for scalable parallel executionJiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Surendra Byna. ipps 2010: 1-12 [doi]

Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous ComponentsKaushik Roy, Byunghoo Jung, Anand Raghunathan. vlsid 2010: 464-469 [doi]

2009

2008

Dynamic Binary Instrumentation-Based Framework for Malware DefenseNajwa Aaraj, Anand Raghunathan, Niraj K. Jha. dimva 2008: 64-87 [doi]

Analysis and design of a hardware/software trusted platform module for embedded systemsNajwa Aaraj, Anand Raghunathan, Niraj K. Jha. tecs, 8(1), 2008. [doi]

Systematic Software-Based Self-Test for Pipelined ProcessorsDimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, M. Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi. tvlsi, 16(11):1441-1453, 2008. [doi]

Dynamically Configurable Bus Topologies for High-Performance On-Chip CommunicationKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. tvlsi, 16(10):1413-1426, 2008. [doi]

Efficient Software Architecture for IPSec Acceleration Using a Programmable Security ProcessorJanar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar. date 2008: 1148-1153 [doi]

2007

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded SystemsNajwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tvlsi, 15(3):296-308, 2007. [doi]

Energy and execution time analysis of a software-based trusted platform moduleNajwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. date 2007: 1128-1133 [doi]

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoCDivya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar. tvlsi, 15(6):699-710, 2007. [doi]

Architectural Support for Run-Time Validation of Program Data PropertiesDivya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tvlsi, 15(5):546-559, 2007. [doi]

Automatic Power Modeling of Infrastructure IP for System-on-Chip Power AnalysisNikhil Bansal, Kanishka Lahiri, Anand Raghunathan. vlsid 2007: 513-520 [doi]

System-on-Chip Power Management Considering Leakage Power VariationsSaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. dac 2007: 877-882 [doi]

Energy-optimizing source code transformations for operating system-driven embedded softwareYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tecs, 7(1), 2007. [doi]

Accelerating System-on-Chip Power Analysis Using Hybrid Power EstimationMohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan. dac 2007: 883-886 [doi]

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level SynthesisChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tvlsi, 15(11):1191-1204, 2007. [doi]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan, editors, ACM, 2007.

Automated Energy/Performance Macromodeling of Embedded SoftwareAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. tcad, 26(3):542-552, 2007. [doi]

Hybrid Simulation for Energy Estimation of Embedded SoftwareAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. tcad, 26(10):1843-1854, 2007. [doi]

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based AnalysisNachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee. tvlsi, 15(4):465-470, 2007. [doi]

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol ExecutionNachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha. tvlsi, 15(5):605-609, 2007. [doi]

Guest Editors Introduction: Security and Trust in Embedded-Systems DesignPatrick Schaumont, Anand Raghunathan. dt, 24(6):518-520, 2007. [doi]

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible ProcessorsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tcad, 26(11):2035-2045, 2007. [doi]

2006

Architectures for efficient face authentication in embedded systemsNajwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. date 2006: 1-6 [doi]

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded ProcessorsDivya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tvlsi, 14(12):1295-1308, 2006. [doi]

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoCDivya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar. dac 2006: 496-501 [doi]

Architectural support for safe software execution on embedded processorsDivya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. codes 2006: 106-111 [doi]

Considering process variations during system-level power analysisSaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. islped 2006: 342-345 [doi]

Use of Computation-Unit Integrated Memories in High-Level SynthesisChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tcad, 25(10):1969-1989, 2006. [doi]

The LOTTERYBUS on-chip communication architectureKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana. tvlsi, 14(6):596-608, 2006. [doi]

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression TechniquesLoganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar. tcad, 25(10):2193-2206, 2006. [doi]

Active Learning Driven Data Acquisition for Sensor NetworksAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. ISCC 2006: 929-934 [doi]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006Wolfgang Nebel, Mircea R. Stan, Anand Raghunathan, Jörg Henkel, Diana Marculescu, editors, ACM, 2006.

Satisfiability-based framework for enabling side-channel attacks on cryptographic softwareNachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee. date 2006: 18-23 [doi]

Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded ProcessorsNachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha. vlsid 2006: 299-304 [doi]

A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security ProtocolsNachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tmc, 5(2):128-143, 2006. [doi]

Systematic software-based self-test for pipelined processorsMihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi. dac 2006: 393-398 [doi]

Integrated data relocation and bus reconfiguration for adaptive system-on-chip platformsKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. date 2006: 728-733 [doi]

Adaptive data placement in an embedded multiprocessor thread libraryPhillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan. date 2006: 698-699 [doi]

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible ProcessorsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. vlsid 2006: 473-476 [doi]

Application-specific heterogeneous multiprocessor synthesis using extensible processorsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tcad, 25(9):1589-1602, 2006. [doi]

A Scalable Synthesis Methodology for Application-Specific ProcessorsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tvlsi, 14(11):1175-1188, 2006. [doi]

RTL-Aware Cycle-Accurate Functional Power EstimationLin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tcad, 25(10):2103-2117, 2006. [doi]

2005

Secure Embedded Processing through Hardware-Assisted Run-Time MonitoringDivya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. date 2005: 178-183 [doi]

Enhancing security through hardware-assisted run-time validation of program data propertiesDivya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. codes 2005: 190-195 [doi]

Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power ModelsNikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar. vlsid 2005: 579-585 [doi]

Hardware Accelerated Power EstimationJoel Coburn, Srivaths Ravi, Anand Raghunathan. date 2005: 528-529 [doi]

Power emulation: a new paradigm for power estimationJoel Coburn, Srivaths Ravi, Anand Raghunathan. dac 2005: 700-705 [doi]

SECA: security-enhanced communication architectureJoel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar. cases 2005: 78-89 [doi]

Efficient fingerprint-based user authentication for embedded systemsPallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. dac 2005: 244-247 [doi]

Generation of distributed logic-memory architectures through high-level synthesisChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tcad, 24(11):1694-1711, 2005. [doi]

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-ChipLoganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar. vlsid 2005: 65-70 [doi]

Hybrid simulation for embedded software energy estimationAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. dac 2005: 23-26 [doi]

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topologyKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. dac 2005: 571-574 [doi]

Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible ProcessorsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. vlsid 2005: 551-556 [doi]

Energy macromodeling of embedded operating systemsTat Kee Tan, Anand Raghunathan, Niraj K. Jha. tecs, 4(1):231-254, 2005. [doi]

Input space-adaptive optimization for embedded-software synthesisWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. tcad, 24(11):1677-1693, 2005. [doi]

2004

A hybrid energy-estimation technique for extensible processorsYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tcad, 23(5):652-664, 2004. [doi]

Energy-Optimizing Source Code Transformations for OS-driven Embedded SoftwareYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. vlsid 2004: 261-266 [doi]

High-level synthesis using computation-unit integrated memoriesChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. iccad 2004: 783-790 [doi]

Power analysis of system-level on-chip communication architecturesKanishka Lahiri, Anand Raghunathan. codes 2004: 236-241 [doi]

Efficient power profiling for battery-driven embedded system designKanishka Lahiri, Anand Raghunathan, Sujit Dey. tcad, 23(6):919-932, 2004. [doi]

Design space exploration for optimizing on-chip communication architecturesKanishka Lahiri, Anand Raghunathan, Sujit Dey. tcad, 23(6):952-961, 2004. [doi]

Design of high-performance system-on-chips using communication architecture tunersKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey. tcad, 23(5):620-636, 2004. [doi]

Common-case computation: a high-level energy and performance optimization techniqueGanesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey. tcad, 23(1):33-49, 2004. [doi]

Automated energy/performance macromodeling of embedded softwareAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. dac 2004: 99-102 [doi]

Tamper Resistance Mechanisms for Secure, Embedded SystemsSrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar. vlsid 2004: 605 [doi]

Security as a new dimension in embedded system designSrivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan. dac 2004: 753-760 [doi]

Security in embedded systems: Design challengesSrivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady. tecs, 3(3):461-491, 2004. [doi]

Custom-instruction synthesis for extensible-processor platformsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. tcad, 23(2):216-228, 2004. [doi]

An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded SoftwareTat Kee Tan, Anand Raghunathan, Niraj K. Jha. csreaESA 2004: 601-605

Resource budgeting for Multiprocess High-level synthesisWeidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey. tcad, 23(7):1010-1019, 2004. [doi]

Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance OptimizationWeidong Wang, Anand Raghunathan, Niraj K. Jha. vlsid 2004: 267 [doi]

Input space adaptive design: a high-level methodology for optimizing energy and performanceWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. tvlsi, 12(6):590-602, 2004. [doi]

Power estimation for cycle-accurate functional descriptions of hardwareLin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. iccad 2004: 668-675 [doi]

2003

A scalable software-based self-test methodology for programmable processorsLi Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey. dac 2003: 548-553 [doi]

Energy Estimation for Extensible ProcessorsYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. date 2003: 10682-10687 [doi]

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive ApplicationsChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. iccad 2003: 46-53 [doi]

Securing Mobile Appliances: New Challenges for the System DesignerAnand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater. date 2003: 10176-10183 [doi]

High-level macro-modeling and estimation techniques for switching activity and power consumptionAnand Raghunathan, Sujit Dey, Niraj K. Jha. tvlsi, 11(4):538-557, 2003. [doi]

Efficient RTL Power Estimation for Large DesignsSrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar. vlsid 2003: 431-439 [doi]

Embedding Security in Wireless Embedded SystemsSrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar. vlsid 2003: 269-270 [doi]

A Scalable Application-Specific Processor Synthesis MethodologyFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. iccad 2003: 283-290 [doi]

A simulation framework for energy-consumption analysis of OS-driven embedded applicationsTat Kee Tan, Anand Raghunathan, Niraj K. Jha. tcad, 22(9):1284-1294, 2003. [doi]

High-level Synthesis of Multi-process Behavioral DescriptionsWeidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey. vlsid 2003: 467-473 [doi]

A comprehensive high-level synthesis system for control-flow intensive behaviorsWeidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha. glvlsi 2003: 11-14 [doi]

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