Naresh R. Shanbhag - researchr alias

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2011

System energy minimization via joint optimization of the DC-DC converter and the coreRami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein. islped 2010: 97-102 [doi]

VLSI Architectures for Soft-Decision Decoding of Reed-Solomon CodesArshad Ahmed, Ralf Koetter, Naresh R. Shanbhag. TIT, 57(2):648-667, 2011. [doi]

Least squares approximation and polyphase decomposition for pipelining recursive filtersAditya Gupta, Andrew C. Singer, Naresh R. Shanbhag. icassp 2011: 1661-1664 [doi]

2010

Robust and energy-efficient DSP systems via output probability processingRami A. Abdallah, Naresh R. Shanbhag. iccd 2010: 38-44 [doi]

Soft NMR: Analysis & application to DSP systemsEric P. Kim, Naresh R. Shanbhag. icassp 2010: 1494-1497 [doi]

BER-optimal analog-to-digital converters for communication linksMinwei Lu, Naresh R. Shanbhag, Andrew C. Singer. iscas 2010: 1029-1032 [doi]

Computation as estimation: a general framework for robustness and energy efficiency in SoCsSriram Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag. tsp, 58(8):4416-4421, 2010. [doi]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim, editors, ACM, 2010.

Stochastic computationNaresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones. dac 2010: 859-864 [doi]

Stochastic Networked ComputationGirish Varatkar, Shrikanth S. Narayanan, Naresh R. Shanbhag, Douglas L. Jones. tvlsi, 18(10):1421-1432, 2010. [doi]

2009

2008

Error-resilient low-power Viterbi decodersRami A. Abdallah, Naresh R. Shanbhag. islped 2008: 111-116 [doi]

Error-resilient low-power Viterbi decoders via state clusteringRami A. Abdallah, Naresh R. Shanbhag. sips 2008: 221-226 [doi]

Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumptionShrikanth Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag. icassp 2008: 1421-1424 [doi]

The Search for Alternative Computational ParadigmsNaresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet Roychowdhury, Douglas L. Jones, Jan M. Rabaey. dt, 25(4):334-343, 2008. [doi]

Joint Equalization and Coding for On-Chip Bus CommunicationSrinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag. tvlsi, 16(3):314-318, 2008. [doi]

Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chipGirish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones. glvlsi 2008: 351-354 [doi]

Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOCGirish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones. iscas 2008: 380-383 [doi]

Error-Resilient Motion Estimation ArchitectureGirish Varatkar, Naresh R. Shanbhag. tvlsi, 16(10):1399-1412, 2008. [doi]

2007

Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical CodesSrinivasa R. Sridhara, Naresh R. Shanbhag. tcad, 26(5):977-982, 2007. [doi]

Variation-Tolerant Motion Estimation ArchitectureGirish Varatkar, Naresh R. Shanbhag. sips 2007: 126-131 [doi]

2006

Energy-efficient soft error-tolerant digital signal processingByonghyo Shim, Naresh R. Shanbhag. tvlsi, 14(4):336-348, 2006. [doi]

Energy-efficient motion estimation using error-toleranceGirish Varatkar, Naresh R. Shanbhag. islped 2006: 113-118 [doi]

Soft-Error-Rate-Analysis (SERA) MethodologyMing Zhang, Naresh R. Shanbhag. tcad, 25(10):2140-2155, 2006. [doi]

Sequential Element Design With Built-In Soft Error ResilienceMing Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel. tvlsi, 14(12):1368-1378, 2006. [doi]

2005

Linear turbo equalization analysis via BER transfer and EXIT chartsSeok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag. tsp, 53(8-1):2883-2897, 2005. [doi]

Energy Efficient VLSI Architecture for Linear Turbo EqualizerSeok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer. vlsisp, 39(1-2):49-62, 2005. [doi]

Area-efficient high-throughput MAP decoder architecturesSeok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer. tvlsi, 13(8):921-933, 2005. [doi]

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC CodesMohammad M. Mansour, Naresh R. Shanbhag. vlsisp, 40(3):371-382, 2005. [doi]

Guest EditorialNaresh R. Shanbhag, Keshab K. Parhi. vlsisp, 39(1-2):5-6, 2005. [doi]

Coding for Reliable On-Chip Buses: Fundamental Limits and Practical CodesSrinivasa R. Sridhara, Naresh R. Shanbhag. vlsid 2005: 417-422 [doi]

Joint Equalization and Coding for On-Chip Bus CommunicationSrinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan. isqed 2005: 642-647 [doi]

Coding for system-on-chip networks: a unified frameworkSrinivasa R. Sridhara, Naresh R. Shanbhag. tvlsi, 13(6):655-667, 2005. [doi]

A low-power bus design using joint repeater insertion and codingSrinivasa R. Sridhara, Naresh R. Shanbhag. islped 2005: 99-102 [doi]

An energy-efficient circuit technique for single event transient noise-toleranceMing Zhang, Naresh R. Shanbhag. iscas 2005: 636-639 [doi]

2004

Switching methods for linear turbo equalizationSeok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer. iscas 2004: 601-604 [doi]

A communication-theoretic design paradigm for reliable SOCsNaresh R. Shanbhag. dac 2004: 76 [doi]

Reliable and Efficient System-on-Chip DesignNaresh R. Shanbhag. Computer, 37(3):42-50, 2004. [doi]

Reliable low-power digital signal processing via reduced precision redundancyByonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag. tvlsi, 12(5):497-510, 2004.

Coding for system-on-chip networks: a unified frameworkSrinivasa R. Sridhara, Naresh R. Shanbhag. dac 2004: 103-106 [doi]

Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip BusesSrinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag. iccd 2004: 12-17 [doi]

A soft error rate analysis (SERA) methodologyMing Zhang, Naresh R. Shanbhag. iccad 2004: 111-118 [doi]

2003

High bandwidth transimpedance amplifier design using active transmission linesHyeon-Min Bae, Naresh R. Shanbhag. iscas 2003: 253-256 [doi]

Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O LinksGanesh Balamurugan, Naresh R. Shanbhag. iccd 2003: 254-260 [doi]

A low-power VLSI architecture for turbo decodingSeok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer. islped 2003: 366-371 [doi]

High-throughput LDPC decodersMohammad M. Mansour, Naresh R. Shanbhag. tvlsi, 11(6):976-996, 2003. [doi]

Architecture-aware low-density parity-check codesMohammad M. Mansour, Naresh R. Shanbhag. iscas 2003: 57-60 [doi]

VLSI architectures for SISO-APP decodersMohammad M. Mansour, Naresh R. Shanbhag. tvlsi, 11(4):627-650, 2003. [doi]

Performance analysis of algorithmic noise-tolerance techniquesByonghyo Shim, Naresh R. Shanbhag. iscas 2003: 113-116 [doi]

Low-power MIMO signal processingLei Wang, Naresh R. Shanbhag. tvlsi, 11(3):434-445, 2003. [doi]

Energy-efficiency bounds for deep submicron VLSI systems in the presence of noiseLei Wang, Naresh R. Shanbhag. tvlsi, 11(2):254-269, 2003. [doi]

2002

Simplified current and delay models for deep submicron CMOS digital circuitsMohammad M. Mansour, Naresh R. Shanbhag. iscas 2002: 109-112 [doi]

Low-power VLSI decoder architectures for LDPC codesMohammad M. Mansour, Naresh R. Shanbhag. islped 2002: 284-289 [doi]

Reliable and energy-efficient digital signal processingNaresh R. Shanbhag. dac 2002: 830-835 [doi]

2001

2000

Toward achieving energy efficiency in presence of deep submicron noiseRajamohana Hegde, Naresh R. Shanbhag. tvlsi, 8(4):379-391, 2000. [doi]

Coupling-Driven Signal Encoding Scheme for Low-Power Interface DesignKi-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang. iccad 2000: 318-321

Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)Naresh R. Shanbhag, K. Soumyanath, Samuel Martin. islped 2000: 295-302 [doi]

1999

Energy-efficient dynamic circuit design in the presence of crosstalk noiseGanesh Balamurugan, Naresh R. Shanbhag. islped 1999: 24-29 [doi]

Analytical Expressions for Power Dissipation of Macro-blocks in DSP ArchitecturesSudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag. vlsid 1999: 358 [doi]

Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processingManish Goel, Naresh R. Shanbhag. tvlsi, 7(4):463-476, 1999. [doi]

Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSIRajamohana Hegde, Naresh R. Shanbhag. iscas 1999: 334-337 [doi]

Energy-efficient signal processing via algorithmic noise-toleranceRajamohana Hegde, Naresh R. Shanbhag. islped 1999: 30-35 [doi]

Information-theoretic bounds on average signal transition activity [VLSI systems]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. tvlsi, 7(3):359-368, 1999. [doi]

Low-power distributed arithmetic architectures using nonuniform memory partitioningSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. iscas 1999: 470-473 [doi]

A coding framework for low-power address and data bussesSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. tvlsi, 7(2):212-221, 1999. [doi]

Noise-tolerant dynamic circuit designLei Wang, Naresh R. Shanbhag. iscas 1999: 549-552 [doi]

1998

Energy-efficiency in presence of deep submicron noiseRajamohana Hegde, Naresh R. Shanbhag. iccad 1998: 228-234 [doi]

Decorrelating (DECOR) transformations for low-power adaptive filtersSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. islped 1998: 250-255 [doi]

Coding for Low-Power Address and Data Busses: A Source-Coding Framework and ApplicationsSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. vlsid 1998: 18-23

1997

1996

Low-power adaptive filter architectures via strength reductionManish Goel, Naresh R. Shanbhag. islped 1996: 217-220 [doi]

Lower bounds on power dissipation for DSP algorithmsNaresh R. Shanbhag. islped 1996: 43-48 [doi]

1995

Pipelined Adaptive IIR Filter ArchitectureNaresh R. Shanbhag, Gi-Hong Im. iscas 1995: 558-561

1993

A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding ApplicationsNaresh R. Shanbhag, Keshab K. Parhi. iscas 1993: 1956-1958

Roundoff error analysis of the pipelined ADPCM coderNaresh R. Shanbhag, Keshab K. Parhi. iscas 1993: 886-889