Pierre G. Paulin - researchr alias

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2010

A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoCSébastien Le Beux, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin. iscas 2010: 3613-3616 [doi]

Combining mapping and partitioning exploration for NoC-based embedded systemsSébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin. jsa, 56(7):223-232, 2010. [doi]

MpAssign: A framework for solving the many-core platform mapping problemYoucef Bouchebaba, Pierre G. Paulin, A. E. Ozcan, Bruno Lavigueur, Michel Langevin, Olivier Benny, Gabriela Nicolescu. rsp 2010: 1-7 [doi]

Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chipBruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin. rsp 2010: 1-9 [doi]

2009

Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia ApplicationsBruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur. vlsisp, 57(2):263-283, 2009. [doi]

2008

Multicore design is the challenge! what is the solution?Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne Wolf, Achim Nohl, Drew Wingard, Mike Muller. dac 2008: 128-130 [doi]

Reliable performance analysis of a multicore multithreaded system-on-chipSimon Schliecker, Mircea Negrean, Gabriela Nicolescu, Pierre G. Paulin, Rolf Ernst. codes 2008: 161-166 [doi]

2007

MPSoC memory optimization for digital camera applicationsYoucef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin. dsdm 2007: 424-427 [doi]

MPSoC memory optimization using program transformationYoucef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin. todaes, 12(4), 2007. [doi]

Two-level tiling for MPSoC architectureYoucef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu. asap 2007: 314-319 [doi]

Roundtable: Envisioning the Future for Multiprocessor SoCAhmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne Wolf. dt, 24(2):174-183, 2007. [doi]

Roundtable: Design and CAD Challenges for Leading-Edge Multimedia DesignsAndrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias. dt, 24(1):83-93, 2007. [doi]

A future of customizable processors: are we there yet?Laura Pozzi, Pierre G. Paulin. date 2007: 1224-1225 [doi]

2006

An Application Mapping Methodology and Case Study for Multi-Processor On-Chip ArchitecturesGiovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane. vlsi 2006: 146-151 [doi]

Application-Level Memory Optimization for MPSoCBruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur. rsp 2006: 169-178 [doi]

Parallel programming models for a multiprocessor SoC platform applied to networking and multimediaPierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, V. Gagne, Gabriela Nicolescu. tvlsi, 14(7):667-680, 2006. [doi]

Distributed object models for multi-processor SoC s, with application to low-power multimedia wireless systemsPierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo. date 2006: 482-487 [doi]

2004

System level design: six success stories in search of an industryFrancine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane. dac 2004: 349-350 [doi]

Designing High Quality, Scaleable SoC??s with Heterogeneous ComponentsPierre G. Paulin. isqed 2004: 325 [doi]

Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia ApplicationPierre G. Paulin. dsdm 2004: 2-4 [doi]

Application of a Multi-Processor SoC Platform to High-Speed Packet ForwardingPierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard. date 2004: 58-63 [doi]

DATE Panel: Chips of the Future: Soft, Crunchy or Hard?Pierre G. Paulin. date 2004: 844-851 [doi]

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic managementPierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu. codes 2004: 48-53 [doi]

2003

System-on-chip beyond the nanometer wallPhilippe Magarshack, Pierre G. Paulin. dac 2003: 419-424 [doi]

Network Processing Challenges and an Experimental NPU PlatformPierre G. Paulin, Chuck Pilkington, Essaid Bensoudane. date 2003: 20064-20069 [doi]

2002

2001

Programming models for network processors (Panel)Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld. isss 2001: 202

Embedded systems technologies for application-specific architecture platformsPierre G. Paulin. isss 2001: 195

Network processors: a perspective on market requirements, processor architectures and embedded S/W toolsPierre G. Paulin, Faraydon Karim, Paul Bromley. date 2001: 420-429 [doi]

2000

The Future of Flexible HW Platform Architectures Panel DiscussionRolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers. date 2000: 634 [doi]

Towards Application-Specific Architecture Platforms: Embedded Systems Design Automation TechnologiesPierre G. Paulin. euromicro 2000: 1028 [doi]

1997

1996

Address Calculation for Retargetable Compilation and Exploration of Instruction-Set ArchitecturesClifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya. dac 1996: 597-600 [doi]

1995

1994

1993

Insulin: An Instruction Set Simulation EnvironmentShailesh Sutarwala, Pierre G. Paulin, Yatish Kumar. chdl 1993: 369-376

1991

Meta VHDL for Higher Level Controller Modeling and SynthesisAhmed Amine Jerraya, Pierre G. Paulin, Simon Curry. vlsi 1992: 215-224

1989

Scheduling and Binding Algorithms for High-Level SynthesisPierre G. Paulin, John P. Knight. dac 1989: 1-6 [doi]

Force-directed scheduling for the behavioral synthesis of ASICsPierre G. Paulin, John P. Knight. tcad, 8(6):661-679, 1989. [doi]

Horizontal Partitioning of PLA-based Finite State MachinesPierre G. Paulin. dac 1989: 333-338 [doi]

1987

Force-Directed Scheduling in Automatic Data Path SynthesisPierre G. Paulin, John P. Knight. dac 1987: 195-202 [doi]

1986

HAL: a multi-paradigm approach to automatic data path synthesisPierre G. Paulin, John P. Knight, Emil F. Girczyc. dac 1986: 263-270 [doi]