Andrzej Krasniewski - researchr alias

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Viewing Publication 1 - 39 from 39

2014

Rule Induction Based on Logic Synthesis MethodsGrzegorz Borowik, Andrzej Krasniewski, Tadeusz Luba. icseng 2015: 813-816 [doi]

2012

Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitchingJakub Korczyc, Andrzej Krasniewski. ddecs 2012: 171-174 [doi]

2011

Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAsGrzegorz Borowik, Andrzej Krasniewski. eurocast 2012: 327-334 [doi]

A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAsGrzegorz Borowik, Andrzej Krasniewski. icseng 2011: 488-489 [doi]

2008

Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAsAndrzej Krasniewski. ddecs 2008: 74-79 [doi]

Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAsAndrzej Krasniewski. mam, 32(5-6):303-312, 2008. [doi]

Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAsAndrzej Krasniewski. dsd 2008: 250-255 [doi]

2007

Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAsAndrzej Krasniewski. dsdm 2007: 579-586 [doi]

2006

Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAsAndrzej Krasniewski. ddecs 2006: 180-185

2005

A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded MemoryAndrzej Krasniewski. iolts 2005: 197-198 [doi]

2004

Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAsAndrzej Krasniewski. dft 2004: 487-495 [doi]

Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded MemoryAndrzej Krasniewski. fpl 2004: 1067-1072 [doi]

Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory BlocksAndrzej Krasniewski. iolts 2004: 67-72 [doi]

2003

Evaluation of Testability of Path Delay Faults for User-Configured Programmable DevicesAndrzej Krasniewski. fpl 2003: 828-838 [doi]

Evaluation of the Quality of Testing Path Delay Faults under Restricted Input AssumptionAndrzej Krasniewski. iolts 2003: 168 [doi]

Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAsAndrzej Krasniewski. jsa, 49(4-6):283-296, 2003. [doi]

2002

On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAsAndrzej Krasniewski. fpl 2002: 596-606 [doi]

Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAsAndrzej Krasniewski. fpl 2002: 616-626 [doi]

2001

Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA TestingAndrzej Krasniewski. dsdm 2001: 310-317 [doi]

Testing FPGA Delay Faults in the System Environment is Very Different from Ordinary Delay Fault TestingAndrzej Krasniewski. iolts 2001: 37 [doi]

2000

Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAsAndrzej Krasniewski. fpl 2000: 675-684 [doi]

Self-Testing of FPGA Delay Faults in the System EnvironmentAndrzej Krasniewski. iolts 2000: 40 [doi]

1999

Application-Dependent Testing of FPGA Delay FaultsAndrzej Krasniewski. euromicro 1999: 1260-1267 [doi]

Self-Testing of S-Compatible Test Units in User-Programmed FPGAsPawel Tomaszewicz, Andrzej Krasniewski. euromicro 1999: 1254-1259 [doi]

1996

Design of Dependable Hardware: What BIST is most Efficient?Andrzej Krasniewski. edcc 1996: 233-245

1994

Coverage of Delay Faults: When 13 and 99 Mean the SameAndrzej Krasniewski, Leszek B. Wronski. edcc 1994: 178-195

Tests for path delay faults vs. tests for gate delay faults: how different they areAndrzej Krasniewski, Leszek B. Wronski. eurodac 1994: 310-315 [doi]

1992

High Quality Testing of Embedded RAMs Using Circular Self-Test PathAndrzej Krasniewski, Slawomir Pilarski. itc 1992: 652-661

Estimating testing effectiveness of the circular self-test path techniqueSlawomir Pilarski, Andrzej Krasniewski, Tiko Kameda. tcad, 11(10):1301-1316, 1992. [doi]

Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space ExpansionXiaodong Xie, Alexander Albicki, Andrzej Krasniewski. iccd 1992: 482-485

1991

Logic Synthesis for Efficient Pseudoexhaustive TestabilityAndrzej Krasniewski. dac 1991: 66-72 [doi]

Random Testability of Redundant CircuitsAndrzej Krasniewski, Alexander Albicki. iccd 1991: 424-427

Can Redundancy Enhance Testability?Andrzej Krasniewski. itc 1991: 483-491

1990

Design for verification testabilityAndrzej Krasniewski. eurodac 1990: 644-648 [doi]

1989

Circular self-test path: a low-cost BIST technique for VLSI circuitsAndrzej Krasniewski, Slawomir Pilarski. tcad, 8(1):46-55, 1989. [doi]

1987

Circular Self-Test Path: A Low-Cost BIST TechniqueAndrzej Krasniewski, Slawomir Pilarski. dac 1987: 407-415 [doi]

1985

Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applicationsAndrzej Krasniewski, Alexander Albicki. dac 1985: 808-811 [doi]

Automatic Design of Exhaustively Self-Testing Chips with Bilbo ModulesAndrzej Krasniewski, Alexander Albicki. itc 1985: 362-371

1984

Fuzzy Automata as Adaptive Algorithms for Telephone Traffic RoutingAndrzej Krasniewski. icc 1984: 61-66

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