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2006

14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, TaiwanIEEE Computer Society, 2006.

Forewordmtdt 2006: [doi]

Organizing Committeemtdt 2006: [doi]

Program Committeemtdt 2006: [doi]

Reviewersmtdt 2006: [doi]

High-Quality Memory TestMohamed Azimane. mtdt 2006: [doi]

A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static FaultsT. A. Gyonjyan, Gurgen Harutunyan, Valery A. Vardanian. mtdt 2006: 9-14 [doi]

Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia CodingShen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng. mtdt 2006: 34-42 [doi]

Future Prospective of Programmable Logic Non-volatile DeviceCharles Hsu. mtdt 2006: [doi]

Fault-Pattern Oriented Defect Diagnosis for Flash MemoryMu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu. mtdt 2006: 3-8 [doi]

Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash MemoryVictor Chao-Wei Kuo, Chih-Ming Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, Liang-Tai Kuo, Shi-Hsien Chen, Houng-Chi Wei, Hann-Ping Hwang, Saysamone Pittikoun. mtdt 2006: 77-79 [doi]

SRAM Cell Current in Low Leakage DesignDing-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou. mtdt 2006: 65-70 [doi]

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal AssignmentDing-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu. mtdt 2006: 28-33 [doi]

SRAM Design Techniques for Sub-nano CMOS TechnologyJordan Lai. mtdt 2006: [doi]

Improved Representatives for Unrepairability Judging and Economic Repair Solutions of MemoriesHsing-Chung Liang, Le-Quen Tzeng. mtdt 2006: 15 [doi]

A New 1T DRAM Cell With Enhanced Floating Body EfJyi-Tsong Lin, Mike Chang. mtdt 2006: 23-27 [doi]

Non-volatile Semiconductor Memory Technology in Nanotech EraChih-Yuan Lu. mtdt 2006: [doi]

New on-Chip DFT and ATE Features for Efficient Embedded Memory TestPeter Muhmenthaler. mtdt 2006: [doi]

DRAM Industry TrendPei-Lin Pai. mtdt 2006: [doi]

Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability TestsMohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev. mtdt 2006: 55-64 [doi]

MRAM Write Error Categorization with QCKBYuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa. mtdt 2006: 43-48 [doi]

Roadmap of the Flash MemoryRiichiro Shirota. mtdt 2006: [doi]

DDR2 DRAM Output Timing OptimizationJörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson. mtdt 2006: 49-54 [doi]

On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM componentsHua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene. mtdt 2006: 71-76 [doi]

Comparison of Electrical and Reliability Characteristics of Different Tunnel Oxides in SONOS Flash MemoryJia-Lin Wu, Hua-Ching Chien, Chien-Wei Liao, Cheng-Yen Wu, Chih-Yuan Lee, Houng-Chi Wei, Shih-Hsien Chen, Hann-Ping Hwang, Saysamone Pittikoun, Travis Cho, Chin-Hsing Kao. mtdt 2006: 80-84 [doi]

2005

13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, TaiwanIEEE Computer Society, 2005.

A programmable built-in self-test for embedded DRAMsShibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya. mtdt 2005: 58-63 [doi]

A novel CMOS compatible embedded nonvolatile memory with zero process adderMatthew J. Breitwisch, Chung Hon Lam, Jeffrey B. Johnson, Steven W. Mittl, Jian W. Zhu. mtdt 2005: 9-12 [doi]

Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding techniqueMeng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai. mtdt 2005: 16-21 [doi]

A low-power SRAM design using quiet-bitline architectureShin-Pao Cheng, Shi-Yu Huang. mtdt 2005: 135-139 [doi]

Full-speed field programmable memory BIST supporting multi-level loopingXiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy. mtdt 2005: 67-71 [doi]

Impact of stresses on the fault coverage of memory testsSaid Hamdioui, Zaid Al-Ars, Ad J. Van de Goor, Rob Wadsworth. mtdt 2005: 103-108 [doi]

Measurement and characterization of 6T SRAM cell currentChing-Hua Hsiao, Ding-Ming Kwai. mtdt 2005: 140-145 [doi]

Distributed data-retention power gating techniques for column and row co-controlled embedded SRAMChung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang. mtdt 2005: 129-134 [doi]

DFT techniques for memory macro with built-in ECCKeiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama. mtdt 2005: 109-114 [doi]

Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memoryKung-Hong Lee, Shih-Chen Wang, Ya-Chin King. mtdt 2005: 3-8 [doi]

DFT architecture for a dynamic fault model of the embedded mask ROM of SOCYang-Han Lee, Yih-Guang Jan, Jei-Jung Shen, Shian-Wei Tzeng, Ming-Hsueh Chuang, Jheng-Yao Lin. mtdt 2005: 78-82 [doi]

Dielectric tunnel parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM applicationsSimon C. Li, J. P. Su, T. H. Wu, J. M. Lee, M. F. Shu. mtdt 2005: 29-34 [doi]

An error detection and correction scheme for RAMs with partial-write functionJin-Fu Li, Yu-Jane Huang. mtdt 2005: 115-120 [doi]

Embedded OTP fuse in CMOS logic processChing-Yuan Lin, Chung-Hung Lin, Chien-Hung Ho, Wei-Wu Liao, Shu-Yueh Lee, Ming-Chou Ho, Shih-Chen Wang, Shih-Chan Huang, Yuan-Tai Lin, Charles Ching-Hsiang Hsu. mtdt 2005: 13-15 [doi]

A BIRA algorithm for embedded memories with 2D redundancyShyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang. mtdt 2005: 121-126 [doi]

Advanced simulation technology and its application in memory design and verificationBruce McGaughy, S. Wünsche, K. K. Hung. mtdt 2005: [doi]

Zero capacitor embedded memory technology for system on chipSerguei Okhonin, Pierre Fazan, Mark-Eric Jones. mtdt 2005: [doi]

An investigation into three-level ferroelectric memoryKamlesh R. Raiter, Bruce F. Cockburn. mtdt 2005: 38-43 [doi]

A high speed BIST architecture for DDR-SDRAM testingSheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee. mtdt 2005: 52-57 [doi]

Software based in-system memory test for highly available systemsAmandeep Singh, Debashish Bose, Sandeep Darisala. mtdt 2005: 89-94 [doi]

A nor-type MLC ROM with novel sensing scheme for embedded applicationsStar Sung, Thomas Chang, Juei Lung Chen. mtdt 2005: 22-25 [doi]

FSM-based programmable memory BIST with macro commandPo-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang. mtdt 2005: 72-77 [doi]

A complete memory address generator for scan based March algorithmsWei-Lun Wang, Kuen-Jong Lee. mtdt 2005: 83-88 [doi]

Reliability enhancement of CMOS SRAMsChin-Long Wey, Meng-Yao Liu, Shaolei Quan. mtdt 2005: 146-151 [doi]

A novel single poly-silicon EEPROM using trench floating gateMeng-Yi Wu, Shin-Chang Feng, Ya-Chin King. mtdt 2005: 35-37 [doi]

A systematic approach to reducing semiconductor memory test time in mass productionJen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen. mtdt 2005: 97-102 [doi]

2004

12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USAIEEE Computer Society, 2004.

An Integrated Memory Self Test and EDA SolutionR. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald. mtdt 2004: 92-95 [doi]

A BIST Algorithm for Bit/Group Write Enable Faults in SRAMsSaman Adham, Benoit Nadeau-Dostie. mtdt 2004: 98-101 [doi]

Redundancy & It s Not Just for Defects AnymoreRobert C. Aitken. mtdt 2004: 117-120 [doi]

Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache DesignAdil Akaaboune, Nazeih Botros, Jaafar Alghazo. mtdt 2004: 13-18 [doi]

Influence of Bit Line Twisting on the Faulty Behavior of DRAMsZaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor. mtdt 2004: 32-37 [doi]

SF-LRU Cache Replacement AlgorithmJaafar Alghazo, Adil Akaaboune, Nazeih Botros. mtdt 2004: 19-24 [doi]

A Novel Method for Silicon Configurable Test Flow and Algorithms for Testing, Debugging and Characterizing Different Types of Embedded Memories through a Shared ControllerSwapnil Bahl. mtdt 2004: 78-83 [doi]

Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access MemoryBruce F. Cockburn. mtdt 2004: 46-51 [doi]

A Parallel Built-in Diagnostic Scheme for Multiple Embedded MemoriesLi-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu. mtdt 2004: 65-69 [doi]

Embedded Memory Reliability: The SER ChallengeN. Derhacobian, Valery A. Vardanian, Yervant Zorian. mtdt 2004: 104-110 [doi]

The State-of-Art and Future Trends in Testing Embedded MemoriesSaid Hamdioui, Georgi Gaydadjiev, A. J. van de Goor. mtdt 2004: 54-59 [doi]

Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMsShyue-Kung Lu, Shih-Chang Huang. mtdt 2004: 60-64 [doi]

Fast Error-Correcting Circuits for Fault-Tolerant MemoryElaine Ou, Woodward Yang. mtdt 2004: 8-12 [doi]

Markov Models of Fault-Tolerant Memory Systems under SEULuca Schiano, Marco Ottavi, Fabrizio Lombardi. mtdt 2004: 38-43 [doi]

A Programmable Built-in Self-Diagnosis for Embedded SRAMCarolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa, Stefano Corbani, Giovanni Mastrodomenico, Lara Albani. mtdt 2004: 84-89 [doi]

Do We Need Anything More Than Single Bit Error Correction (ECC)?Michael Spica, T. M. Mak. mtdt 2004: 111-116 [doi]

The Effectiveness of the Scan Test and Its New VariantsA. J. van de Goor, Said Hamdioui, Zaid Al-Ars. mtdt 2004: 26-31 [doi]

Micro Programmable Built-In Self Repair for SRAMsRita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli, M. Crestan, Giovanni Mastrodomenico, Lara Albani. mtdt 2004: 72-77 [doi]

2003

11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USAIEEE Computer Society, 2003.

Applying Defect-Based Test to Embedded Memories in a COT ModelRobert C. Aitken. mtdt 2003: 72 [doi]

Systematic Memory Test Generation for DRAM Defects Causing Two Floating NodesZaid Al-Ars, A. J. van de Goor. mtdt 2003: 27-32 [doi]

A Fault Primitive Based Analysis of Linked Faults in RAMsZaid Al-Ars, Said Hamdioui, A. J. van de Goor. mtdt 2003: 33 [doi]

ITRS Commodity Memory RoadmapRoger Barth. mtdt 2003: 61-63 [doi]

Optimal Spare Utilization in Repairable and Reliable Memory CoresMinsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri. mtdt 2003: 64-71 [doi]

A Multilevel DRAM with Hierarchical Bitlines and Serial SensingBruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott. mtdt 2003: 14-19 [doi]

A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded ApplicationsJean Michel Daga, Caroline Papaix, Emmanuel Racape, Marylene Combe, Vincent Sialelli, Jeanine Guichaoua. mtdt 2003: 81-85 [doi]

A Testability-Driven Optimizer and Wrapper Generator for Embedded MemoriesRei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li. mtdt 2003: 53 [doi]

Application Specific DRAMs TodayBetty Prince. mtdt 2003: 7-13 [doi]

An Electrical Simulation Model for the Chalcogenide Phase-Change Memory CellDaniel Salamon, Bruce F. Cockburn. mtdt 2003: 86 [doi]

Output Timing Measurement Using an Idd MethodJörg E. Vollrath. mtdt 2003: 43-46 [doi]

Reducing Test Time of Embedded SRAMsBaosheng Wang, Josh Yang, André Ivanov. mtdt 2003: 47-52 [doi]

Cost Optimum Embedded DRAM Design by Yield AnalysisYouhei Zenda, Koji Nakamae, Hiromu Fujioka. mtdt 2003: 20 [doi]

2002

10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, FranceIEEE Computer Society, 2002.

The YATE Fail-Safe Interface: The User s Point of ViewD. Bied-Charreton, D. Guillon, B. Jacques. mtdt 2002: 39-43 [doi]

High Speed 15 ns 4 Mbits SRAM for Space ApplicationBernard Coloma, Patrick Delaunay, Olivier Husson. mtdt 2002: 32-38 [doi]

Design and Test of a 9-port SRAM for a 100Gb/s STS-1 SwitchRobert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu. mtdt 2002: 83 [doi]

Adder Merged DRAM ArchitectureMasashi Hashimoto. mtdt 2002: 88-94 [doi]

Defect-Oriented Analysis of Memory BIST TestsAlvin Jee. mtdt 2002: 7-11 [doi]

Embedded Memory Test and RepairA. Kablanian. mtdt 2002:

Decreasing EEPROM Programming Bias With Negative Voltage, Reliability ImpactR. Laffont, J. Razafindramora, P. Canet, Rachid Bouchakour, J. M. Mirabel. mtdt 2002: 168-176 [doi]

SoC s Trends and Challenges going to 0.10µmPhilippe Magarshack. mtdt 2002:

Fault Tolerant Insertion and Verification: A Case StudyAlberto Manzone, Diego De Costantini. mtdt 2002: 44-48 [doi]

A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile MemoriesCaroline Papaix, Jean Michel Daga. mtdt 2002: 149-156 [doi]

A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy ScenariosEmmanuel Rondey, Yann Tellier, Simone Borri. mtdt 2002: 57-61 [doi]

Challenges and Opportunities Created by the SoC ShockwaveM. Templeton. mtdt 2002:

A Fault Modeling Technique to Test Memory BIST AlgorithmsRaja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla. mtdt 2002: 109-116 [doi]

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