Table of Contents

• ReflectionsLaura Chizuko Fujino. 4 [doi]
• Foreword: Silicon systems for the Internet of EverythingKevin Zhang. 5 [doi]
• Session 1 overview: Plenary sessionAnantha Chandrakasan, Kevin Zhang. 6-7 [doi]
• 1.1 Moore's law: A path going forwardWilliam M. Holt. 8-13 [doi]
• 1.2 Three pillars enabling the Internet of Everything: Smart everyday objects, information-centric networks, and automated real-time insightsSophie V. Vandebroek. 14-20 [doi]
• 1.3 Evolution of 5G mobile technology toward 1 2020 and beyondSeizo Onoe. 23-28 [doi]
• 1.4 The road ahead for securely-connected carsLars Reger. 29-33 [doi]
• Session 2 overview: RF frequency synthesis techniquesAhmad Mirzaei, Hyunchol Shin. 34-35 [doi]
• 2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOSYan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang 0002, Theodore Reck, Huan-Neng Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang. 36-37 [doi]
• 2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arraysAbhishek Agrawal, Arun Natarajan. 38-39 [doi]
• 2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLLZhiqiang Huang, Bingwei Jiang, Lianming Li, Howard Cam Luong. 40-41 [doi]
• 2.4 A 2-to-16GHz BiCMOS ΔΣ fractional-N PLL synthesizer with integrated VCOs and frequency doubler for wireless backhaul applicationsTino Copani, Claudio Asero, Matteo Colombo, Paolo Aliberti, Giuseppe Martino, Francesco Clerici. 42-43 [doi]
• 2.5 A complementary VCO for IoE that achieves a 195dBc/Hz FOM and flicker noise corner of 200kHzDavid Murphy, Hooman Darabi. 44-45 [doi]
• 2.6 A 190.5GHz mode-switching VCO with 20.7% continuous tuning range and maximum power of -2.1dBm in 0.13µm BiCMOSRouzbeh Kananizadeh, Omeed Momeni. 46-47 [doi]
• 2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise cornerJun Yin, Pui-In Mak, Franco Maloberti, Rui Paulo Martins. 48-49 [doi]
• 2.8 A mixed-mode injection frequency-locked loop for self-calibration of injection locking range and phase noise in 0.13µm CMOSDongseok Shin, Sanjay Raman, Kwang-Jin Koh. 50-51 [doi]
• 2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOSSebastian Sievert, Ofir B. Degani, Assaf Ben Bassat, Rotem Banin, Ashoke Ravi, Bernd-Ulrich Klepser, Zdravko Boos, Doris Schmitt-Landsiedel. 52-54 [doi]
• Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient linksHyeon-Min Bae, Ajith Amerasekera. 54-55 [doi]
• 3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOISergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli. 56-57 [doi]
• 3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOSDelong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo-Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao. 58-59 [doi]
• 3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOSTakayasu Norimatsu, Takashi Kawamoto, Kenji Kogo, Naohiro Kohmu, Fumio Yuki, Norio Nakajima, Takashi Muto, Junya Nasu, Takemasa Komori, Hideki Koba, Tatsunori Usugi, Tomofumi Hokari, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Masatoshi Tsuge, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta. 60-61 [doi]
• 3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOSKarthik Gopalakrishnan, Alan Ren, Amber Tan, Arash Farhood, Arun Tiruvur, Belal Helal, Chang-Feng Loi, Chris Jiang, Halil Cirit, Irene Quek, Jamal Riani, James Gorecki, Jennifer Wu, Jorge Pernillo, Lawrence Tse, Michael Le, Mohammad Ranjbar, Pui-Shan Wong, Pulkit Khandelwal, Rajesh Narayanan, Ravindran Mohanavelu, Sameer Herlekar, Sudeep Bhoja, Vlad Shvydun. 62-63 [doi]
• 3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOSTakayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura. 64-65 [doi]
• 3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOIMatteo Bassi, Francesco Radice, Melchiorre Bruccoleri, Simone Erba, Andrea Mazzanti. 66-67 [doi]
• 3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFETYohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang. 68-70 [doi]
• Session 4 overview: Digital processorsMahesh Mehendale, Luke Shin. 70-71 [doi]
• 4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performanceEyal Fayneh, Marcelo Yuffe, Ernest Knoll, Michael Zelikson, Muhammad Abozaed, Yair Talker, Ziv Shmuely, Saher Abu Rahme. 72-73 [doi]
• 4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power managementAaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger. 74-75 [doi]
• 4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performanceHugh Mair, Gordon Gammie, Alice Wang, Rolf Lagerquist, C. J. Chung, Sumanth Gururajarao, Ping Kao, Anand Rajagopalan, Anirban Saha, Amit Jain, Ericbill Wang, Shichin Ouyang, Huajun Wen, Achuta Thippana, HsinChen Chen, Syed Rahman, Minh Chau, Anshul Varma, Brian Flachs, Mark Peng, Alfred Tsai, Vincent Lin, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko. 76-77 [doi]
• 4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systemsSeiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori. 78-79 [doi]
• 4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliabilityChikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita. 80-81 [doi]
• 4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor clusterMichael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini. 82-83 [doi]
• 4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logicYongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Chien-Chen Lin, Qi Wei, Yu Wang, Ya-Chin King, Chrong Jung Lin, Pedram Khalili, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang. 84-86 [doi]
• Session 5 overview: Analog techniquesMarco Berkhout, Tim Piessens. 86-87 [doi]
• 5.1 A 10MHz-bandwidth 4µs-large-signal-settling 6.5nV/√Hz-noise 2µV-offset chopper operational amplifierVadim Ivanov, Munaf Shaik. 88-89 [doi]
• 5.2 A 118dB-PSRR 0.00067%(-103.5dB) THD+N and 3.1W fully differential class-D audio amplifier with PWM common-mode controlWen-Chieh Wang, Yu-Hsin Lin. 90-91 [doi]
• 5.3 A 2×70W monolithic five-level Class-D audio power amplifierMikkel Hoyerby, Jorgen Kragh Jakobsen, Jesper Midtgaard, Thomas Holm Hansen, Allan Nogueras Nielsen, Hans Hasselby-Andersen. 92-93 [doi]
• 5.4 A sub-µW 36nV/√Hz chopper amplifier for sensors using a noise-efficient inverter-based 0.2V-supply input stageFrank M. Yaul, Anantha P. Chandrakasan. 94-95 [doi]
• 5.5 A 2µW 40mVpp linear-input-range chopper- stabilized bio-signal amplifier with boosted input impedance of 300MΩ and electrode-offset filteringHariprasad Chandrakumar, Dejan Markovic. 96-97 [doi]
• 5.6 A 420µW 100GHz-GBW CMOS Programmable-Gain Amplifier leveraging the cross-coupled pair regenerationMarco Sautto, Fabio Quaglia, Giulio Ricotti, Andrea Mazzanti. 98-99 [doi]
• 5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltageShunta Iguchi, Takayasu Sakurai, Makoto Takamiya. 100-101 [doi]
• 5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor schemeTae-Kwang Jang, Myungjoon Choi, Seokhyeon Jeong, Suyoung Bang, Dennis Sylvester, David Blaauw. 102-103 [doi]
• 5.9 A 24MHz crystal oscillator with robust fast start-up using dithered injectionDanielle Griffith, James Murdock, Per Torstein Røine. 104-105 [doi]
• 5.10 A 1.4V 10.5MHz swing-boosted differential relaxation oscillator with 162.1dBc/Hz FOM and 9.86psrms period jitter in 0.18µm CMOSJunghyup Lee, Arup K. George, Minkyu Je. 106-108 [doi]
• Session 6 overview: Image sensorsJun Deguchi, David Stoppa. 108-109 [doi]
• 6.1 An over 120dB simultaneous-capture wide-dynamic-range 1.6e- ultra-low-reset-noise organic-photoconductive-film CMOS image sensorKazuko Nishimura, Yoshihiro Sato, Junji Hirase, Ryota Sakaida, Masaaki Yanagida, Tokuhiko Tamaki, Masayuki Takase, Hidenari Kanehara, Masashi Murakami, Yasunori Inoue. 110-111 [doi]
• 6.2 210ke- Saturation signal 3µm-pixel variable-sensitivity global-shutter organic photoconductive image sensor for motion captureSanshiro Shishido, Yasuo Miyake, Yoshiaki Sato, Tokuhiko Tamaki, Naoki Shimasaki, Yoshihiro Sato, Masashi Murakami, Yasunori Inoue. 112-113 [doi]
• 6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applicationsJan Bogaerts, Raf Lafaille, Marc Borremans, Jia Guo, Bart Ceulemans, Guy Meynants, Navid Sarhangnejad, Gavril Arsinte, Victor Statescu, Sonja van der Groen. 114-115 [doi]
• 6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiersHirofumi Totsuka, Toshiki Tsuboi, Takashi Muto, Daisuke Yoshida, Yasushi Matsuno, Masanobu Ohmura, Hidekazu Takahashi, Katsuhito Sakurai, Takeshi Ichikawa, Hiroshi Yuzurihara, Shunsuke Inoue. 116-117 [doi]
• 6.5 A 64×64-pixel digital silicon photomultiplier direct ToF sensor with 100Mphotons/s/pixel background rejection and imaging/altimeter mode with 0.14% precision up to 6km for spacecraft navigation and landingMatteo Perenzoni, Daniele Perenzoni, David Stoppa. 118-119 [doi]
• 6.6 A 1280×720 single-photon-detecting image sensor with 100dB dynamic range using a sensitivity-boosting techniqueMitsuyoshi Mori, Yusuke Sakata, Manabu Usuda, Sejii Yamahira, Shigetaka Kasuga, Yutaka Hirose, Yoshihisa Kato, Tsuyoshi Tanaka. 120-121 [doi]
• 6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGAKei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura. 122-123 [doi]
• 6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate biasCharles Chih-Min Liu, Manoj M. Mhala, Chin-Hao Chang, Honyih Tu, Po-Sheng Chou, Calvin Chao, Fu-Lung Hsueh. 124-125 [doi]
• 6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital convertersToshiki Arai, Toshio Yasue, Kazuya Kitamura, Hiroshi Shimamoto, Tomohiko Kosugi, Sung-Wook Jun, Satoshi Aoyama, Ming-Chieh Hsu, Yuichiro Yamashita, Hirofumi Sumi, Shoji Kawahito. 126-128 [doi]
• Session 7 overview: Nonvolatile memory solutionsSungdae Choi, Jin-Man Han. 128-129 [doi]
• 7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layersDongku Kang, Woopyo Jeong, Chulbum Kim, Doo-Hyun Kim, Yong-Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doo-Gon Kim, Young-Sun Min, Moosung Kim, AnSoo Park, Jae-Ick Son, In-Mo Kim, Pansuk Kwak, Bong-Kil Jung, Doosub Lee, Hyunggon Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi. 130-131 [doi]
• 7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write schemeHiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura. 132-133 [doi]
• 7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applicationsWin-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, Sangbum Kim, Hsiang-Lam Lung, Chung Lam. 134-135 [doi]
• 7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cellChien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya-Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng-Fan Chang. 136-137 [doi]
• 7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rateSeungjae Lee, Jin-yub Lee, Il Han Park, Jong-Yeol Park, Sung-Won Yun, Minsu Kim, Jong-Hoon Lee, Min-Seok Kim, Kangbin Lee, Taeeun Kim, Byungkyu Cho, Dooho Cho, Sangbum Yun, Jung-No Im, Hyejin Yim, Kyung-hwa Kang, Suchang Jeon, Sungkyu Jo, Yang-Lo Ahn, Sung-Min Joe, Suyong Kim, Deok-kyun Woo, Jiyoon Park, Hyun Wook Park, Youngmin Kim, Jonghoon Park, Yongsu Choi, Makoto Hirano, Jeong-Don Ihm, Byunghoon Jeong, Seon-Kyoo Lee, Moosung Kim, Hokil Lee, Sungwhan Seo, Hongsoo Jeon, Chan Ho Kim, Hyunggon Kim, Jintae Kim, Yongsik Yim, Hoosung Kim, Dae-Seok Byeon, Hyang-Ja Yang, Ki Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi. 138-139 [doi]
• 7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°CHidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi. 140-141 [doi]
• 7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memoryTomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung-Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo. 142-144 [doi]
• Session 8 overview: Low-power digital circuitsEric Fluhr, Bing Sheu. 144-145 [doi]
• 8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D linksPascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos. 146-147 [doi]
• 8.2 Fully integrated low-drop-out regulator based on event-driven PI controlDoyun Kim, Mingoo Seok. 148-149 [doi]
• 8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processorsYong-Jin Lee, Min-Yong Jung, Shashank Singh, Tae-Hwang Kong, Dae-Yong Kim, Kwang Ho Kim, Sang-Ho Kim, Jae Jin Park, Ho-Jin Park, Gyu-Hyeong Cho. 150-151 [doi]
• 8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gatingMinki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James Tschanz, Muhammad M. Khellah, Vivek De. 152-153 [doi]
• 8.5 A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systemsWanyeong Jung, Junhua Gu, Paul D. Myers, Minseob Shim, Seokhyeon Jeong, Kaiyuan Yang, Myungjoon Choi, Zhiyoong Foo, Suyoung Bang, Sechang Oh, Dennis Sylvester, David Blaauw. 154-155 [doi]
• 8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiringJohn M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally. 156-157 [doi]
• 8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chipsBohdan Karpinskyy, Yongki Lee, Yunhyeok Choi, YongSoo Kim, Mijung Noh, Sanghyun Lee. 158-160 [doi]
• 8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processorYiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David Blaauw, Dennis Sylvester. 160-162 [doi]
• Session 9 overview: High-performance wirelessAli Afsahi, Guang-Kaai Dehng. 162-163 [doi]
• 9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidthNikolaus Klemmer, S. Akhtar, V. Srinivasan, P. Litmanen, Himanshu Arora, Satish Uppathil, Scott Kaylor, A. Akour, V. Wang, M. Fares, F. Dulger, A. Frank, D. Ghosh, S. Madhavapeddi, H. Safiri, J. Mehta, A. Jain, H. Choo, E. Zhang, Charles K. Sestok, C. Fernando, Rajagopal K. A., S. Ramakrishnan, V. Sinari, V. Baireddy. 164-165 [doi]
• 9.2 A scalable 0.1-to-1.7GHz spatio-spectral-filtering 4-element MIMO receiver array with spatial notch suppression enabling digital beamformingLinxiao Zhang, Arun Natarajan, Harish Krishnaswamy. 166-167 [doi]
• 9.3 A very-low-noise frequency-translational quadrature-hybrid receiver for carrier aggregationJianxun Zhu, Peter R. Kinget. 168-169 [doi]
• 9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelationRenaldi Winoto, Ashkan Olyaei, Mohammad Hajirostam, Wai Lau, Xiang Gao, Arnab Mitra, Ovidiu Carnu, Philip Godoy, Luns Tee, Hao Li, Erdem Erdogan, Alden Wong, Qiang Zhu 0002, Timothy Loo, Fan Zhang, Liwei Sheng, Donghong Cui, Anuranjan Jha, Xiang Li, Wanghua Wu, Kun-Seok Lee, Derek Cheung, Ka Wo Pang, Haisong Wang, Jiexi Liu, Xingliang Zhao, Daibashish Gangopadhyay, David Cousinard, Arvind Anumula Paramanandam, Xiaoang Li, Norman Liu, Weiwei Xu, Yuan Fang, Xiaoyue Wang, Randy Tsang, Li Lin. 170-171 [doi]
• 9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOSZhiming Deng, Eric Lu, Edris Rostami, Dai Sieh, Dimitris Papadopoulos, Bryan Huang, Ray Chen, Hua Wang, W. H. Hsu, C. H. Wu, Osama Shanaa. 172-173 [doi]
• 9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOSXiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin. 174-175 [doi]
• 9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLLNereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx. 176-177 [doi]
• 9.8 Receiver with integrated magnetic-free N-path-filter-based non-reciprocal circulator and baseband self-interference cancellation for full-duplex wirelessJin Zhou, Negar Reiskarimian, Harish Krishnaswamy. 178-180 [doi]
• Session 10 overview: Advanced wireline transceivers and PLLsJaeha Kim, Roberto Nonis. 180-181 [doi]
• 10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOSAmin Shokrollahi, Dario Carnelli, John Fox, Klaas Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh. 182-183 [doi]
• 10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interfaceWei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang. 184-185 [doi]
• 10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOSHui Pan, Junhua Tan, Evelyn Wenting Wang, Jingguang Wang, Karthik Swaminathan, Ramalingam Pandarinathan, Ramesh Pasagadugula, VamshiKrishna Yakkala, Mostafa Hammad, Karim Abdelhalim, Kaijun Li, Su Cui, Jing Wang, Ahmad Chini, Mehmet Tazebay, Suresh Venkatesan, Derek Tam, Ichiro Fujimori, Kambiz Vakilian. 186-187 [doi]
• 10.4 A 12Gb/s 0.9mW/Gb/s wide-bandwidth injection-type CDR in 28nm CMOS with reference-free frequency captureTakashi Masuda, Ryota Shinoda, Jeremy Chatwin, Jacob Wysocki, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Zhiwei Zhou, Hideyuki Matsumoto, Hideyuki Suzuki, Norio Shoji. 188-189 [doi]
• 10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOSCheng-Ru Ho, Mike Shuo-Wei Chen. 190-191 [doi]
• 10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOSAhmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu. 192-193 [doi]
• 10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detectorSeojin Choi, Seyeon Yoo, Jaehyouk Choi. 194-195 [doi]
• 10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOsMark A. Ferriss, Bodhisatwa Sadhu, Alexander Rylyakov, Herschel A. Ainspan, Daniel J. Friedman. 196-198 [doi]
• Session 11 overview: Sensors and displaysYong Ping Xu, Joseph Shor. 198-199 [doi]
• 11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2Meisam Heidarpour Roshan, Samira Zali Asl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Sudhakar Pamarti, Joseph C. Doll, Nicholas Miller, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon. 200-201 [doi]
• 11.2 3D ultrasonic fingerprint sensor-on-a-chipHao-Yen Tang, Yipeng Lu, Fari Assaderagh, Mike Daneman, Xiaoyue Jiang, Martin Lim, Xi Li, Eldwin Ng, Utkarsh Singhal, Julius M. Tsai, David A. Horsley, Bernhard E. Boser. 202-203 [doi]
• 11.3 A hybrid multipath CMOS magnetic sensor with 210µTrms resolution and 3MHz bandwidth for contactless current sensingJunfeng Jiang, Kofi A. A. Makinwa. 204-205 [doi]
• 11.4 1650µm2 thermal-diffusivity sensors with inaccuracies down to ±0.75°C in 40nm CMOSUgur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa. 206-207 [doi]
• 11.5 A 3.2×1.5×0.8mm3 240nA 1.25-to-5.5V 32kHz-DTCXO RTC module with an overall accuracy of µ1ppm and an all-digital 0.1ppm compensation-resolution scheme at 1HzDavid Ruffieux, Franz-Xaver Pengg, Nicola Scolari, Frédéric Giroud, Daniel Séverac, Thanh Le, Silvio Dalla Piazza, Olivier Aubry. 208-209 [doi]
• 11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20VppJun-Eun Park, Jiheon Park, Young Ha Hwang, Jonghyun Oh, Deog Kyoon Jeong. 210-211 [doi]
• 11.7 A load-aware pre-emphasis column driver with 27% settling-time reduction in ±18% panel-load RC delay variation for 240Hz UHD flat-panel displaysJun-Suk Bang, Hyunsik Kim, Kye-Seok Yoon, Sang-Han Lee, Se-Hong Park, Ohjo Kwon, Choongsun Shin, Seonki Kim, Gyu-Hyeong Cho. 212-213 [doi]
• 11.8 Chip-scale electro-optical 3D FMCW lidar with 8µm ranging precisionBehnam Behroozpour, Phillip A. M. Sandborn, Niels Quack, Tae Joon Seok, Yasuhiro Matsui, Ming C. Wu, Bernhard E. Boser. 214-216 [doi]
• Session 12 overview: Efficient Power ConversionVadim Ivanov, Jaejin Park. 216-217 [doi]
• 12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedbackWanyeong Jung, Dennis Sylvester, David Blaauw. 218-219 [doi]
• 12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistributionNicolas Butzen, Michiel Steyaert. 220-221 [doi]
• 12.3 A 2-output step-up/step-down switched-capacitor DC-DC converter with 95.8% peak efficiency and 0.85-to-3.6V input voltage rangeChen Kong Teh, Atsushi Suzuki. 222-223 [doi]
• 12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiencyDaniel Lutz, Peter Renz, Bernhard Wicht. 224-225 [doi]
• 12.5 A 2MHz 12-to-100V 90%-efficiency self-balancing ZVS three-level DC-DC regulator with constant-frequency AOT V2 control and 5ns ZVS turn-on delayJing Xue, Hoi Lee. 226-227 [doi]
• 12.6 Capacitor-current-sensor calibration technique and application in a 4-phase buck converter with load-transient optimizationSzu-Yu Huang, Kuan-Yu Fang, Yi-Wei Huang, Shih-Hsiung Chien, Tai-Haur Kuo. 228-229 [doi]
• 12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolutionHsiang-An Yang, Wen-Hau Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Shin-Chi Lai. 230-231 [doi]
• 12.8 Synchronized floating current mirror for maximum LED utilization in multiple-string linear LED driversJunsik Kim, Shihong Park. 232-233 [doi]
• 12.9 A flying-domain DC-DC converter powering a Cortex-M0 processor with 90.8% efficiencyLoai G. Salem, John G. Louie, Patrick P. Mercier. 234-236 [doi]
• Session 13 overview: Wireless systemsYuu Watanabe, Pierre Busson. 236-237 [doi]
• 13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applicationsHwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son, Jaeha Kim. 238-239 [doi]
• 13.2 A Ku-band 260mW FMCW synthetic aperture radar TRX with 1.48GHz BW in 65nm CMOS for micro-UAVsYong Wang, Kai Tang, Ying Zhang, Liheng Lou, Bo Chen, Supeng Liu, Lei Qiu, Yuanjin Zheng. 240-241 [doi]
• 13.3 A 56Gb/s W-band CMOS wireless transceiverKorkut Kaan Tokgoz, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Jun Emmei, Masato Dome, Hisashi Kato, Jian Pang, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Yuuki Seo, Kimsrun Lim, Shinji Sato, Li Ning, Kengo Nakata, Kenichi Okada, Akira Matsuzawa. 242-243 [doi]
• 13.4 A microwave injection-locking outphasing modulator with 30dB dynamic range and 22% system efficiency in 45nm CMOS SOIMohammad Sadegh Mehrjoo, James F. Buckwalter. 244-245 [doi]
• 13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOSGiovanni Mangraviti, Khaled Khalaf, Qixian Shi, Kristof Vaesen, Davide Guermandi, Vito Giannini, Steven Brebels, Fortunato Frazzica, André Bourdoux, Charlotte Soens, Wim Van Thillo, Piet Wambacq. 246-247 [doi]
• 13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ayRui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. 248-249 [doi]
• 13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noisePedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx. 250-252 [doi]
• Session 14 overview: Next-generation processingPaul Liang, Marian Verhelst. 252-253 [doi]
• 14.1 A 126.1mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glassesSeongwook Park, Sungpill Choi, Jinmook Lee, Minseo Kim, Junyoung Park, Hoi-Jun Yoo. 254-255 [doi]
• 14.2 A 502GOPS and 0.984mW dual-mode ADAS SoC with RNN-FIS engine for intention prediction in automotive black-box systemKyuho Jason Lee, Kyeongryeol Bong, Changhyeon Kim, Jaeeun Jang, Hyunki Kim, Jihee Lee, Kyoung-Rog Lee, Gyeonghoon Kim, Hoi-Jun Yoo. 256-257 [doi]
• 14.3 A 0.55V 1.1mW artificial-intelligence processor with PVT compensation for micro robotsYouchang Kim, Dongjoo Shin, Jinsu Lee, Yongsu Lee, Hoi-Jun Yoo. 258-259 [doi]
• 14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOSHimanshu Kaul, Mark A. Anders, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal, Ram Krishnamurthy. 260-261 [doi]
• 14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networksYu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze. 262-263 [doi]
• 14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systemsJaehyeong Sim, Jun-Seok Park, Minhye Kim, Dongmyung Bae, YeongJae Choi, Lee-Sup Kim. 264-265 [doi]
• 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applicationsDajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto. 266-268 [doi]
• Session 15 overview: Oversampling data convertersVenkatesh Srinivasan, Tai-Cheng Lee. 268-269 [doi]
• 15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOSBo Wu, Shuang Zhu, Benwei Xu, Yun Chiu. 270-271 [doi]
• 15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BWLucien J. Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche. 272-273 [doi]
• 15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣMBlazej Nowacki, Nuno F. Paulino, João Goes. 274-275 [doi]
• 15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifactsSujith Billa, Amrith Sukumaran, Shanthi Pavan. 276-277 [doi]
• 15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOSYunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey Gealow. 278-279 [doi]
• 15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction techniqueSu-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai. 280-281 [doi]
• 15.7 A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BWBurak Gonen, Fabio Sebastiano, Robert H. M. van Veldhoven, Kofi A. A. Makinwa. 282-283 [doi]
• 15.8 A 22.3b 1kHz 12.7mW switched-capacitor ΔΣ modulator with stacked split-steering amplifiersMatthias Steiner, Nigel Greer. 284-286 [doi]
• Session 16 overview: Innovations in circuits and systems enabled by novel technologiesPirooz Parvarandeh, Shuichi Nagai. 286-287 [doi]
• 16.1 A nanogap transducer array on 32nm CMOS for electrochemical DNA sequencingDrew A. Hall, Jonathan S. Daniels, Bibiche Geuskens, Noureddine Tayebi, Grace M. Credo, David J. Liu, Handong Li, Kai Wu, Xing Su, Madoo Varma, Oguz H. Elibol. 288-289 [doi]
• 16.2 A Keccak-based wireless authentication tag with per-query key update and power-glitch attack countermeasuresChiraag Juvekar, Hyung-Min Lee, Joyce Kwong, Anantha P. Chandrakasan. 290-291 [doi]
• 16.3 A 16×16 pixels SPAD-based 128-Mb/s quantum random number generator with -74dB light rejection ratio and -6.7ppm/°C bias sensitivity on temperatureNicola Massari, Leonardo Gasparini, Alessandro Tomasi, Alessio Meneghetti, Hesong Xu, Daniele Perenzoni, Guglielmo Morgari, David Stoppa. 292-293 [doi]
• 16.4 A flexible EEG acquisition and biomarker extraction system based on thin-film electronicsTiffany Moy, Liechao Huang, Warren Rieutort-Louis, Sigurd Wagner, James C. Sturm, Naveen Verma. 294-295 [doi]
• 16.5 A flexible thin-film pixel array with a charge-to-current gain of 59µA/pC and 0.33% nonlinearity and a cost effective readout circuit for large-area X-ray imagingFlorian De Roose, Kris Myny, Soeren Steudel, Myriam Willigems, Steve Smout, Tim Piessens, Jan Genoe, Wim Dehaene. 296-297 [doi]
• 16.6 Flexible thin-film NFC transponder chip exhibiting data rates compatible to ISO NFC standards using self-aligned metal-oxide TFTsKris Myny, Soeren Steudel. 298-299 [doi]
• 16.7 A fully-integrated half-duplex data/power transfer system with up to 40Mb/s data rate, 23mW output power and on-chip 5kV galvanic isolationPierpaolo Lombardo, Vincenzo Fiore, Egidio Ragonese, Giuseppe Palmisano. 300-301 [doi]
• 16.8 A 3-to-40V 10-to-30MHz automotive-use GaN driver with active BST balancing and VSW dual-edge dead-time modulation achieving 8.3% efficiency improvement and 3.4ns constant propagation delayXugang Ke, Joseph Sankman, Minkyu Song, Pooya Forghani, Dongsheng Brian Ma. 302-304 [doi]
• Session 17 overview: SRAMHugh Mair, Atsushi Kawasumi. 304-305 [doi]
• 17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimizationTaejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyu-Hong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, E. S. Jung, Steve Sungho Park, Kinam Kim. 306-307 [doi]
• 17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technologyJohn Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang. 308-309 [doi]
• 17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOIMahmood Khayatzadeh, Mehdi Saligane, Jingcheng Wang, Massimo Alioto, David Blaauw, Dennis Sylvester. 310-312 [doi]
• Session 18 overview: High-bandwidth DRAMChulwoo Kim, Martin Brox. 312-313 [doi]
• 18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distributionHye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim 0001, Yong-Jun Kim, Ju-Hwan Kim, Won Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin. 314-315 [doi]
• 18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distributionKyomin Sohn, Won-Joo Yun, Reum Oh, Chi Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin. 316-317 [doi]
• 18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interfaceJong Chern Lee, Jihwan Kim, Kyung-whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae-Hwan Kim, Jin-Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee. 318-319 [doi]
• 18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test schemeYoung Jun Yoon, Byung Deuk Jeon, Byung-Soo Kim, Ki Up Kim, Tae Yong Lee, Nohhyup Kwak, Woo-Yeol Shin, Na Yeon Kim, Yunseok Hong, Kyeong Pil Kang, Dong Yoon Ka, Seong Ju Lee, Yong Sun Kim, Young Kyu Noh, Jaehoon Kim, Dong Keum Kang, Ho Uk Song, Hyeon Gon Kim, Jonghoon Oh. 320-322 [doi]
• Session 19 overview: Digital PLLsJohn Maneatis, Kathy Wilcox. 322-323 [doi]
• 19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoCFazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-en Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori. 324-325 [doi]
• 19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detectionSomnath Kundu, Bongjin Kim, Chris H. Kim. 326-327 [doi]
• 19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOSHyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho. 328-329 [doi]
• 19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOSKuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser A. Kurd. 330-331 [doi]
• 19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellationChe-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu. 332-333 [doi]
• 19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS SystemFahim U. Rahman, Visvesh S. Sathe. 334-335 [doi]
• 19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDCAkihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura. 336-337 [doi]
• 19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOSJunheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu. 338-340 [doi]
• Session 20 overview: RF-to-THz transceiver techniquesHarish Krishnaswamy, Jussi Ryynänen. 340-341 [doi]
• 20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channelsKosuke Katayama, Kyoya Takano, Shuhei Amakawa, Shinsuke Hara, Akifumi Kasamatsu, Koichi Mizuno, Kazuaki Takahashi, Takeshi Yoshida, Minoru Fujishima. 342-343 [doi]
• 20.2 A frequency-reconfigurable mm-Wave power amplifier with active-impedance synthesis in an asymmetrical non-isolated combinerChandraKanth Reddy Chappidi, Kaushik Sengupta. 344-345 [doi]
• 20.3 An 86-to-94.3GHz transmitter with 15.3dBm output power and 9.6% efficiency in 65nm CMOSYue Chao, Lianming Li, Howard Cam Luong. 346-347 [doi]
• 20.4 A 300GHz wirelessly locked 2×3 array radiating 5.4dBm with 5.1% DC-to-RF efficiency in 65nm CMOSSamuel Jameson, Eliezer Halpern, Eran Socher. 348-349 [doi]
• 20.5 1.4THz, -13dBm-EIRP frequency multiplier chain using symmetric- and asymmetric-CV varactors in 65nm CMOSZeshan Ahmad, Mark Lee, Kenneth K. O. 350-351 [doi]
• 20.6 A 28GHz efficient linear power amplifier for 5G phased arrays in 28nm bulk CMOSSherif Shakib, Hyun-Chul Park, Jeremy Dunworth, Vladimir Aparin, Kamran Entesari. 352-353 [doi]
• 20.7 An RF-PA supply modulator achieving 83% efficiency and -136dBm/Hz noise for LTE-40MHz and GSM 35dBm applicationsJi-Seon Paek, Yong-Sik Youn, Jeong-Hyun Choi, Dong-Su Kim, Jun-Hee Jung, Young-Hwan Choo, Sung-Jun Lee, Seung-Chul Lee, Thomas Byunghak Cho, Inyup Kang. 354-355 [doi]
• 20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexersBenjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx. 356-357 [doi]
• 20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixersTian Ya Liu, Antonio Liscidini. 358-359 [doi]
• 20.10 A 68.1-to-96.4GHz variable-gain low-noise amplifier in 28nm CMOSMarco Vigilante, Patrick Reynaert. 360-362 [doi]
• Session 21 overview: Harvesting and wireless powerAnton Bakker, Yuan Gao. 362-363 [doi]
• 21.1 A single-cycle MPPT charge-pump energy harvester using a thyristor-based VCO without storage capacitorXiaosen Liu, Edgar Sánchez-Sinencio. 364-365 [doi]
• 21.2 A 4µW-to-1mW parallel-SSHI rectifier for piezoelectric energy harvesting of periodic and shock excitations with inductor sharing, cold start-up and up to 681% power extraction improvementDaniel A. Sanchez, Joachim Leicht, Eduardas Jodka, Elham Fazel, Yiannos Manoli. 366-367 [doi]
• 21.3 A 200nA single-inductor dual-input-triple-output (DITO) converter with two-stage charging and process-limit cold-start voltage for photovoltaic and thermoelectric energy harvestingYanfeng Lu, Suyi Yao, Bin Shao, Paul Brokaw. 368-369 [doi]
• 21.4 A >78%-efficient light harvester over 100-to-100klux with reconfigurable PV-cell network and MPPT circuitInhee Lee, Wootaek Lim, Alan Teran, Jamie Phillips, Dennis Sylvester, David Blaauw. 370-371 [doi]
• 21.5 A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systemsMyungjoon Choi, Tae-Kwang Jang, Junwon Jeong, Seokhyeon Jeong, David Blaauw, Dennis Sylvester. 372-373 [doi]
• 21.6 A 1.2cm2 2.4GHz self-oscillating rectifier-antenna achieving -34.5dBm sensitivity for wirelessly powered sensorsJian Kang, Patrick Yin Chiang, Arun Natarajan. 374-375 [doi]
• 21.7 A 6.78MHz 6W wireless power receiver with a 3-level 1× / ½ × / 0× reconfigurable resonant regulating rectifierLin Cheng, Wing-Hung Ki, Tat-To Wong, Tak-Sang Yim, Chi-Ying Tsui. 376-377 [doi]
• 21.8 An all-in-one (Qi, PMA and A4WP) 2.5W fully integrated wireless battery charger IC for wearable applicationsJong Tae Hwang, Dong Su Lee, Jong-Hoon Lee, Sung Min Park, Ki Woong Jin, Min Jung Ko, Hyun Ick Shin, Sang Oh Jeon, Dae Ho Kim, Joon Rhee. 378-380 [doi]
• Session 22 overview: Systems and instruments for human-machine interfacesLong Yan, Refet Firat Yazicioglu. 380-381 [doi]
• 22.2 A 176-channel 0.5cm3 0.7g wireless implant for motor function recovery after spinal cord injuryYi-Kai Lo, Chih-Wei Chang, Yen-Cheng Kuan, Stanislav Culaclii, Brian Kim, Kuanfu Chen, Parag Gad, V. Reggie Edgerton, Wentai Liu. 382-383 [doi]
• 22.3 A 141µW sensor SoC on OLED/OPD substrate for SpO2/ExG monitoring stickerYongsu Lee, Hyeonwoo Lee, Jaeeun Jang, Jihee Lee, Minseo Kim, Jaehyuk Lee, Hyunki Kim, Kyoung-Rog Lee, Kwantae Kim, Hyunwoo Cho, Seunghyup Yoo, Hoi-Jun Yoo. 384-385 [doi]
• 22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled dataPamula Venkata Rajesh, Jose Manuel Valero-Sarmiento, Long Yan, Alper Bozkurt, Chris Van Hoof, Nick Van Helleputte, Refet Firat Yazicioglu, Marian Verhelst. 386-387 [doi]
• 22.5 A 0.5V 55µW 64×2-channel binaural silicon cochlea for event-driven stereo-audio sensingMinhao Yang, Chen-Han Chien, Tobias Delbrück, Shih-Chii Liu. 388-389 [doi]
• 22.6 A 22V compliant 56µW active charge balancer enabling 100% charge compensation even in monophasic and 36% amplitude correction in biphasic neural stimulatorsNatalie Butz, Armin Taschwer, Yiannos Manoli, Matthias Kuhl. 390-391 [doi]
• 22.7 A 966-electrode neural probe with 384 configurable channels in 0.13µm SOI CMOSCarolina Mora Lopez, Srinjoy Mitra, Jan Putzeys, Bogdan Raducanu, Marco Ballini, Alexandru Andrei, Simone Severi, Marleen Welkenhuysen, Chris Van Hoof, Silke Musa, Refet Firat Yazicioglu. 392-393 [doi]
• 22.8 Multi-functional microelectrode array system featuring 59, 760 electrodes, 2048 electrophysiology channels, impedance and neurotransmitter measurement unitsVijay Viswam, Jelena Dragas, Amir Shadmani, Yihui Chen, Alexander Stettler, Jan Mueller, Andreas Hierlemann. 394-396 [doi]
• Session 23 overview: Electrical and optical link innovationsFrank O'Mahony, Simone Erba. 396-397 [doi]
• 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOSGuanghua Shu, Woo-seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu. 398-399 [doi]
• 23.2 A 32Gb/s bidirectional 4-channel 4pJ/b capacitively coupled link in 14nm CMOS for proximity communicationChintan Thakkar, Shreyas Sen, James E. Jaussi, Bryan Casper. 400-401 [doi]
• 23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displaysMohammad Hekmat, Sanquan Song, Nancy Jaffari, Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong. 402-403 [doi]
• 23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologiesEnrico Temporiti, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Francesco Svelto. 404-405 [doi]
• 23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimpedance amplifier with automatic gain control in 0.13µm BiCMOS technology for optical fiber coherent receiversAhmed Awny, Rajasekhar Nagulapalli, Daniel Micusik, Jan Hoffmann, Gunter Fischer, Dietmar Kissinger, Ahmet Cagri Ulusoy. 406-407 [doi]
• 23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-pathPier Andrea Francese, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl. 408-409 [doi]
• 23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µsShayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone. 410-411 [doi]
• 23.8 A 40Gb/s 14mW CMOS wireline receiverAbishek Manian, Behzad Razavi. 412-414 [doi]
• Session 24 overview: Ultra-efficient computing: Application-inspired and analog-assisted digitalAntoine Dupret, Subhasish Mitra. 414-415 [doi]
• 24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impairedDongsuk Jeon, Nathan Ickes, Priyanka Raina, Hsueh-Cheng Wang, Daniela Rus, Anantha Chandrakasan. 416-417 [doi]
• 24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nmEdward H. Lee, S. Simon Wong. 418-419 [doi]
• 24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOSSkylar Skrzyniarz, Laura Fick, Jinal Shah, Yejoong Kim, Dennis Sylvester, David Blaauw, David Fick, Michael B. Henry. 420-422 [doi]
• Session 25 overview: Mm-Wave and THz sensingBrian Ginsburg, Minoru Fujishima. 422-423 [doi]
• 25.1 A fully integrated 0.55THz near-field sensor with a lateral resolution down to 8µm in 0.13µm SiGe BiCMOSJanusz Grzyb, Bernd Heinemann, Ullrich R. Pfeiffer. 424-425 [doi]
• 25.2 A 210-to-305GHz CMOS receiver for rotational spectroscopyQian Zhong, Wooyeol Choi, Christopher Miller, Rashaunda Henderson, Kenneth K. O. 426-427 [doi]
• 25.3 A 40-to-330GHz synthesizer-free THz spectroscope-on-chip exploiting electromagnetic scatteringXue Wu, Kaushik Sengupta. 428-429 [doi]
• 25.4 A 0.43K-noise-equivalent-ΔT 100GHz dicke-free radiometer with 100% time efficiency in 65nm CMOSA. J. Tang, Yangyho Kim, Qun Jane Gu. 430-431 [doi]
• 25.5 A 320GHz subharmonic-mixing coherent imager in 0.13µm SiGe BiCMOSChen Jiang, Ali Mostajeran, Ruonan Han, Mohammad Emadi, Hani Sherry, Andreia Cathelin, Ehsan Afshari. 432-434 [doi]
• Session 26 overview: Wireless for IoEKenichi Okada, Jan van Sinderen. 434-435 [doi]
• 26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOSHidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura. 436-437 [doi]
• 26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilienceDawei Ye, Ronan A. R. van der Zee, Bram Nauta. 438-439 [doi]
• 26.3 A 1.3nJ/b IEEE 802.11ah fully digital polar transmitter for IoE applicationsAo Ba, Yao-Hong Liu, Johan H. C. van den Heuvel, Paul Mateman, Benjamin Busze, Jordy Gloudemans, Peter Vis, Johan Dijkhuis, Christian Bachmann, Guido Dolmans, Kathleen Philips, Harmke de Groot. 440-441 [doi]
• 26.4 A 160-to-960MHz ETSI class-1-compliant IoE transceiver with 100dB blocker rejection, 70dB ACR and 800pA standby currentNiall Kearney, Charley Billon, Michael Deeney, Eric Evans, Kalim Khan, Hongxing Li, Siwen Liang, Kenneth Mulvaney, Keith A. O'Donoghue, Shane O'Mahony, Philip Quinlan, Sivanendra Selvanayagam, Sudarshan Onkar, Charul Agrawal. 442-443 [doi]
• 26.5 A 0.7V 1.5-to-2.3mW GNSS receiver with 2.5-to-3.8dB NF in 28nm FD-SOIKen Yamamoto, Kenichi Nakano, Gaku Hidai, Yuya Kondo, Hitoshi Tomiyama, Hideyuki Takano, Fumitaka Kondo, Yusuke Shinohe, Hidenori Takeuchi, Nobuhisa Ozawa, Shingo Harada, Shinichiro Eto, Mari Kishikawa, Daisuke Ide, Hiroyasu Tagami, Masayuki Katakura, Norio Shoji. 444-445 [doi]
• 26.6 A programmable receiver front-end achieving >17dBm IIP3 at <1.25×BW frequency offsetSameed Hameed, Neha Sinha, Mansour Rachid, Sudhakar Pamarti. 446-447 [doi]
• 26.7 A 10mm3 syringe-implantable near-field radio system on glass substrateYao Shi, Myungjoon Choi, Ziyun Li, Gyouho Kim, Zhiyoong Foo, Hun-Seok Kim, David Wentzloff, David Blaauw. 448-449 [doi]
• 26.8 A 236nW -56.5dBm-sensitivity bluetooth low-energy wakeup receiver with energy harvesting in 65nm CMOSNathan E. Roberts, Kyle Craig, Aatmesh Shrivastava, Stuart N. Wooters, Yousef Shakhsheer, Benton H. Calhoun, David D. Wentzloff. 450-451 [doi]
• 26.9 A 0.038mm2 SAW-less multiband transceiver using an N-Path SC gain loopGengzhen Qi, Pui-In Mak, Rui Paulo Martins. 452-454 [doi]
• Session 27 overview: Hybrid and nyquist data convertersStéphane Le Tual, Kostas Doris. 454-455 [doi]
• 27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOSShiyu Su, Mike Shuo-Wei Chen. 456-457 [doi]
• 27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOSYun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo. 458-459 [doi]
• 27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DACKyojin D. Choo, John Bell, Michael P. Flynn. 460-461 [doi]
• 27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOSChun-Cheng Liu. 462-463 [doi]
• 27.5 A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidthMatt Straayer, Jim Bales, Dwight Birdsall, Denis C. Daly, Phillip Elliott, Bill Foley, Roy Mason, Vikas Singh, Xuejin Wang. 464-465 [doi]
• 27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOSJiangfeng Wu, Acer Chou, Tianwei Li, Rong Wu, Tao Wang, Giuseppe Cusmai, Sha-Ting Lin, Cheng-Hsun Yang, Greg Unruh, Sunny Raj Dommaraju, Mo M. Zhang, Po Tang Yang, Wei-Ting Lin, Xi Chen, Dongsoo Koh, Qingqi Dou, Hemasundar Mohan Geddada, Juo-Jung Hung, Massimo Brandolini, Young Shin, Hung Sen Huang, Chun-Ying Chen, Ardie Venes. 466-467 [doi]
• 27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibrationChin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee. 468-469 [doi]
• 27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOSAlessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani. 470-472 [doi]
• Session 28 overview: Biological sensors for point of carePeter Wu, Jan Genoe. 472-473 [doi]
• 28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assaysKa-Meng Lei, Hadi Heidari, Pui-In Mak, Man Kay Law, Franco Maloberti, Rui Paulo Martins. 474-475 [doi]
• 28.2 A 14GHz battery-operated point-of-care ESR spectrometer based on a 0.13µm CMOS ASICJonas Handwerker, Benedikt Schlecker, Ulrich Wachter, Peter Radermacher, Maurits Ortmanns, Jens Anders. 476-477 [doi]
• 28.3 CMOS biosensor IC focusing on dielectric relaxations of biological water with 120GHz and 60GHz oscillator arraysTakeshi Mitsunaka, Nobuyuki Ashida, Akira Saito, Kunihiko Iizuka, Tetsuhito Suzuki, Yuichi Ogawa, Minoru Fujishima. 478-479 [doi]
• 28.4 A battery-powered efficient multi-sensor acquisition system with simultaneous ECG, BIO-Z, GSR, and PPGMario Konijnenburg, Stefano Stanzione, Long Yan, Dong-Woo Jee, Julia Pettine, Roland Van Wegberg, Hyejung Kim, Chris van Liempd, Ram Fish, James Schluessler, Harmke de Groot, Chris Van Hoof, Refet Firat Yazicioglu, Nick Van Helleputte. 480-481 [doi]
• 28.5 A 0.6V 0.015mm2 time-based biomedical readout for ambulatory applications in 40nm CMOSRachit Mohan, Samira Zaliasl, Georges G. E. Gielen, Chris Van Hoof, Nick Van Helleputte, Refet Firat Yazicioglu. 482-483 [doi]
• 28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correctionWenlong Jiang, Vahagn Hokhikyan, Hariprasad Chandrakumar, Vaibhav Karkare, Dejan Markovic. 484-485 [doi]
• 28.7 CMOS monolithic airborne-particulate-matter detector based on 32 capacitive sensors with a resolution of 65zF rmsPietro Ciccarella, Marco Carminati, Marco Sampietro, Giorgio Ferrari. 486-488 [doi]
• F1: Designing secure systems: Manufacturing, circuits and architecturesVivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata. 492-494 [doi]
• F2: Data-converter calibration and dynamic-matching techniquesKostas Doris, Alyosha Molnar, Xicheng Jiang, Seung-Tak Ryu. 495-497 [doi]
• F3: Radio architectures and circuits towards 5GStefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic. 498-501 [doi]
• F4: Emerging short-reach and high-density interconnect solutions for internet of everythingIchiro Fujimori, Martin Brox, Elad Alon, Pavan Hanumolu, Gerrit den Besten, Hideyuki Nosaka. 502-505 [doi]
• F5: Advanced IC design for ultra-low-noise sensingMakoto Ikeda, David Stoppa, Michiel Pertijs, Yusuke Oike, Maurits Ortmanns, Vadim Ivanov, Fu-Lung Hsueh. 506-509 [doi]
• F6: Circuit, systems and data processing for next-generation wearable and implantable medical devicesKush Gulati, Refet Firat Yazicioglu, Antoine Dupret, Roman Genov, Peter Chung-Yu Wu, Long Yan. 510-513 [doi]
• ES1: Student research previewJan Van der Spiegel, SeongHwan Cho, Denis Daly. 514-516 [doi]
• ES2: Computing architectures paving the path to power efficiencyDejan Markovic, Antoine Dupret, Atsuki Inoue, Dejan Markovic. 517 [doi]
• EE1: Class of 2025 - Where will be the best jobs?Xicheng Jiang, Axel Thomsen, Piero Malcovati, M.-C. Frank Chang. 518 [doi]
• EE2: Do we need to downscale our radios below 20nm?Harish Krishnaswamy, Jan Craninckx, Tae-Wook Kim, Harish Krishnaswamy. 519 [doi]
• EE3: Survey says!Harry Lee, Matt Straayer, Chris Mangelsdorf. 520 [doi]
• EE4: Eureka! The best moments of solid-state circuit design in the 2000sWoogeun Rhee, Eric A. M. Klumperink, Hossein Hashemi. 521 [doi]
• SC1: Circuits for the internet of everythingWim Dehaene. 522-523 [doi]