Kiyoung Choi - researchr alias

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2011

A polynomial-time custom instruction identification algorithm based on dynamic programmingJunwhan Ahn, Imyong Lee, Kiyoung Choi. aspdac 2011: 573-578 [doi]

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable ArchitecturesGanghee Lee, Kiyoung Choi, Nikil D. Dutt. tcad, 30(5):637-650, 2011. [doi]

2010

Memory-Centric Communication Architecture for Reconfigurable ComputingKyungwook Chang, Kiyoung Choi. arc 2010: 400-405 [doi]

Acceleration of control flow on CGRA using advanced predicated executionKyuseung Han, Jong Kyung Paek, Kiyoung Choi. fpt 2010: 429-432 [doi]

Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable ArchitectureYoonjin Kim, Rabi N. Mahapatra, Kiyoung Choi. tvlsi, 18(10):1471-1482, 2010. [doi]

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable ArchitectureGanghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt. arc 2010: 231-243 [doi]

Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative executionGanghee Lee, Kyungwook Chang, Kiyoung Choi. ipps 2010: 1-4 [doi]

Binary acceleration using coarse-grained reconfigurable architectureJong Kyung Paek, Kiyoung Choi, Jong-eun Lee. sigarch, 38(4):33-39, 2010. [doi]

2009

2008

2007

Low Runtime-Overhead Software Synthesis for Communicating Concurrent ProcessesYoungchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya. rsp 2007: 195-201 [doi]

Buffer Size Reduction through Control-Flow DecompositionYoungchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi. rtcsa 2007: 183-190 [doi]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich, editors, ACM, 2007.

Instruction set synthesis with efficient instruction encoding for configurable processorsJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. todaes, 12(1), 2007. [doi]

Memory Operation Inclusive Instruction-Set Extensions and Data Path GenerationImyong Lee, Dongwook Lee, Kiyoung Choi. asap 2007: 383-390 [doi]

Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space ExplorationGanghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi. samos 2007: 50-57 [doi]

Communication Architecture Synthesis of Cascaded Bus MatrixJun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi. aspdac 2007: 171-177 [doi]

2006

2005

2004

2003

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC DesignYoungchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh. date 2003: 20132-20137 [doi]

Configurable Processors for Embedded ComputingNikil D. Dutt, Kiyoung Choi. Computer, 36(1):120-123, 2003. [doi]

Energy-efficient instruction set synthesis for application-specific processorsJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. islped 2003: 330-333 [doi]

An algorithm for mapping loops onto coarse-grained reconfigurable architecturesJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. lctrts 2003: 183-188 [doi]

Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable ArchitecturesJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. asap 2003: 172-182 [doi]

Compilation Approach for Coarse-Grained Reconfigurable ArchitecturesJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. dt, 20(1):26-33, 2003. [doi]

2002

Efficient instruction encoding for automatic instruction set design of configurable ASIPsJong-eun Lee, Kiyoung Choi, Nikil Dutt. iccad 2002: 649-654 [doi]

Reconfigurable SoC design with hierarchical FSM and synchronous dataflow modelSunghyun Lee, Sungjoo Yoo, Kiyoung Choi. codes 2002: 199-204 [doi]

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow modelSunghyun Lee, Kiyoung Choi, Sungjoo Yoo. islped 2002: 84-87 [doi]

2001

High-level synthesis under multi-cycle interconnect delayJinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi. aspdac 2001: 662 [doi]

Performance improvement of multi-processor systems cosimulation based on SW analysisJinyong Jung, Sungjoo Yoo, Kiyoung Choi. date 2001: 749-753 [doi]

Behavior-to-Placed RTL Synthesis with Performance-Driven PlacementDaehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi. iccad 2001: 320 [doi]

Low power pipelining of linear systems: a common operand centric approachDaehong Kim, Dongwan Shin, Kiyoung Choi. islped 2001: 225-230 [doi]

Scheduling-based code size reduction in processors with indirect addressing modeSungtaek Lim, Jihong Kim, Kiyoung Choi. codes 2001: 165-169 [doi]

Performance-driven high-level synthesis with bit-level chaining andclock selectionSanghun Park, Kiyoung Choi. tcad, 20(2):199-212, 2001. [doi]

Area-efficient buffer binding based on a novel two-port FIFO structureKyoungseok Rha, Kiyoung Choi. codes 2001: 122-127 [doi]

Narrow bus encoding for low-power DSP systemsYoungsoo Shin, Kiyoung Choi, Young-Hoon Chang. tvlsi, 9(5):656-660, 2001. [doi]

Partial bus-invert coding for power optimization of application-specific systemsYoungsoo Shin, Soo-Ik Chae, Kiyoung Choi. tvlsi, 9(2):377-383, 2001. [doi]

2000

Power minimization of functional units partially guarded computationJunghwan Choi, Jinhwan Jeon, Kiyoung Choi. islped 2000: 131-136 [doi]

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAsByungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi. aspdac 2000: 169-174 [doi]

Narrow bus encoding for low power systemsYoungsoo Shin, Kiyoung Choi. aspdac 2000: 217-220 [doi]

Power Optimization of Real-Time Embedded Systems on Variable Speed ProcessorsYoungsoo Shin, Kiyoung Choi, Takayasu Sakurai. iccad 2000: 365-368

Schedulability-driven performance analysis of multiple mode embedded real-time systemsYoungsoo Shin, Daehong Kim, Kiyoung Choi. dac 2000: 495-500 [doi]

Low power self-timed Radix-2 division (poster session)Jae-Hee Won, Kiyoung Choi. islped 2000: 210-212 [doi]

Fast Hardware-Software Coverification by Optimistic Execution of Real ProcessorSungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi. date 2000: 663-668 [doi]

Performance improvement of geographically distributed cosimulation by hierarchically grouped messagesSungjoo Yoo, Kiyoung Choi, Dong Sam Ha. tvlsi, 8(5):492-502, 2000. [doi]

Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory modelSungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi. codes 2000: 77-81 [doi]

1999

1998

1997

Power-conscious High Level Synthesis Using Loop FoldingDaehong Kim, Kiyoung Choi. dac 1997: 441-445 [doi]

Enforcing Schedulability of Multi-Task Systems by Hardware-Software CodesignYoungsoo Shin, Kiyoung Choi. codes 1997: 3-8 [doi]

Low power high level synthesis by increasing data correlationDongwan Shin, Kiyoung Choi. islped 1997: 62-67 [doi]

1996

Self-timed divider based on RSD number systemKiJong Lee, Kiyoung Choi. tvlsi, 4(2):292-295, 1996. [doi]

Software synthesis through task decomposition by dependency analysisYoungsoo Shin, Kiyoung Choi. iccad 1996: 98-104 [doi]

1995

An integrated hardware-software cosimulation environment for heterogeneous systems prototypingYongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha. aspdac 1995: [doi]

Efficient Prototyping System Based on Incremental Design and Module-by-Module VerificationYongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi. iscas 1995: 924-927

1994

A Self-Timed Divider Using RSD Number SystemKiyoung Choi, KiJong Lee, Jun-Woo Kang. iccd 1994: 504-507

1988

Incremental-in-time Algorithm for Digital SimulationKiyoung Choi, Sun Young Hwang, Tom Blank. dac 1988: 501-505 [doi]

Fast functional simulation: an incremental approachSun Young Hwang, Tom Blank, Kiyoung Choi. tcad, 7(7):765-774, 1988. [doi]