Abstract is missing.
- SoC in Nanoera: Challenges and Endless PossibilityJeong-Taek Kong. 2
- A High Quality/Low Computational Cost Technique for Block Matching Motion EstimationSebastián López, Gustavo Marrero Callicó, José Francisco López, Roberto Sarmiento. 2-7 [doi]
- Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology ChallengesGarry Hughes. 3
- A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable ArchitecturesNastaran Baradaran, Pedro C. Diniz. 6-11 [doi]
- Hardware Acceleration of Hidden Markov Model Decoding for Person DetectionSuhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk. 8-13 [doi]
- Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific OptimizationYoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi. 12-17 [doi]
- A Hardware-Friendly Wavelet Entropy Codec for Scalable VideoHendrik Eeckhaut, Harald Devos, Benjamin Schrauwen, Mark Christiaens, Dirk Stroobandt. 14-19 [doi]
- A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software PartitioningRoman L. Lysecky, Frank Vahid. 18-23 [doi]
- A Real-Time Streaming Memory ControllerArtur Burchard, Ewa Hekstra-Nowacka, Atul Chauhan. 20-25 [doi]
- Reconfigurable Elliptic Curve Cryptosystems on a ChipRay C. C. Cheung, Wayne Luk, Peter Y. K. Cheung. 24-29 [doi]
- A Coprocessor for Accelerating Visual Information ProcessingWalter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón. 26-31 [doi]
- An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAsRui Rodrigues, João M. P. Cardoso. 30-31 [doi]
- Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform ArchitecturesSandro V. Silva, Sergio Bampi. 32-37 [doi]
- FPGA Architecture for Multi-Style Asynchronous LogicN. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin. 32-33 [doi]
- Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich. 36-42 [doi]
- Hardware Engines for Bus Encryption: A Survey of Existing TechniquesReouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud. 40-45 [doi]
- On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System ChipsSandeep Kumar Goel, Erik Jan Marinissen. 44-49 [doi]
- Performance Considerations for an Embedded Implementation of OMA DRM 2Daniel Thull, Roberto Sannino. 46-51 [doi]
- Test Planning for Mixed-Signal SOCs with Wrapped Analog CoresAnuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty. 50-55 [doi]
- A Novel Unified Architecture for Public-Key CryptographyAlessandro Cilardo, Antonino Mazzeo, Nicola Mazzocca, Luigi Romano. 52-57 [doi]
- Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test QualityMatthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press. 56-61 [doi]
- A VLSI Design Flow for Secure Side-Channel Attack Resistant ICsKris Tiri, Ingrid Verbauwhede. 58-63 [doi]
- Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based ArchitectureAlexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno. 62-63 [doi]
- Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching ApproachShengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie. 64-69 [doi]
- The Challenges of Hardware Synthesis from C-Like LanguagesStephen A. Edwards. 66-67 [doi]
- Software Thread Integration and Synthesis for Real-Time ApplicationsAlexander G. Dean. 68-69 [doi]
- Applying UML and MDA to Real Systems DesignIan Oliver. 70-71 [doi]
- Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba s MethodZoya Dyka, Peter Langendoerfer. 70-75 [doi]
- Energy Bounds for Fault-Tolerant Nanoscale DesignsDiana Marculescu. 74-79 [doi]
- An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication SecurityHala A. Farouk, Magdy Saeb. 76-81 [doi]
- DVS for On-Chip Bus Designs Based on Timing Error CorrectionHimanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin. 80-85 [doi]
- FPGA based Agile Algorithm-On-Demand Co-ProcessorRamachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti. 82-83 [doi]
- Joint Power Management of Memory and DiskLe Cai, Yung-Hsiang Lu. 86-91 [doi]
- Multimedia Applications of Multiprocessor Systems-on-ChipsWayne Wolf. 86-89 [doi]
- Assertion-Based Design Exploration of DVS in Network Processor ArchitecturesJia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin. 92-97 [doi]
- Wireless LAN: Past, Present, and FutureKeith Holt. 92-93 [doi]
- Direct Conversion Pulsed UWB Transceiver ArchitectureRaúl Blázquez, Fred S. Lee, David D. Wentzloff, Brian P. Ginsburg, Johnna Powell, Anantha Chandrakasan. 94-95 [doi]
- Power Saving Techniques for Wireless LANsTajana Simunic. 96-97 [doi]
- A Synthesizable IP Core for DVB-S2 LDPC Code DecodingFrank Kienle, Torben Brack, Norbert Wehn. 100-105 [doi]
- Instruction Scheduling for Dynamic Hardware ConfigurationsElena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis. 100-105 [doi]
- A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable HardwareJavier Resano, Daniel Mozos, Francky Catthoor. 106-111 [doi]
- picoArray Technology: The Tool s StoryAndrew Duller, Daniel Towner, Gajinder Panesar, Alan Gray, Will Robbins. 106-111 [doi]
- Queue Management in Network ProcessorsIoannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis. 112-117 [doi]
- Optimized Generation of Data-Path from C Codes for FPGAsZhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers. 112-117 [doi]
- System Level Analysis of the Bluetooth StandardMassimo Conti, Daniele Moretti. 118-123 [doi]
- Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial SeriesEwout Martens, Georges G. E. Gielen. 120-125 [doi]
- C Based Hardware Design for Wireless ApplicationsAndrés Takach, Bryan Bowyer, Thomas Bollaert. 124-129 [doi]
- Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop TracingFang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev. 126-131 [doi]
- Hardware Accelerated Collision Detection - An Architecture and Simulation ResultsAndreas Raabe, Blazej Bartyzel, Joachim K. Anlauf, Gabriel Zachmann. 130-135 [doi]
- On Statistical Timing Analysis with Inter- and Intra-Die VariationsHratch Mangassarian, Mohab Anis. 132-137 [doi]
- Modeling of a Reconfigurable OFDM IP Block Family For an RF System SimulatorHannu Heusala, Jussi Liedes. 136-137 [doi]
- Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus ArchitectureYoung-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo. 138-139 [doi]
- Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit SynthesisRaoul F. Badaoui, Ranga Vemuri. 138-143 [doi]
- Meeting the Embedded Design Needs of Automotive ApplicationsWayne Lyons. 142-147 [doi]
- On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI CircuitsKoichiro Noguchi, Makoto Nagata. 146-151 [doi]
- Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCsAlbrecht Mayer, Harry Siebert, Klaus D. McDonald-Maier. 148-152 [doi]
- Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECLDavid C. Keezer, C. Gray, A. M. Majid, N. Taher. 152-157 [doi]
- The Integration of On-Line Monitoring and Reconfiguration Functions using IEEE1149.4 Into a Safety Critical Automotive Electronic Control UnitCarl Jeffrey, Reuben Cutajar, Stephen Prosser, M. Lickess, Andrew Richardson, Stephen Riches. 153-158 [doi]
- Noise Figure Evaluation Using Low Cost BISTMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 158-163 [doi]
- LC Oscillator Driver for Safety Critical ApplicationsPavel Horsky. 159-164 [doi]
- Specification Test Compaction for Analog Circuits and MEMSSounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi. 164-169 [doi]
- Context Sensitive Performance Analysis of Automotive ApplicationsJan Staschulat, Rolf Ernst, Andreas Schulze, Fabian Wolf. 165-170 [doi]
- Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented ApproachRabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir. 170-171 [doi]
- AutoMoDe - Model-Based Development of Automotive SoftwareDirk Ziegenbein, Peter Braun 0003, Ulrich Freund, Andreas Bauer 0002, Jan Romberg, Bernhard Schätz. 171-177 [doi]
- EEE 1149.4 Compatible ABMs for Basic RF MeasurementsPekka Syri, Juha Häkkinen, Markku Moilanen. 172-173 [doi]
- Fault-Trajectory Approach for Fault Diagnosis on Analog CircuitsCarlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho. 174-175 [doi]
- SystemC Analysis of a New Dynamic Power Management ArchitecturMassimo Conti. 177-178 [doi]
- Secure Embedded Processing through Hardware-Assisted Run-Time MonitoringDivya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 178-183 [doi]
- Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety SystemsSteve Chappell, Alistair Macarthur, Dan Preston, Dave Olmstead, Bob Flint, Chris Sullivan. 180-185 [doi]
- Energy-Aware Routing for E-Textile ApplicationsJung-Chun Kao, Radu Marculescu. 184-189 [doi]
- Platform Based Design for Automotive Sensor ConditioningLuca Fanucci, A. Giambastiani, Francesco Iozzi, Corrado Marino, A. Rocchi. 186-191 [doi]
- LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor NetworksArijit Ghosh, Tony Givargis. 190-195 [doi]
- Realization of a Virtual Lambda Sensor on a Fixed Precision SystemPaolo Amato, Nicola Cesario, M. Di Meglio, Francesco Pirozzi. 192-197 [doi]
- Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement PerspectivesBruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan, Wim Dehaene. 196-201 [doi]
- Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization DetectionClaudio Stagni, Carlotta Guiducci, Massimo Lanzoni, Luca Benini, Bruno Riccò. 198-203 [doi]
- Lifetime Modeling of a Sensor NetworkVivek Rai, Rabi N. Mahapatra. 202-203
- A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop SystemsMomchil Milev, Rod Burt. 204-208 [doi]
- A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICsJosé Luis Rosselló, Vicens Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura. 206-211 [doi]
- Activity Packing in FPGAs for Leakage Power ReductionHassan Hassan, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry. 212-217 [doi]
- Simultaneous Partitioning and Frequency Assignment for On-Chip Bus ArchitecturesSuresh Srinivasan, Lin Li, Narayanan Vijaykrishnan. 218-223 [doi]
- Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic CircuitsSaibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy. 224-229 [doi]
- Leakage-Aware Interconnect for On-Chip NetworkYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 230-231 [doi]
- Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware TilesVincent Nollet, Théodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet. 234-239 [doi]
- Symmetric Multiprocessing on Programmable Chips Made EasyAustin Hung, William D. Bishop, Andrew A. Kennings. 240-245 [doi]
- A Complete Network-On-Chip Emulation FrameworkNicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor. 246-251 [doi]
- Low Cost Task Migration Initiation in a Heterogeneous MP-SoCVincent Nollet, Prabhat Avasare, Jean-Yves Mignolet, Diederik Verkest. 252-253 [doi]
- Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-ChipSander Stuijk, Twan Basten, Bart Mesman, Marc Geilen. 254-255 [doi]
- Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery CircuitPaul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici. 258-263 [doi]
- MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power ConsumptionHua Tang, Ying Wei, Alex Doboli. 264-269 [doi]
- Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect ResistanceCharlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay. 270-275 [doi]
- Systematic Figure of Merit Computation for the Design of Pipeline ADCLudovic Barrandon, S. Crand, Dominique Houzet. 277-278 [doi]
- Designer-Driven Topology Optimization for Pipelined Analog to Digital ConvertersYu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee. 279-280 [doi]
- Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer MatricesSmita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes. 282-287 [doi]
- Soft-Error Tolerance Analysis and Optimization of Nanometer CircuitsYuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee. 288-293 [doi]
- Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical TechniquesOsama Neiroukh, Xiaoyu Song. 294-299 [doi]
- Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide BreakdownJonathan R. Carter, Sule Ozev, Daniel J. Sorin. 300-305 [doi]
- An Accurate SER Estimation Method Based on Propagation ProbabilityGhazanfar Asadi, Mehdi Baradaran Tahoori. 306-307 [doi]
- Techniques for Fast Transient Fault Grading Based on Autonomous EmulationCelia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes. 308-309 [doi]
- TDMA Time Slot and Turn Optimization with Evolutionary Search TechniquesArne Hamann, Rolf Ernst. 312-317 [doi]
- Scheduling of Soft Real-Time Systems for Context-Aware ApplicationsJennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak. 318-323 [doi]
- Model Reuse through Hardware Design PatternsFernando Rincón, Francisco Moya, Jesús Barba, Juan Carlos López. 324-329 [doi]
- A Public-Key Watermarking Technique for IP DesignsAmr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid. 330-335 [doi]
- Design of a Virtual Component Neutral Network-on-Chip Transaction LayerPhilippe Martin. 336-337 [doi]
- Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia ProcessingShrirang M. Yardi, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha. 340-345 [doi]
- HEBS: Histogram Equalization for Backlight ScalingAli Iranli, Hanif Fatemi, Massoud Pedram. 346-351 [doi]
- Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition ApproachÜmit Y. Ogras, Radu Marculescu. 352-357 [doi]
- A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated ProcessorsTohru Ishihara, Farzan Fallah. 358-363 [doi]
- Design Space Exploration for Dynamically Reconfigurable ArchitecturesBenoit Miramond, Jean-Marc Delosme. 366-371 [doi]
- A Dependability-Driven System-Level Design Approach for Embedded SystemsArshad Jhumka, Stephan Klaus, Sorin A. Huss. 372-377 [doi]
- A Time Slice Based Scheduler Model for System Level DesignLuciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe. 378-383 [doi]
- A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-EmulationJae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung. 384-389 [doi]
- Automated Synthesis of Assertion Monitors using Visual SpecificationsAmbar A. Gadkari, S. Ramesh. 390-395 [doi]
- A Decompilation Approach to Partitioning Software for Microprocessor/FPGA PlatformsGreg Stitt, Frank Vahid. 396-397 [doi]
- Statistical Timing Based Optimization using Gate SizingAseem Agarwal, Kaviraj Chopra, David Blaauw. 400-405 [doi]
- An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit GraphsMaxim Teslenko, Elena Dubrova. 406-411 [doi]
- SAT-Based Complete Don t-Care Computation for Network OptimizationAlan Mishchenko, Robert K. Brayton. 412-417 [doi]
- Efficient Solution of Language Equations Using Partitioned RepresentationsAlan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko. 418-423 [doi]
- DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and ImprovementG. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain. 424-429 [doi]
- Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven DecompositionAndrés Martinelli, Elena Dubrova. 430-431 [doi]
- Uniformly-Switching Logic for Cryptographic HardwareIgor L. Markov, Dmitri Maslov. 432-433 [doi]
- Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group TheoryGuowu Yang, William N. N. Hung, Xiaoyu Song, Marek A. Perkowski. 434-435 [doi]
- Memory Testing Under Different Stress Conditions: An Industrial EvaluationAnanta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen. 438-443 [doi]
- Worst-Case and Average-Case Analysis of n-Detection Test SetsIrith Pomeranz, Sudhakar M. Reddy. 444-449 [doi]
- Defect Aware Test PatternsHuaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz. 450-455 [doi]
- Computational Intelligence Characterization Method of Semiconductor DeviceEric Liau, Doris Schmitt-Landsiedel. 456-461 [doi]
- A New Embedded Measurement Structure for eDRAM CapacitorLaurent Lopez, Jean Michel Portal, Didier Née. 462-463 [doi]
- Smart Temperature Sensor for Thermal Testing of Cell-Based ICsSebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura. 464-465 [doi]
- An Approximation Algorithm for Energy-Efficient Scheduling on A Chip MultiprocessorChuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo. 468-473 [doi]
- Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival ModelHaisang Wu, Binoy Ravindran, E. Douglas Jensen. 474-479 [doi]
- Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-DependenciesRafik Henia, Rolf Ernst. 480-485 [doi]
- A New Task Model for Streaming Applications and Its Schedulability AnalysisSamarjit Chakraborty, Lothar Thiele. 486-491 [doi]
- Efficient Feasibility Analysis for Real-Time Systems with EDF SchedulingKarsten Albers, Frank Slomka. 492-497 [doi]
- Unified Modeling of Complex Real-Time Control SystemsHe Hai, Zhong Yi-fang, Cai Chi-lan. 498-499 [doi]
- Exploring NoC Mapping Strategies: An Energy and Timing Aware TechniqueCésar A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel. 502-507 [doi]
- Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software SolutionsMirko Loghi, Massimo Poncino. 508-513 [doi]
- Quasi-Static Voltage Scaling for Energy Minimization with Time ConstraintsAlexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi. 514-519 [doi]
- Tag Overflow Buffering: An Energy-Efficient Cache ArchitectureMirko Loghi, Paolo Azzoni, Massimo Poncino. 520-525 [doi]
- Q-DPM: An Efficient Model-Free Dynamic Power Management TechniqueMin Li, Xiaobo Wu, Richard Yao, Xiaolang Yan. 526-527 [doi]
- Hardware Accelerated Power EstimationJoel Coburn, Srivaths Ravi, Anand Raghunathan. 528-529 [doi]
- Integrated Electronics in the Car and the Design Chain Evolution or Revolution?Alberto L. Sangiovanni-Vincentelli. 532-533
- A New Approach to Component TestingHorst Brinkmeyer. 534-535 [doi]
- Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM PerspectiveThomas Illgen, Stefan Ortmann. 536-537
- Embedded Automotive System Development ProcessJoachim Langenwalter. 538-539 [doi]
- Functional Validation of System Level Static SchedulingSamar Abdi, Daniel D. Gajski. 542-547 [doi]
- Defining an Enhanced RTL SemanticsShuqing Zhao, Daniel D. Gajski. 548-553 [doi]
- RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemCM. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 554-559 [doi]
- Design for Verification of SystemC Transaction Level ModelsAli Habibi, Sofiène Tahar. 560-565 [doi]
- Systematic Transaction Level Modeling of Embedded Systems with SystemCWolfgang Klingauf. 566-567 [doi]
- Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring ArchitecturesSohini Dasgupta, Alexandre Yakovlev. 568-569 [doi]
- Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark?Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel. 572
- An Efficient Transparent Test Scheme for Embedded Word-Oriented MemoriesJin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey. 574-579 [doi]
- On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable MemoriesLuca Schiano, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano. 580-585 [doi]
- Increasing Register File Immunity to Transient ErrorsGokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk. 586-591 [doi]
- An Efficient BICS Design for SEUs Detection and Correction in Semiconductor MemoriesBalkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou, Steven L. Garverick. 592-597 [doi]
- nfluence of Memory Hierarchies on Predictability for Time Constrained Embedded SoftwareLars Wehmeyer, Peter Marwedel. 600-605 [doi]
- utomatic Timing Model Generation by CFG Partitioning and Model CheckingIngomar Wenzel, Bernhard Rieder, Raimund Kirner, Peter P. Puschner. 606-611 [doi]
- A Contribution to Branch Prediction Modeling in WCET AnalysiClaire Burguière, Christine Rochange. 612-617 [doi]
- erifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract InterpretationReinhold Heckmann, Christian Ferdinand. 618-619 [doi]
- An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing PlatformsJawad Khan, Ranga Vemuri. 622-627 [doi]
- Design Method for Constant Power Consumption of Differential Logic CircuitsKris Tiri, Ingrid Verbauwhede. 628-633 [doi]
- Exploiting Dynamic Workload Variation in Low Energy Preemptive Task SchedulingLap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu. 634-639 [doi]
- Low Power Oriented CMOS Circuit Optimization ProtocolAlexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne. 640-645 [doi]
- Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power ReductionTakeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa. 646-647 [doi]
- Hotspot Prevention Through Runtime Reconfiguration in Network-On-ChipGreg M. Link, Narayanan Vijaykrishnan. 648-649 [doi]
- Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total LeakageRobert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge. 650-651 [doi]
- Automotive System Architectures (Automotive Special Day)Jürgen Bortolazzi, J.-L. Maté, J. Becker, C. Morgano. 654
- Automotive System Design - Challenges and PotentialHarald Heinecke. 656-657 [doi]
- Effective Lower Bounding Techniques for Pseudo-Boolean OptimizationVasco M. Manquinho, João P. Marques Silva. 660-665 [doi]
- Efficient Conflict-Based Learning in an RTL Circuit Constraint SolverMadhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng. 666-671 [doi]
- A Faster Counterexample Minimization Algorithm Based on Refutation AnalysisShengYu Shen, Ying Qin, Sikun Li. 672-677 [doi]
- Functional Coverage Driven Test Generation for Validation of Pipelined ProcessorsPrabhat Mishra, Nikil D. Dutt. 678-683 [doi]
- Pueblo: A Modern Pseudo-Boolean SAT SolverHossein M. Sheini, Karem A. Sakallah. 684-685 [doi]
- Space-Efficient Bounded Model CheckingJacob Katz, Ziyad Hanna, Nachum Dershowitz. 686-687 [doi]
- Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model CheckingGianpiero Cabodi, Marco Crivellari, Sergio Nocco, Stefano Quer. 688-689 [doi]
- A Model-Based Approach for Executable Specifications on Reconfigurable HardwareTim Schattkowsky, Wolfgang Müller 0003, Achim Rettberg. 692-697 [doi]
- The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio ApplicationAlexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid. 698-703 [doi]
- A SoC Design Methodology Involving a UML 2.0 Profile for SystemCElvinia Riccobene, Patrizia Scandurra, Alberto Rosti, Sara Bocchio. 704-709 [doi]
- UML 2.0 Profile for Embedded System DesignPetri Kukkala, Jouni Riihimäki, Marko Hännikäinen, Timo D. Hämäläinen, Klaus Kronlöf. 710-715 [doi]
- UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC DesignYves Vanderperren, Wim Dehaene. 716-717 [doi]
- Design Refinement for Efficient Cluste ing of Objects in Embedded SystemsWaseem Ahmed, Doug Myers. 718-719 [doi]
- Challenges in Embedded Memory Design and TestErik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian. 722-727 [doi]
- Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW ArchitecturesAnup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar. 730-735 [doi]
- Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory ArchitectureFrancesco Poletti, Antonio Poggiali, Paul Marchal. 736-741 [doi]
- Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing CompilerAndré C. Nácul, Tony Givargis. 742-747 [doi]
- Multithreaded Extension to Multicluster VLIW Processors for Embedded ApplicationsDomenico Barretta, William Fornaciari, Mariagiovanna Sami, Daniele Bagni. 748-749 [doi]
- An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit SimulationZhao Li, C.-J. Richard Shi. 752-757 [doi]
- Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit DesignBharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang. 758-763 [doi]
- Statistical Timing Analysis using Levelized Covariance PropagationKunhyuk Kang, Bipul Chandra Paul, Kaushik Roy. 764-769 [doi]
- A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input SwitchingY. Satish Kumar, Jun Li, Claudio Talarico, Janet Meiling Wang. 770-775 [doi]
- Modeling and Propagation of Noisy Waveforms in Static Timing AnalysisShahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin, Amir H. Ajami. 776-777 [doi]
- A Network Traffic Generator Model for Fast Network-on-Chip SimulationShankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen. 780-785 [doi]
- Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator GenerationMehrdad Reshadi, Nikil D. Dutt. 786-791 [doi]
- Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCsJürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel. 792-797 [doi]
- Virtual Hardware Prototyping through Timed Hardware-Software Co-SimulationFranco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino. 798-803 [doi]
- Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-ChipOreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo. 804-805 [doi]
- FORAY-GEN: Automatic Generation of Affine Functions for Memory OptimizationsIlya Issenin, Nikil D. Dutt. 808-813 [doi]
- Nonuniform Banking for Reducing Memory Energy ConsumptionOzcan Ozturk, Mahmut T. Kandemir. 814-819 [doi]
- Systematic Analysis of Active Clock Deskewing Systems Using Control TheoryVinil Varghese, Tom Chen, Peter Michael Young. 820-825 [doi]
- Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-ChipSankalp Kallakuri, Alex Doboli, Eugene A. Feinberg. 826-827 [doi]
- Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad MemoryPu Hanlai, Ling Ming, Jin Jing. 828-829 [doi]
- UML 2.0 - Overview and Perspectives in SoC DesignTim Schattkowsky. 832-833 [doi]
- Why Systems-on-Chip Needs More UML like a Hole in the HeadStephen J. Mellor, John R. Wolfe, Campbell McCausland. 834-835 [doi]
- Integrating UML into SoC Design ProcessQiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata. 836-837 [doi]
- Rapid Generation of Thermal-Safe Test SchedulesPaul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty. 840-845 [doi]
- Simultaneous Reduction of Dynamic and Static Power in Scan StructuresShervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi. 846-851 [doi]
- A Fast Diagnosis Scheme for Distributed Small Embedded SRAMsBaosheng Wang, Yuejian Wu, André Ivanov. 852-857 [doi]
- New Schemes for Self-Testing RAMGhenadie Bodean, D. Bodean, A. Labunetz. 858-859 [doi]
- At-Speed Logic BIST for IP CoresB. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu. 860-861 [doi]
- Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded SystemsViacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng. 864-869 [doi]
- Locality-Aware Process Scheduling for Embedded MPSoCsMahmut T. Kandemir, Guilin Chen. 870-875 [doi]
- A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC PlatformsTorsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout. 876-881 [doi]
- Access Pattern-Based Code Compression for Memory-Constrained Embedded SystemsOzcan Ozturk, Hendra Saputra, Mahmut T. Kandemir, Ibrahim Kolcu. 882-887 [doi]
- System Synthesis for Networks of Programmable BlocksRyan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid. 888-893 [doi]
- Distributed HW/SW-Partitioning for Embedded Reconfigurable NetworksThilo Streichert, Christian Haubelt, Jürgen Teich. 894-895 [doi]
- Synchronization Processor Synthesis for Latency Insensitive SystemsPierre Bomel, Eric Martin, Emmanuel Boutillon. 896-897 [doi]
- Thermal-Aware Task Allocation and Scheduling for Embedded SystemsWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 898-899 [doi]
- An Improved Multi-Level Framework for Force-Directed PlacementKristofer Vorwerk, Andrew A. Kennings. 902-907 [doi]
- Bright-Field AAPSM Conflict Detection and CorrectionCharles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky. 908-913 [doi]
- Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM ModulesHua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex. 914-919 [doi]
- TSUNAMI: An Integrated Timing-Driven Place And Route Research PlatformChristophe Alexandre, Hugo Clément, Jean-Paul Chaput, Marek Sroka, Christian Masson, Remy Escassut. 920-921 [doi]
- Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment MetricAmitava Bhaduri, Ranga Vemuri. 922-923 [doi]
- Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm TechnologiesAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy. 926-931 [doi]
- Compositional Memory Systems for Multimedia Communicating TasksAnca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven. 932-937 [doi]
- Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design ProcessesJudita Kruse, Clive Thomsen, Rolf Ernst, Thomas Volling, Thomas Spengler. 938-943 [doi]
- A New System Design Methodology for Wire Pipelined SoCMario R. Casu, Luca Macchiarulo. 944-945 [doi]
- A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy BottleneckMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. 946-947 [doi]
- Is there a Market for SystemC Tools?Wolfgang Rosenstiel, Reinaldo A. Bergamaschi, Frank Ghenassia, Thorsten Groetker, Masamichi Kawarabayashi, Marinus C. van Lier, Albrecht Mayer, Mike Meredith, Mark Milligan, Stuart Swan. 950
- Statistical Timing Analysis with Extended Pseudo-Canonical Timing ModelLizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen. 952-957 [doi]
- Modeling Interconnect Variability Using Efficient Parametric Model Order ReductionPeng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif. 958-963 [doi]
- Stochastic Power Grid Analysis Considering Process VariationsPraveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang. 964-969 [doi]
- Buffer Insertion Considering Process VariationJinjun Xiong, King Ho Tam, Lei He. 970-975 [doi]
- EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment FormulationBaohua Wang, Pinaki Mazumder. 976-981 [doi]
- Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise AnalysisCristiano Forzan, Davide Pandini. 982-983 [doi]
- Performance Driven Decoupling Capacitor Allocation Considering Data and Clock InteractionsAjith Chandy, Tom Chen. 984-985 [doi]
- Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing OptimizationPaul Zuber, Armin Windschiegl, Raúl Medina Beltán de Otálora, Walter Stechele, Andreas Herkersdorf. 986-987 [doi]
- Implicit and Exact Path Delay Fault Grading in Sequential CircuitsMahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi. 990-995 [doi]
- Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom DesignsYu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman. 996-1001 [doi]
- Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test GenerationKameshwar Chandrasekar, Michael S. Hsiao. 1002-1007 [doi]
- The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan CircuitsIrith Pomeranz, Sudhakar M. Reddy. 1008-1013 [doi]
- Diagnostic and Detection Fault Collapsing for Multiple Output CircuitsRaja K. K. R. Sandireddy, Vishwani D. Agrawal. 1014-1019 [doi]
- Framework for Fault Analysis and Test Generation in DRAMsZaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor. 1020-1021 [doi]
- Mutation Sampling Technique for the Generation of Structural Test DataMathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. 1022-1023 [doi]
- Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded ProcessingMahmut T. Kandemir, Feihui Li, Guilin Chen, Guangyu Chen, Ozcan Ozturk. 1026-1031 [doi]
- BB-GC: Basic-Block Level Garbage CollectionOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin. 1032-1037 [doi]
- Fine Grain QoS Control for Multimedia Application SoftwareJacques Combaz, Jean-Claude Fernandez, Thierry Lepley, Joseph Sifakis. 1038-1043 [doi]
- Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software DevelopmentMassimo Baleani, Alberto Ferrari, Leonardo Mangeruca, Alberto L. Sangiovanni-Vincentelli, Ulrich Freund, Erhard Schlenker, Hans-Jörg Wolff. 1044-1049 [doi]
- galsC: A Language for Event-Driven Embedded SystemsElaine Cheong, Jie Liu. 1050-1055 [doi]
- Compiler-Directed Instruction Duplication for Soft Error DetectionJie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. 1056-1057 [doi]
- OS Debugging Method Using a Lightweight Virtual Machine MonitorTadashi Takeuchi. 1058-1059 [doi]
- Hardware Support for Arbitrarily Complex Loop Structures in Embedded ApplicationsNikolaos Kavvadias, Spiridon Nikolaidis. 1060-1061 [doi]
- Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog CircuitsAbhishek Somani, Partha Pratim Chakrabarti, Amit Patra. 1064-1069 [doi]
- Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance HypersurfacesTom Eeckelaert, Trent McConaghy, Georges G. E. Gielen. 1070-1075 [doi]
- Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables FrameworkGerd Vandersteen, Ludwig De Locht, Snezana Jenei, Yves Rolain, Rik Pintelon. 1076-1081 [doi]
- CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic ProgrammingTrent McConaghy, Tom Eeckelaert, Georges G. E. Gielen. 1082-1087 [doi]
- A Two-Level Modeling Approach to Analog Circuit Performance MacromodelingMengmeng Ding, Ranga Vemuri. 1088-1089 [doi]
- New Perspectives and Opportunities From the Wild West of Microelectronic BiochipsNicolò Manaresi, Gianni Medoro, Melanie Abonnenc, Vincent Auger, Paul Vulto, Aldo Romani, Luigi Altomare, Marco Tartagni, Roberto Guerrieri. 1092-1093 [doi]
- Verification of Embedded Memory Systems using Efficient Memory ModelingMalay K. Ganai, Aarti Gupta, Pranav Ashar. 1096-1101 [doi]
- An Efficient Sequential SAT Solver With Improved Search StrategiesFeng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen. 1102-1107 [doi]
- Considering Circuit Observability Don t Cares in CNF SatisfiabilityZhaohui Fu, Yinlei Yu, Sharad Malik. 1108-1113 [doi]
- Integration, Verification and Layout of a Complex Multimedia SOCChien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin. 1116-1117 [doi]
- PEG, MPEG-4, and H.264 Codec IP DevelopmentChung-Jr Lian, Yu-Wen Huang, Hung-Chi Fang, Yung-Chi Chang, Liang-Gee Chen. 1118-1119 [doi]
- SOC Testing Methodology and PracticeCheng-Wen Wu. 1120-1121 [doi]
- Evolutionary Optimization in Code-Based Test CompressionIlia Polian, Alejandro Czutro, Bernd Becker. 1124-1129 [doi]
- Reconfigurable Linear Decompressors Using Symbolic Gaussian EliminationKedarnath J. Balakrishnan, Nur A. Touba. 1130-1135 [doi]
- A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test ApplicationSwarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy. 1136-1141 [doi]
- Hybrid BIST Based on Repeating Sequences and Cluster AnalysisLei Li, Krishnendu Chakrabarty. 1142-1147 [doi]
- C Compiler Retargeting Based on Instruction Semantics ModelsJianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun. 1150-1155 [doi]
- A Constraint Network Based Approach to Memory Layout OptimizationGuilin Chen, Mahmut T. Kandemir, Mustafa Karaköy. 1156-1161 [doi]
- Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array AccessMohammed Javed Absar, Francky Catthoor. 1162-1167 [doi]
- Structural Testing Based on Minimum KernelsElena Dubrova. 1168-1173 [doi]
- An Application-Specific Design Methodology for STbus Crossbar GenerationSrinivasan Murali, Giovanni De Micheli. 1176-1181 [doi]
- A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and VerificationKees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema. 1182-1187 [doi]
- ast pipes Lite: A Synthesis Oriented Design Library For Networks on ChipsStergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli. 1188-1193 [doi]
- Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local ReconfigurationFei Su, Krishnendu Chakrabarty, Vamsee K. Pamula. 1196-1201 [doi]
- Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic BiochipsFei Su, Krishnendu Chakrabarty. 1202-1207 [doi]
- Quantum Circuit Simplification Using TemplatesDmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck. 1208-1213 [doi]
- owards Designing Robust QCA Architectures in the Presence of Sneak Noise PathsKyosun Kim, Kaijie Wu, Ramesh Karri. 1214-1219 [doi]
- CMOS-Based Biosensor ArraysRoland Thewes, Christian Paulus, Meinrad Schienle, Franz Hofmann, Alexander Frey, Ralf Brederlow, M. Augustyniak, Martin Jenkner, Björn Eversmann, Petra Schindler-Bauer, Melanie Atzesberger, Birgit Holzapfl, Gottfried Beer, Thomas Haneder, Hans-Christian Hanke. 1222-1223 [doi]
- A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-ChipTobias Bjerregaard, Jens Sparsø. 1226-1231 [doi]
- A Quality-of-Service Mechanism for Interconnection Networks in System-on-ChipsWolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew Wingard. 1232-1237 [doi]
- A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip NetworksHangsheng Wang, Li-Shiuan Peh, Sharad Malik. 1238-1243 [doi]
- ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative ImprovementPartha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne. 1246-1251 [doi]
- Behavioural Transformation to Improve Circuit Performance in High-Level SynthesisRafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida. 1252-1257 [doi]
- Reliability-Centric High-Level SynthesisSuleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie. 1258-1263 [doi]
- PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded ProcessorsAviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie. 1264-1269 [doi]
- Concurrent Error Detection in Asynchronous Burst-Mode ControllersSobeeh Almukhaizim, Yiorgos Makris. 1272-1277 [doi]
- Reliable System Specification for Self-Checking Data-PathsCristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante. 1278-1283 [doi]
- Evaluation of Error-Resilience for Reliable Compression of Test DataHamidreza Hashempour, Luca Schiano, Fabrizio Lombardi. 1284-1289 [doi]
- On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAsFernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda. 1290-1295 [doi]
- Automatic Formal Verification of Fused-Multiply-Add FPUsChristian Jacobi 0002, Kai Weber, Viresh Paruthi, Jason Baumgartner. 1298-1303 [doi]
- Refinement Maps for Efficient Verification of Processor ModelsPanagiotis Manolios, Sudarshan K. Srinivasan. 1304-1309 [doi]
- Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source CodeK. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens. 1310-1315 [doi]
- Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data TransmissionBrock J. LaMeres, Sunil P. Khatri. 1318-1323 [doi]
- An O(bn:::2:::) Time Algorithm for Optimal Buffer Insertion with b Buffer TypesZhuo Li, Weiping Shi. 1324-1329 [doi]
- RIP: An Efficient Hybrid Repeater Insertion Scheme for Low PowerXun Liu, Yuantao Peng, Marios C. Papaefthymiou. 1330-1335 [doi]
- eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical DetectionRaymond Campagnolo. 1338-1339 [doi]
- Cantilever-Based Biosensors in CMOS TechnologyKay-Uwe Kirstein, Yue Li, Martin Zimmermann, Cyril Vancura, Tormod Volden, Wan Ho Song, Jan Lichtenberg, Andreas Hierlemann. 1340-1341 [doi]