Abstract is missing.
- Fast global motion estimation for sprite generationHoi-Kok Cheung, Wan-Chi Siu. 1-4 [doi]
- A systematic technique for optimizing multiple branch FIR filters for sampling rate conversionPeyman Arian, Tapio Saramäki, S. K. Mitra. 1-4 [doi]
- An analysis of noise in timing-based communications over local area networksJ. B. Miller, John C. McEachen, H. H. Loomis Jr., Michael A. Tope, D. B. Copeland. 1-4 [doi]
- On power allocation for generalized cyclic-prefix based channel-equalizersPalghat P. Vaidyanathan, Bojan Vrcelj. 1-4 [doi]
- Implementation of the transposed Farrow structureDjordje Babic, J. Vesma, Tapio Saramäki, Markku Renfors. 5-8 [doi]
- A novel predictive global motion estimation for video codingWing Cheong Chan, Oscar C. Au, Ming Fai Fu. 5-8 [doi]
- An improved peak-to-average-power ratio reduction algorithm for multicarrier communicationsYajun Kou, Wu-Sheng Lu, Andreas Antoniou. 5-8 [doi]
- PPFPS - a paraboloid prediction based fractional pixel search strategy for H.26LZhibo Chen, Cheng Du, Jinghua Wang, Yun He. 9-12 [doi]
- Subspace estimation-based constrained optimization method for multipath CDMA channelsX. M. Wang, Wu-Sheng Lu, Andreas Antoniou. 9-12 [doi]
- Fractional biorthogonal partners and application in signal interpolationBojan Vrcelj, P. P. Vaidyanathan. 9-12 [doi]
- An array based technique for routing messages in distributed double loop networksR. Katti, V. V. Bapeswara Rao. 9-12 [doi]
- Low-band-shift (LBS) motion estimation with symmetric padding in wavelet domainMing Fai Fu, Oscar C. Au, Wing Cheong Chan. 13-16 [doi]
- Enhancing robustness of information hiding against interference of communication with turbo codeJie Yang, Moon Ho Lee, Ju Yong Park. 13-16 [doi]
- Multiplier-less implementation of linear phase cosine modulated filter banks with composite channel numberP. M. Yiu, S. C. Chan. 13-16 [doi]
- Analysis of hardlimiting parallel interference cancellation (PIC) for synchronous CDMA communicationYu-Nan Lin, David W. Lin. 13-16 [doi]
- Using SDL a tool for system simulationsA. Laitinen, Marko Hännikäinen, Timo Hämäläinen. 17-20 [doi]
- Link adaptation and receiver design for enhanced General Packet Radio Services wireless networksQilian Liang. 17-20 [doi]
- Lifting based integer wavelet transform with binary coefficientsDavid B. H. Tay. 17-20 [doi]
- Successive packing based interleaver design for turbo codesX. Zhang, Yun Q. Shi, Hangjun Chen, Alexander M. Haimovich, Anthony Vetro, Huifang Sun. 17-20 [doi]
- A 50 duty-cycle correction circuit for PLL outputT. Gawa, K. Taniguchi. 21-24 [doi]
- Large-signal time-domain simulation of class-E amplifierW. Pietrenko, W. Janke, A. K. Kazimierczuk. 21-24 [doi]
- A parallel fast algorithm of Volterra adaptive filtersK. Takeichi, T. Furukawa. 21-24 [doi]
- Bandwidth utilization and signal strength-based handover initiation in mobile multimedia cellular networksQilian Liang. 21-24 [doi]
- An improved stochastic model for the least mean fourth (LMF) adaptive algorithmPedro Inácio Hübscher, José Carlos M. Bermudez. 25-28 [doi]
- Local resource management of distributed sensor networks via static output feedback controlJ. Zhang, Kamal Premaratne, Peter H. Bauer. 25-28 [doi]
- Performance evaluation of Secure Remote Password protocolPanu Hämäläinen, Marko Hännikäinen, Markku Niemi, Timo Hämäläinen. 29-32 [doi]
- Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD methodI. Hattori, A. Kamo, T. Watanabe, H. Asai. 29-32 [doi]
- A 22-mW 435-MHz differential CMOS high-gain LNA for subsampling receiversT.-H. Huang, Ertan Zencir, Numan Sadi Dogan, Andrea Arvas. 29-32 [doi]
- Network optimization problem in tie-set flow vector space and information network resource managementT. Koide, T. Ishibashi, H. Watanabe. 33-36 [doi]
- Learning characteristics of adaptive fault tolerant filters in the presence of transient errorsR. S. Srivatsa, W. Kenneth Jenkins. 33-36 [doi]
- A 10-mW 435-MHz differential CMOS LNA for low-IF receivers in space applicationsErtan Zencir, Numan Sadi Dogan, Ercument Arvas. 33-36 [doi]
- Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)Lan-Da Van, Chih-Hong Chang. 37-40 [doi]
- A monolithic low power pulsed optical encoderNicola Massari, Lorenzo Gonzo, Massimo Gottardi, Andrea Simoni. 37-40 [doi]
- A new method for efficient time-domain simulation of power electronic circuitsErnesto Chiarantoni, Girolamo Fornarelli, Silvano Vergura. 37-40 [doi]
- A new detector architecture for optical pickup units in DVD systemsI. Hehemann, W. Brockherde, A. Bussmann, H. Hofmann, A. Kemna, R. Kokozinski, H. Richter, Bedrich J. Hosticka. 41-44 [doi]
- Leveraged current mirror op ampRobert M. Fox, Inchang Seo, H. Yeo, O. Jeon. 41-44 [doi]
- Design method for optimal step size matrix of the affine projection algorithm using semidefinite programmingK. Konishi, K. Okuyama, A. Kato, T. Furukawa. 41-44 [doi]
- Third-generation and beyond (3.5G) wireless networks and its applicationsR. C. Qiu, Wenwu Zhu, Ya-Qin Zhang. 41-44 [doi]
- Enhanced adaptive sparse algorithms using the Haar waveletDominic K. C. Ho, Shannon D. Blunt. 45-48 [doi]
- Adaptive playout for real-time media streamingMark Kalman, Eckehard G. Steinbach, Bernd Girod. 45-48 [doi]
- A robust edge detector for motion detectionGuangbin Zhang, Jin Liu. 45-48 [doi]
- New adaptive Kalman filters using filter bankK. Okuyama, S. Yoshimoto, T. Furukawa. 49-52 [doi]
- A high-performance, low-voltage, body-driven CMOS current mirrorXuguang Zhang, Ezz I. El-Masry. 49-52 [doi]
- Robust video multicast under rate and channel variability with applications to wireless LANsAbhik Majumdar, Rohit Puri, Kannan Ramchandran, Igor Kozintsev. 49-52 [doi]
- New pixel-shared design and split-path readout of CMOS image sensor circuitsHwang-Cherng Chow, Yung-Kuo Ho. 49-52 [doi]
- A CMOS imager with PFM/PWM based analog-to-digital converterAmine Bermak. 53-56 [doi]
- Adaptive end-to-end optimization of mobile video streaming using QoS negotiationJacco R. Taal, Koen Langendoen, Arjen van der Schaaf, Hylke W. van Dijk, Reginald L. Lagendijk. 53-56 [doi]
- A low-voltage high-speed BiCMOS current switch with enhanced-spectral performanceKwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang. 53-56 [doi]
- Current-mode leapfrog ladder filters using CDBAsWorapong Tangsrirat, Nobuo Fujii, Wanlop Surakampontorn. 57-60 [doi]
- Clustering in globally coupled system of chaotic circuitsM. Miyamura, Yoshifumi Nishio, Akio Ushida. 57-60 [doi]
- Video transport over ad-hoc networks using multiple pathsShunan Lin, Yao Wang, Shiwen Mao, Shivendra S. Panwar. 57-60 [doi]
- Error robust video transmission over wireless IP networks with multiuser detectionYong Sun, Shengjie Zhao, Zixiang Xiong, Xiaodong Wang. 61-64 [doi]
- Parameter optimization tool for enhancing on-chip network performanceJouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo Hämäläinen. 61-64 [doi]
- On-chip spectrum analyzer for built-in testing analog ICsMarcia G. Méndez-Rivera, José Silva-Martínez, Edgar Sánchez-Sinencio. 61-64 [doi]
- Generalized synchronization on linear manifold in coupled nonlinear systemsSilvano Cincotti, Andrea Teglio. 61-64 [doi]
- Compact continuous-time analog rank-order filter implementation in CMOS technologyJaime Ramírez-Angulo, C. Lackey, Alejandro Díaz-Sánchez. 65-68 [doi]
- A generalized methodology for lower-error area-efficient fixed-width multipliersLan-Da Van, Sung-Huang Lee. 65-68 [doi]
- Chaotic system reconstruction from noisy time series measurements using improved least squares genetic programmingVinay Varadan, Henry Leung. 65-68 [doi]
- Design of low error CSD fixed-width multiplierSang-Min Kim, Jin-Gyun Chung, Keshab K. Parhi. 69-72 [doi]
- Antisymmetries in the realization of Boolean functionsJacqueline E. Rice, Jon C. Muzio. 69-72 [doi]
- An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channelsAndrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, M. Bruccoleri, G. Betti. 69-72 [doi]
- Mapping atoms to nonlinear Chua s circuitsR. Tonelli, Leon O. Chua, F. Meloni. 69-72 [doi]
- Memory exploration utilizing scheduling effects in high-level synthesisJaewon Seo, Taewhan Kim. 73-76 [doi]
- CMOS circuit design and implementation of the discrete time chaotic chipHan Jung Song, Kae-Dal Kwack. 73-76 [doi]
- Neuromorphic noise shaping in coupled neuron populationsJ. T. Marienborg, Tor Sverre Lande, Mats Erling Høvin. 73-76 [doi]
- The use of reduced two s-complement representation in low-power DSP designZhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.. 77-80 [doi]
- Empirical comparison of analog and digital auditory preprocessing for automatic speech recognitionT. M. Massengill, D. M. Wilson, Paul E. Hasler, David W. Graham. 77-80 [doi]
- Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptionsJ. A. Lopez, G. Domenech, R. Ruiz, Tom J. Kazmierski. 77-80 [doi]
- CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay networkChih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu. 77-80 [doi]
- A superregenerative receiver for phase and frequency modulated carriersLuis Hernández, Susanna Patón. 81-84 [doi]
- Static timing analysis based circuit-limited-yield estimationAnne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long. 81-84 [doi]
- A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliersM.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu. 81-84 [doi]
- Maximum achievable energy reduction using coding with applications to deep sub-micron busesPaul-Peter Sotiriadis, Anantha Chandrakasan, Vahid Tarokh. 85-88 [doi]
- Regression criteria and their application in different modeling casesFrancky Leyn, Erik Lauwers, Martin Vogels, Georges G. E. Gielen, Willy M. C. Sansen. 85-8 [doi]
- A novel analysis method of bus signal transmission and a proposal for high-speed low-power bus circuitS. Saito. 89-92 [doi]
- A new methodology for the statistical analysis of VLSI CMOS circuits and its application to flash memoriesMassimo Conti, Paolo Crippa, Simone Orcioni, M. Pesare, Claudio Turchetti, Loris Vendrame, S. Lucherini. 89-92 [doi]
- A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA)Kwang-Jin Koh, Yong-Sik Youn, Hyun-Kyu Yu. 89-92 [doi]
- Low power register file architecture for application specific DSPsMatthias Müller, Andreas Wortmann, Sven Simon, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek. 89-92 [doi]
- Mismatch-induced tradeoffs and scalability of mixed-signal vision chipsÁngel Rodríguez-Vázquez, Gustavo Liñán, Servando Espejo-Meana, Rafael Domínguez-Castro. 93-96 [doi]
- Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant codingDavide Bertozzi, Luca Benini, Bruno Riccò. 93-96 [doi]
- On the global robust stability of delayed neural networksSabri Arik, Vedat Tavsanoglu. 93-96 [doi]
- Low-power multipliers by minimizing switching activities of partial productsNan-Ying Shen, Oscal T.-C. Chen. 93-96 [doi]
- Oscillatory hysteresis associative memoryK. Jin no. 97-100 [doi]
- A novel list-scheduling algorithm for the low-energy program executionG. Sinevriotis, Thanos Stouraitis. 97-100 [doi]
- On dynamic delay and repeater insertionHannu Tenhunen, Dinesh Pamunuwa. 97-100 [doi]
- Resistors layout for enhancing yield of R-2R DACsYu Lin, Randall L. Geiger. 97-100 [doi]
- Implementation oriented theory design issues on the DTCNN template generationVictor M. Brea, David López Vilariño, Ari Paasio, Diego Cabello. 101-104 [doi]
- A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applicationsBill Pontikakis, Mohamed Nekili. 101-104 [doi]
- Inductance/area/resistance tradeoffs in high performance power distribution gridsAndrey V. Mezhiba, Eby G. Friedman. 101-104 [doi]
- An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applicationsSeyed Reza Abdollahi, S. Kiaei, B. Bakkaloglu, Seid Mehdi Fakhraie, R. Anvari, S. E. Abdollahi. 101-104 [doi]
- Comparative analysis of double-edge versus single-edge triggered clocked storage elementsNikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija. 105-108 [doi]
- Enlarging neural class detection capacity in passive sonar systemsWilliam Soares-Filho, José Manoel de Seixas, Luiz Pereira Calôba. 105-108 [doi]
- A necessary and sufficient condition for mismatch shaping in multi-bit DACsJ. Welz, Ian Galton. 105-108 [doi]
- FIR filters for compensating D/A converter frequency response distortionJouko Vankka, Jonne Lindeberg, Kari Halonen. 105-108 [doi]
- Nonsymmetric PDF approximation by artificial neurons: application to statistical characterization of reinforced compositesSimone Fiori, Pietro Burrascano. 109-112 [doi]
- Correction of transmitter gain and phase errors at the receiverEdiz Çetin, Izzet Kale, Richard C. S. Morling. 109-112 [doi]
- Design of oversampling current steering DAC with 640 MHz equivalent clock frequencyYunyoung Choi, Franco Maloberti. 109-112 [doi]
- Simplified current and delay models for deep submicron CMOS digital circuitsMohammad M. Mansour, Naresh R. Shanbhag. 109-112 [doi]
- A differential DAC architecture with variable common-mode levelK. Ola Andersson, N. U. Andersson, Mark Vesterbacka, J. Jacob Wikner. 113-116 [doi]
- Self-timed MOS current mode logic for digital applicationsMohab Anis, Mohamed I. Elmasry. 113-116 [doi]
- A dual-band RF front-end for WCDMA and GPS applicationsMin-Yi Wang, R. R.-B. Sheen, Oscal T.-C. Chen, R. Y. J. Tsen. 113-116 [doi]
- Binary image rotation using cellular neural networksQun Gao, P. Messmer, George S. Moschytz. 113-116 [doi]
- The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniquesYu-Yee Liow, Chung-Yu Wu. 117-120 [doi]
- A general analysis on the timing jitter in D/A convertersKonstantinos Doris, Arthur H. M. van Roermund, Domine Leenaerts. 117-120 [doi]
- RF gain control in direct conversion receiversJussi Ryynänen, Kalle Kivekäs, Jarkko Jussila, A. Parssinen, Kari Halonen. 117-120 [doi]
- A 10-bit 100-MS/s 50 mW CMOS A/D converterZ. Tao, M. Keramat. 121-124 [doi]
- Design of a new signal security systemJui-Cheng Yen, Jiun-In Guo. 121-124 [doi]
- A 14-bit, 40-MS/s DAC with current mode deglitcherJussi Pirkkalaniemi, Marko Waltari, Mikko Kosunen, Lauri Sumanen, Kari Halonen. 121-124 [doi]
- A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communicationYew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, Chen-Yi Lee. 121-124 [doi]
- A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applicationsKoon Hung Lee, Mourad N. El-Gamal. 125-128 [doi]
- A novel adaptive algorithm applied to a class of redundant representation vector quantizers for waveform and model based codingV. Krishnan, Wasfy B. Mikhael. 125-128 [doi]
- A single-chip real-time programmable video signal processorLingfeng Li, Danian Gong, Yun He. 129-132 [doi]
- Charge sampling mixer with Delta-Sigma quantized impulse responseSami Karvonen, Tom A. D. Riley, Juha Kostamovaara. 129-132 [doi]
- Measurement verification of estimation method for time errors in a time-interleaved A/D converter systemJonas Elbornsson, K. Folkesson, Jan-Erik Eklund. 129-132 [doi]
- A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-µm CMOSJ. Talebzadeh, M. R. Hasanzadeh, Mohammad Yavari, Omid Shoaei. 133-136 [doi]
- High-speed memory-saving architecture for the embedded block coding in JPEG2000Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen. 133-136 [doi]
- A high throughput context-based adaptive arithmetic codec for JPEG2000Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee. 133-136 [doi]
- GHz programmable dual-modulus prescaler for multi-standard wireless applicationsHong Jo Ahn, M. Ismail. 137-140 [doi]
- An adaptive Viterbi algorithm based on strongly connected trellis decodingMan Guo, M. Omair Ahmad, M. N. S. Swamy, Chunyan Wang. 137-140 [doi]
- An associative-processor-based mixed signal system for robust grayscale image recognitionM. Yagi, T. Shibata. 137-140 [doi]
- Content-based video retrieval using motion descriptors extracted from compressed domainR. Venkatesh Babu, K. R. Ramakrishnan. 141-144 [doi]
- A direct digital RF amplitude modulatorYijun Zhou, Jiren Yuan. 141-144 [doi]
- An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCsPedro Amaral, João Goes, Nuno F. Paulino, Adolfo Steiger-Garção. 141-144 [doi]
- A current steering CMOS folding amplifierWeidong Guo, R. J. Huber, K. F. Smith. 141-144 [doi]
- Region-based relevance feedback in image retrievalFeng Jing, Mingjing Li, HongJiang Zhang, Bo Zhang. 145-148 [doi]
- Matching considerations in I/Q A/D converter pairsCharles T. Peach, Waisiu Law, D. R. Beck, Ward J. Helms, David J. Allstot. 145-148 [doi]
- SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technologyA. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis. 145-148 [doi]
- Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standardG. O. D. Acevedo, Jaime Ramírez-Angulo. 149-152 [doi]
- A neural network approach for fault diagnosis of large-scale analogue circuitsYigang He, Yanghong Tan, Yichuang Sun. 153-156 [doi]
- A lifting based system for optimal compression and classification in the JPEG2000 frameworkGamal Fahmy, Sethuraman Panchanathan. 153-156 [doi]
- Locating stuck faults in analog circuitsJanusz A. Starzyk, D. Liu. 153-156 [doi]
- Charge-based MOS correlated double sampling comparator and folding circuitRoman Genov, Gert Cauwenberghs. 153-156 [doi]
- Efficient content-based CT brain image retrieval by using region shape featuresWen-Nung Lie, Wen-Hung Peng, Cheng-Hung Chuang. 157-160 [doi]
- A decomposition method for analog fault locationJanusz A. Starzyk, D. Liu. 157-160 [doi]
- CMOS dynamic comparators for pipeline A/D convertersLauri Sumanen, Mikko Waltari, Väinö Hakkarainen, Kari Halonen. 157-160 [doi]
- Concept of phase-noise tuning of bipolar voltage-controlled oscillatorsAleksandar Tasic, Wouter A. Serdijn. 161-164 [doi]
- Fault location of single-phase transmission lines by Laguerre functionA. Yonemoto, Takashi Hisakado, Kohshi Okumura. 161-164 [doi]
- A fault tolerant incremental design methodologyS. Cailotto, Alessandro Fin, Franco Fummi. 161-164 [doi]
- A cellular nonlinear approach to decentralized locomotion control of the stick insectPaolo Arena, Holk Cruse, Luigi Fortuna, Mattia Frasca, Luca Patané. 165-168 [doi]
- A novel and efficient timing-driven global router for standard cell layout design based on critical network conceptTong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu. 165-168 [doi]
- Testability of path history memories with register-exchange architecture used in Viterbi-decodersS. R. Meier, Mario Steinert, S. Buch. 165-168 [doi]
- A 57-dB image band rejection CMOS G/sub m/-C polyphase filter with automatic frequency tuning for BluetoothBo Shi, Weiyun Shan, Pietro Andreani. 169-172 [doi]
- On segmented channel routabilityWilliam N. N. Hung, Xiaoyu Song, Alan J. Coppola, Andrew A. Kennings. 169-172 [doi]
- Towards fast solid state DNA sequencingS. Purushothaman, Christofer Toumazou, Julius Georgiou. 169-172 [doi]
- Advanced neural implants using thin-film polymersD. R. Kipke, D. S. Pellinen, R. J. Vetter. 173-176 [doi]
- A 1.8V CMOS, 80-200MHz continuous-time 4th order 0.05/spl deg/ equiripple linear phase filter with automatic tuning systemMingdeng Chen, J. Silva-Martinez, S. Rokhsaz, M. Robinson. 173-176 [doi]
- Modeling a resonant LC tank circuit embedded in a VCOYe-Ming Li, J. Alvin Connelly. 173-176 [doi]
- Gated direct sequence spread spectrum clocking scheme for multimedia systemsT. T. Tran, R. Liu. 173-176 [doi]
- A CMOS phase-locked loop with an auto-calibrated VCOY. Fouzar, Yvon Savaria, Mohamad Sawan. 177-180 [doi]
- Wavelet method for high-speed clock tree simulationXin Li, Xuan Zeng, Dian Zhou, Xieting Ling. 177-180 [doi]
- Automatic tuning of linearly tunable high-Q filtersAydin I. Karsilayan, Sung-Ling Huang, Jader A. De Lima. 177-180 [doi]
- Design flow of robust routed power distribution for low power ASICDae Woon Kang, Yong-Bin Kim. 181-184 [doi]
- Analysis of VCO jitter in chip-package co-designH. Parthasarathy, Ghanshyam Nayak, Ponnathpur R. Mukund. 181-184 [doi]
- A low-voltage low-noise digital buffer systemRadu M. Secareanu, Bill Peterson, D. Hartman. 181-184 [doi]
- Space-time blind adaptive multiuser detection in antenna array CDMA systemsYuPing Yan, Zemin Liu. 185-188 [doi]
- A new technique for noise-tolerant pipelined dynamic digital circuitsFernando Mendoza-Hernandez, M. Linares, Víctor H. Champac, A. Diaz-Sanchez. 185-188 [doi]
- A 0.9-V 0.2-/spl mu/W CMOS single-opamp-based switched-opamp /spl Sigma//spl Delta/ modulator for pacemaker applicationsV. S. L. Cheung, H. Luong, Mansun Chan. 185-188 [doi]
- Suppression of bit-pulsed jammer signals in DS-CDMA array system using independent component analysisK. Raju, Tapani Ristaniemi, Juha Karhunen, A. Oja. 189-192 [doi]
- Novel macromodeling for on-chip RC/RLC interconnectsQinwei Xu, Pinaki Mazumder, Li Ding 0002. 189-192 [doi]
- A micropower band-pass filter for use in bionic earsChristopher D. Salthouse, Rahul Sarpeshkar. 189-192 [doi]
- A resistorless low current reference circuit for implantable devicesJulius Georgiou, Christofer Toumazou. 193-196 [doi]
- Low noise preamplifier design for nerve cuff electrode recording systemsRobert Rieger, John Taylor, Nick Donaldson. 193-196 [doi]
- Optimising bandwidth over deep sub-micron interconnectDinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen. 193-196 [doi]
- Multiuser wavelet based MC-CDMA receiver with linearly constrained constant modulus IQRD-RLS algorithmShiunn-Jang Chern, Chung-Yao Chang, Hsiao-Chen Liu. 193-196 [doi]
- 1.5V CMOS current reference with extended temperature operating rangeDean A. Badillo. 197-200 [doi]
- State space blind source recovery for mixtures of multiple source distributionsKhurram Waheed, Fathi M. Salam. 197-200 [doi]
- Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductanceMasud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter. 197-200 [doi]
- A low-power, low-noise CMOS amplifier for neural recording applicationsReid R. Harrison. 197-200 [doi]
- An efficient modified Phong shading algorithm & its low-complexity realizationMing-Hsiu Lai, Ming-Feng Yu, Sau-Gee Chen. 201-204 [doi]
- Low-power circuit advantages of the scaled accumulation FETR. Murali, Lihui Wang, Blanca Austin, James D. Meindl. 201-204 [doi]
- Wavelet denoising for highly noisy source separationAnisoara Paraschiv-Ionescu, Christian Jutten, Kamiar Aminian, Bijan Najafi, Philippe Robert. 201-204 [doi]
- Low-voltage bandgap reference with temperature compensation based on a threshold voltage techniqueA. Bendali, Yvon Savaria. 201-204 [doi]
- Circuits and devices with integrated VFETs and RTDsL.-E. Wernersson, E. Lind, P. Lindstrom, Pietro Andreani. 205-208 [doi]
- A low-noise bandgap reference voltage source with curvature correctionA. Azarkan, Arie van Staveren, F. Fruett. 205-208 [doi]
- Adaptive antenna systems for mobile ad-hoc networksSalvatore Bellofiore, Jeffrey A. Foutz, R. Govindarajula, Israfil Bahceci, Constantine A. Balanis, Andreas S. Spanias, Jeffrey M. Capone, Tolga M. Duman. 205-208 [doi]
- A ring-processor based blind beamformer design for use in wireless sensor networksFan Xu, Guichang Zhong, D. D. Richard III, Alan N. Willson Jr.. 205-208 [doi]
- Channel identification scheme for modified MC-CDMA systems with the mixing model of replicating and serial-to-parallel convertingXiaojun Wu, Qinye Yin, Ke Deng. 209-212 [doi]
- Image-adaptive watermarking based on warped discrete cosine transformHan-Seung Jung, Nam Ik Cho, Sang Uk Lee. 209-212 [doi]
- An 8-qubit quantum-circuit processorShin-ichi O uchi, Minoru Fujishima, Koichiro Hoh. 209-212 [doi]
- A scalable sorting architecture based on maskable WTA/MAX circuitShin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu. 209-212 [doi]
- Self-organising behavior of arrays of nonidentical Josephson junctionsLuigi Fortuna, Mattia Frasca, Alessandro Rizzo. 213-216 [doi]
- Subspace-based estimation method of uplink FIR channel in MC-CDMA system without cyclic prefix over frequency-selective fading channelXiaojun Wu, Qinye Yin, Jianguo Zhang. 213-216 [doi]
- Analysis and improvement of correlation-based watermarking methods for digital imagesAkio Miyazaki, Akihiro Okamoto. 213-216 [doi]
- A new pipelined adaptive DFE architecture with improved convergence rateMeng-Da Yang, An-Yeu Wu. 213-216 [doi]
- Design of a pipelined and expandable sorting architecture with simple control schemeChi-Sheng Lin, Bin-Da Liu. 217-220 [doi]
- Independent component analysis of digital image watermarkingShiwei Zhang, P. K. Rajan. 217-220 [doi]
- Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomialYuanbin Guo, Joseph R. Cavallaro. 217-220 [doi]
- Accurate CMOS implementation of PWL CNN neuron activationsMauro Forti, Luca Pancioni, Santina Rocchi, Valerio Vignoli. 221-224 [doi]
- A scalable BSIM3v3 RF model for multi-finger NMOSFETs with ring substrate contactM. Lee, R. B. Anna, Jui-Chu Lee, Scott M. Parker, Kim M. Newton. 221-224 [doi]
- FRM based FIR filter design - the WLS approachYa Jun Yu, Yong Ching Lim. 221-224 [doi]
- Optimization of frequency-response-masking based FIR filters with reduced complexityTapio Saramäki, Juha Yli-Kaakinen. 225-228 [doi]
- Initiation and tracking of dim target via fusion of feature probabilities with CNN-UMHyongsuk Kim, Tamás Roska, Leon O. Chua, Frank S. Werblin. 225-228 [doi]
- Theory and algorithms for RF sensitivity computationJaijeet S. Roychowdhury. 225-228 [doi]
- Multirate cascaded continuous time Sigma-Delta modulatorsMaurits Ortmanns, Lourans Samid, Yiannos Manoli, Friedel Gerfers. 225-228 [doi]
- Efficient implementation for cosine-modulated filter banks using the frequency response masking approachSergio L. Netto, Paulo S. R. Diniz, Luiz C. R. de Barcellos. 229-232 [doi]
- Systematic approach for discrete-time to continuous-time transformation of Sigma-Delta modulatorsHassan Aboushady, Marie-Minerve Louërat. 229-232 [doi]
- On the existence of stable equilibrium points in cellular neural networksMarco Gilli, Mario Biey, Pier Paolo Civalleri. 229-232 [doi]
- Robust design with virtual tests of mixed-signal circuits in VHDL-AMSJian-Yi Wu, Steven B. Bibyk. 229-232 [doi]
- Frequency response masking FIR filters with short delayL. Svensson, H. Johansson. 233-236 [doi]
- Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulatorsFriedel Gerfers, Kian Min Soh, Maurits Ortmanns, Yiannos Manoli. 233-236 [doi]
- Progressive image reconstruction via cellular neural networksS. Itakura, Y. Tanji, Tsuyoshi Otake, Mamoru Tanaka. 233-236 [doi]
- An efficient modeling approach for substrate noise coupling analysisD. Ozis, Kartikeya Mayaram, Terri S. Fiez. 237-240 [doi]
- A modified structure for the design of sharp FIR filters using frequency response masking techniqueChun Zhu Yang, Yong Lian. 237-240 [doi]
- The template optimization of discrete time CNN for image compression and reconstructionNobuaki Takahashi, Tsuyoshi Otake, Mamoru Tanaka. 237-240 [doi]
- Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integrationMartin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen. 237-240 [doi]
- Removing of blocking artefacts using error-compensation interpolation and fast adaptive spatial-varying filteringA. C.-W. Yu, Oscar C. Au, Bing Zeng. 241-244 [doi]
- Transcription of polyphonic signals using fast filter bankSay Wei Foo, Edwin Wei Thai Lee. 241-244 [doi]
- Analysis of time-controlled switched systems using stability preserving mappingsGuisheng Zhai, Bo Hu, Ye Sun, Anthony N. Michel. 241-244 [doi]
- Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic familyG. R. Chaji, Seid Mehdi Fakhraie, K. C. Smith. 245-248 [doi]
- CMOS R-MOSFET-C fourth-order Bessel filter with accurate group delayYigang He, Jinguang Jiang, Yichuang Sun. 245-248 [doi]
- Block loss recovery in DCT image encoding using POCSJiho Park, Dong-Chul Park, Robert J. Marks II, Mohamed A. El-Sharkawi. 245-248 [doi]
- A new low power transconductor for Gm-C filtersA. Hassan, K. Sharaf, H. El-Ghitani, H. F. Ragaie. 249-252 [doi]
- Stabilizing linear time-invariant systems with finite-state hybrid static output feedbackGuisheng Zhai, Xinkai Chen. 249-252 [doi]
- Image quality optimization using computationally efficient variable QoS multicarrier bit-allocationJohn E. Kleider, Glen P. Abousleman. 249-252 [doi]
- Power-delay trade-offs in SCL gatesMassimo Alioto, Gaetano Palumbo. 249-252 [doi]
- Stability and linearization: discrete-time systemsIrwin W. Sandberg. 253-256 [doi]
- CMOS bulk input techniqueHong-Yi Huang, Jing-Fu Lin. 253-256 [doi]
- Image quality assessment by using neural networksP. Carrai, Ingrid Heynderickx, Paolo Gastaldo, Rodolfo Zunino. 253-256 [doi]
- A high dynamic range CMOS variable gain filter for ADSLSaeid Mehrmanesh, Seyed Mojtaba Atarodi. 257-260 [doi]
- Non-causal error diffusion for image halftoningKen-Chung Ho. 257-260 [doi]
- Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D:::3:::L (D:::4:::L) logic stylesR. Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, K. C. Smith. 257-260 [doi]
- The Cauchy-Floquet factorization by successive Riccati transformationsP. van der Kloet, F. L. Neerhoff. 257-260 [doi]
- A critical look at design guidelines for SOI logic gatesRouwaida Kanj, Elyse Rosenbaum. 261-264 [doi]
- A trace-back-free Viterbi decoder using a new survival path management algorithmYingtao Jiang, Yiyan Tang, Yuke Wang, M. N. S. Swamy. 261-264 [doi]
- A 2.8V RWDM BTL Class-D power amplifier using an FGMOS comparatorK. Nandhasri, Jitkasem Ngarmnil, K. Moolpho. 261-264 [doi]
- A silicon model of an adapting motoneuronJ. A. Bragg, Edgar A. Brown, Paul E. Hasler, Stephen P. DeWeerth. 261-264 [doi]
- On-chip current sensing technique for CMOS monolithic switch-mode power convertersCheung Fai Lee, Philip K. T. Mok. 265-268 [doi]
- Power reduction techniques for an OFDM burst synchronization coreLukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner. 265-268 [doi]
- Handset detector architectures for DS-CDMA wireless systemsFrank Livingston, Vikram Chandrasekhar, M. Vaya, Joseph R. Cavallaro. 265-268 [doi]
- Parasitic-aware synthesis of RF CMOS switching power amplifiersKiyong Choi, David J. Allstot, Sayfe Kiaei. 269-272 [doi]
- VLSI architecture of digital matched filter and prime interleaver for W-CDMAYoshihiro Uchida, M. Ise, Takao Onoye, Isao Shirakawa, Itthichai Arungsrisangchai. 269-272 [doi]
- Analog filter adaptation using a dithered linear search algorithmAnthony Chan Carusone, David A. Johns. 269-272 [doi]
- An adaptive analog video line driver with impedance matching based on peak detectionN. Prasad, H. Dinc, Aydin I. Karsilayan. 273-276 [doi]
- Minimum power broadcast trees for wireless networks: optimizing using the viability lemmaRobert J. Marks II, Arindam Kumar Das, Mohamed A. El-Sharkawi, Payman Arabshahi, Andrew Gray. 273-276 [doi]
- Analysis of measurement delay errors in an Ethernet based communication infrastructure for power systemsStephen P. Carullo, Chika O. Nwankpa. 273-276 [doi]
- A VLSI architecture of a K-best lattice decoding algorithm for MIMO channelsKwan-wai Wong, Chi-Ying Tsui, R. S.-K. Cheng, Wai Ho Mow. 273-276 [doi]
- A nonlinear observability formulation for power systems incorporating generator dynamicsChris J. Dafis, Chika O. Nwankpa. 277-280 [doi]
- Low power SOVA architecture using bi-directional schemeMahmoud Elassal, Magdy Bayoumi. 277-280 [doi]
- FPGA-based radix-4 butterflies for HIPERLAN/2A. Perez-Pascual, T. Sansaloni, Javier Valls. 277-280 [doi]
- Tonal behavior analysis of an adaptive second-order sigma-delta modulatorXiaohong Sun, K. R. Laker. 277-280 [doi]
- A high-speed FFT processor for OFDM systemsByung S. Son, Byung G. Jo, Myung Hoon Sunwoo, Yong Serk Kim. 281-284 [doi]
- Interpolation of discrete periodic nonuniform decimation using alias unravelingRobert J. Marks II, S. Narayanan. 281-284 [doi]
- Electro-active polymers as CNN actuators for locomotion controlPaolo Arena, Claudia Bonomo, Luigi Fortuna, Mattia Frasca. 281-284 [doi]
- Lossless/lossy coding gain to evaluate coding performance of the lossless/lossy waveletSomchart Chokchaitam, Masahiro Iwahashi. 281-284 [doi]
- Low coefficient complexity approximations of the one dimensional discrete cosine transformT. W. Fox, L. E. Turner. 285-288 [doi]
- On the theory and design of a class of perfect-reconstruction nonuniform cosine-modulated filter-banksX. M. Xie, S. C. Chan, T. I. Yuk. 285-288 [doi]
- Linearity enhancement of multibit Delta-Sigma modulators using pseudo data-weighted averagingAnas A. Hamoui, K. Martin. 285-288 [doi]
- Development of autonomous, mobile micro-electro-mechanical devicesSalvatore Baglio, Salvatore Castorina, Luigi Fortuna, Nicolò Savalli. 285-288 [doi]
- Error spectrum shaping in closed-loop systems with state-estimate feedback controllerT. Hinamoto, S. Yamamoto. 289-292 [doi]
- Multirate approximately linear-phase IIR filter structures for arbitrary bandwidthsH. Johansson. 289-292 [doi]
- A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulatorLourans Samid, Maurits Ortmanns, Yiannos Manoli, Friedel Gerfers. 293-296 [doi]
- Design of a DSP-based 24 bit digital audio equalizer for automotive applicationsAlberto Bellini, Eraldo Carpanoni, Giacomo Frassi, Monica Tesauri, Emanuele Ugolotti. 293-296 [doi]
- Noise-mediated cooperative behavior in a system of coupled DC SQUIDsJuan A. Acebrón, Adi R. Bulsara, W.-J. Rappel. 293-296 [doi]
- An alternative approach to the design and synthesis of higher-order Bode-type variable-amplitude wave-digital equalizersBehrouz Nowrouzian, Arthur T. G. Fuller, M. N. S. Swamy. 293-296 [doi]
- Power analysis of multiplier blocksSüleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale. 297-300 [doi]
- A cost-effective and high-precision architecture for CORDIC-based adaptive lattice filtersShin ichi Shiraishi, Miki Haseyama, Hideo Kitajima. 297-300 [doi]
- BiCMOS switched buffers resonator for a 320 MHz 2-path sigma-delta modulatorFausto Borghetti, A. Esposito, Umberto Gatti, Piero Malcovati, Franco Maloberti. 297-300 [doi]
- Organic molecules and composites with applications in micro and nanoelectronic systemsLuigi Occhipinti, Luigi Fortuna. 297-300 [doi]
- A high-bandwidth high-swing CMOS power amplifier for portable audio playersP. K. Chan, J. C. Tao. 301-304 [doi]
- Theory and design of a bio-inspired multistable oscillatorRobert J. Butera, N. McSpadden, J. Mason. 301-304 [doi]
- A CMOS coupled nonlinear oscillator arrayJoseph D. Neff, Brian K. Meadows, Edgar A. Brown, Stephen P. DeWeerth, Paul E. Hasler. 301-304 [doi]
- A 2.5-V Sigma-Delta modulator in 0.25-µm CMOS for ADSLRocio del Río, F. Medeiro, José Manuel de la Rosa, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez. 301-304 [doi]
- Analysis of Hopf bifurcation in parallel-connected boost converters via averaged modelsHerbert H. C. Iu, C. K. Tse, V. Pjevalica, Y. M. Lai. 305-308 [doi]
- Design considerations and experimental evaluation of a syllabic companding audio frequency filterG. Palaskas, Yannis P. Tsividis. 305-308 [doi]
- Comparison of two schemes for continuous-time sub-volt op-amp operationJaime Ramírez-Angulo, Antonio B. Torralba, Ramón González Carvajal. 305-308 [doi]
- Design rewiring for power minimization [logic design]Mandana Amiri, Andreas G. Veneris, Ivor Ting. 305-308 [doi]
- Energy dissipation modeling of lossy transmission lines driven by CMOS invertersPayam Heydari. 309-312 [doi]
- Bifurcation of modes in three-coupled oscillators with the increase of nonlinearityY. Aruga, T. Endo, A. Hasegawa. 309-312 [doi]
- An 1 V rail-rail low-power CMOS op-ampDingtzay Chen, Hongchin Lin. 309-312 [doi]
- Direct noise analysis of log-domain filtersA. E. J. Ng, John I. Sewell. 309-312 [doi]
- Confronting violations of the TSCG(T) in low-power designAthanasios Kakarountas, K. Papadomanolakis, Spiridon Nikolaidis, Dimitrios Soudris, Constantinos E. Goutis. 313-316 [doi]
- Inverting the bipolar differential pair for low-voltage applicationsBradley A. Minch. 313-316 [doi]
- Phase pattern switching in star-coupled Wien-bridge oscillators driven by pulse trainS. Moro, T. Matsumoto. 313-316 [doi]
- Analysis of phase-waves in coupled oscillators as a ladderMasayuki Yamauchi, Yoshifumi Nishio, Akio Ushida. 317-320 [doi]
- Iterative solution of ODE-PDE-AE systems for RF circuit simulationO. Wing, Tan Jun, Jin-mei Lai, Junyan Ren, Qianling Zhang. 317-320 [doi]
- A micropower log domain FGMOS filterEsther Rodríguez-Villegas, Adoración Rueda, Alberto Yufera. 317-320 [doi]
- Synthesis of a translinear analog adaptive filterE. J. McDonald, Bradley A. Minch. 321-324 [doi]
- Boolean verification with fastest LIA transformsBogdan J. Falkowski, Susanto Rahardja. 321-324 [doi]
- An efficient low-power binding algorithm in high-level synthesisYoonseo Choi, Taewhan Kim. 321-324 [doi]
- Analysis and optimization of gain-boosted telescopic amplifiersWalter Aloisi, Gianluca Giustolisi, Gaetano Palumbo. 321-324 [doi]
- A novel integration of on-sensor wavelet compression for a CMOS imagerQiang Luo, John G. Harris. 325-328 [doi]
- A don t-care based image circuit for function verificationJiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang. 325-328 [doi]
- Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000Hong-Hui Chen, Chung-Jr Lian, Te-Hao Chang, Liang-Gee Chen. 329-332 [doi]
- An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]Yutao Hu, Kartikeya Mayaram. 329-332 [doi]
- A CMOS imager with real-time frame differencing and centroid computationRichard A. Blum, Charles S. Wilson, Paul E. Hasler, Stephen P. DeWeerth. 329-332 [doi]
- Rail-to-rail OTA using a pair of single channel type MOSFETsTakahide Sato, Shigetaka Takagi, Nobuo Fujii. 329-332 [doi]
- Semi-formal verification of VHDL-AMS descriptionsA. Salem. 333-336 [doi]
- A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithmH. Kimura, T. Shibata. 333-336 [doi]
- JPEG2000 adaptive rate control for embedded systemsTakahiko Masuzaki, Hiroshi Tsutsui, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura. 333-336 [doi]
- Variable ordering on multiway decision graphsYi Feng, Eduard Cerny. 337-340 [doi]
- A matrix transform imager allowing high-fill factorPaul E. Hasler, Abhishek Bandyopadhyay, Paul D. Smith. 337-340 [doi]
- A vector based fast block motion estimation algorithm for implementation on SIMD architecturesC. J. Duanmu, M. Omair Ahmad, M. N. S. Swamy, Ali Shatnawi. 337-340 [doi]
- A 1.2 V rail-to-rail differential mode input linear CMOS transconductorAimin Xu, M. F. Li. 337-340 [doi]
- A hardware accelerator for video segmentation using programmable morphology PE arrayShao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen. 341-344 [doi]
- Adaptive optimization of notch bandwidth of an IIR filter used to suppress narrow-band interferenceAloys Mvuma, Shotaro Nishimura, Takao Hinamoto. 341-344 [doi]
- A processing element architecture for high-density focal plane analog programmable array processorsGustavo Liñan Cembrano, Servando Espejo-Meana, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez. 341-344 [doi]
- Sequence-pair based placement with boundary constraintsChih-Hung Lee, Yi-Lin Hsieh, Hui-Chun Lee, Tsai-Ming Hsieh. 341-344 [doi]
- Simplified input current waveshaping technique by using inductor voltage sensing for power factor correction isolated Sepic rectifierTanes Tanitteerapan, S. Mori. 345-348 [doi]
- Steady-state analysis of a subband adaptive algorithm with critical samplingMariane R. Petraglia, R. T. B. Vasconcellos. 345-348 [doi]
- A genetic approach to analog module placement with simulated annealingLihong Zhang, Ulrich Kleine. 345-348 [doi]
- A property of Jacobian matrices and some of its consequencesAlfred Fettweis, Nirmal K. Bose. 345-348 [doi]
- Module placement with pre-placed modules using the corner block list representationS. Dhamdhere, Ningyu Zhou, Ting-Chi Wang. 349-352 [doi]
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- A single-phase three-level boost type rectifierBor-Ren Lin, Tsung-Liang Hung. 353-356 [doi]
- Minimax design of 2-D IIR digital filters using sequential semidefinite programmingWu-Sheng Lu, Andreas Antoniou. 353-356 [doi]
- Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuitsRoy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev. 357-360 [doi]
- Performance analysis of nonlinear RLS in mixture noiseShu Hung Leung, Y. Xiong, J. F. Weng, C. F. So, W. H. Lau. 357-360 [doi]
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- Improved wave-digital approach to numerically integrating the PDES of fluid dynamicsAlfred Fettweis. 361-364 [doi]
- Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purityJ. M. Pierre Langlois, Dhamin Al-Khalili. 361-364 [doi]
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- Voltage-clamped class E amplifier with a Zener diode across the switchTadashi Suetsugu, Marian K. Kazimierczuk. 361-364 [doi]
- Physical synthesis for ASIC datapath circuitsTerry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli. 365-368 [doi]
- An efficient design for FIR filters with variable precisionXiaojuan Hu, Linda DeBrunner, Victor E. DeBrunner. 365-368 [doi]
- Joint source-channel content-based multistream video coding schemeJie Chen, K. J. Ray Liu. 365-368 [doi]
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- TDMA-based communication scheduling in system-on-chip video encoderTero Kangas, Kimmo Kuusilinna, Timo Hämäläinen. 369-372 [doi]
- Asynchronous circuit synthesis via direct translationDelong Shang, Fei Xia, Alexandre Yakovlev. 369-372 [doi]
- Efficient digit-serial FIR filters with skew-tolerant dominoSungwook Kim, Gerald E. Sobelman. 369-372 [doi]
- Low power implementation of high throughput FIR filtersTughrul Arslan, Ahmet T. Erdogan. 373-376 [doi]
- A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulatorByung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu. 373-376 [doi]
- Logic synthesis for PLA with 2-input logic elementsHiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada. 373-376 [doi]
- Recursive patching for video-on-demand (VOD) systems with limited client buffer constraintZhi Shi, C. C. Jay Kuo. 373-376 [doi]
- A 1-V, self adjusting, 5-MHz CMOS RC-oscillatorK. Lasanen, Elvi Räisänen-Ruotsalainen, Juha Kostamovaara. 377-380 [doi]
- Dynamic throughput estimation for wireless multimedia transmissionWuttipong Kumwilaisak, C. C. Jay Kuo. 377-380 [doi]
- Polynomial expansions over GF(2) based on fastest transformationSusanto Rahardja, Bogdan J. Falkowski. 377-380 [doi]
- A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applicationsM. A. R. Eltokhy, Boon-Keat Tan, T. Matsuoka, K. Taniguchi. 377-380 [doi]
- K-band phase locked hair-pin oscillatorY. Cheng, Krzysztof Czuba, G. Kompa. 381-384 [doi]
- A reconfigurable logic circuit based on threshold elements with a controlled floating gateK. Aoyama. 381-384 [doi]
- Circuit design from minimized Haar wavelet seriesBogdan J. Falkowski, Radomir S. Stankovic, Dragan Jankovic. 381-384 [doi]
- Analysis of the oscillation problem in tri-flopsOleh V. Maevsky, D. J. Kinniment, Alexandre Yakovlev, Alexandre V. Bystrov. 381-384 [doi]
- Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic385-388 [doi]
- Seamless switching of scalable video bitstreams for efficient streamingXiaoyan Sun, Feng Wu, Shipeng Li, Wen Gao, Ya-Qin Zhang. 385-388 [doi]
- A structurally stable realization for Jacobi elliptic functionsHonghao Ji, R. W. Newcomb. 385-388 [doi]
- Experimental detection of bifurcations and sliding in DC-DC power convertersMario di Bernardo, Francesco Vasca, Luigi Iannelli. 385-388 [doi]
- A non-feedback multiphase clock generatorLixin Yang, Yijun Zhou, Jiren Yuan. 389-392 [doi]
- A dynamic frame-skipping video combiner for multipoint video conferencingKai-Tat Fung, Wan-Chi Siu, Yui-Lam Chan. 389-392 [doi]
- High-speed low-power logic gates using floating gatesEsther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda. 389-392 [doi]
- An advanced design method of bursting in Fitzhugh-Nagumo modelShigeki Tsuji, Tetsushi Ueta, Hiroshi Kawakami, Kazuyuki Aihara. 389-392 [doi]
- Analysis of jitter in ring oscillators due to deterministic noiseN. Barton, D. Ozis, Terri S. Fiez, Kartikeya Mayaram. 393-396 [doi]
- Efficient error recovery techniques in a novel multimedia streaming framework with peer-paired collaborationHao Wang, Guobin Shen, Shipeng Li, Yuzhuo Zhong. 393-396 [doi]
- Performance analysis in chaotic-iteration-based ADCsXiuming Shan, Yulong Liu, Hao Lin, Yong Ren. 393-396 [doi]
- Compact low-voltage self-calibrating digital floating-gate CMOS logic circuitsTrond Ytterdal, Snorre Aunet. 393-396 [doi]
- A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistorsMats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande. 397-400 [doi]
- Design trade-offs of a symmetric linearized CMOS LC VCOF. Dulger, E. Sanchez-Sinencio. 397-400 [doi]
- MPEG-4 video error detection by using data hiding techniquesZhi-Wei Gao, Wen-Nung Lie. 397-400 [doi]
- A high-performance CMOS multiphase voltage-controlled oscillator for communication systemsR. R.-B. Sheen, Oscal T.-C. Chen, Zheng-Dao Lee. 401-404 [doi]
- Optimal design and parallel implementation of FIR filters with variable magnitude and fractional-delay responsesTian-Bo Deng. 401-404 [doi]
- A robust fine granularity scalability using trellis based predictive leakHsiang-Chun Huang, Chung-Neng Wang, Tihao Chiang. 401-404 [doi]
- CMOS phase-shift VCO for short-range wireless communicationM. Nakamura, T. Matsuoka, K. Taniguchi. 405-408 [doi]
- Analysis of interleaved converters with WTA-based switchingToshimichi Saito, M. Yoshizawa, Hiroyuki Torikai, S. Tazaki. 405-408 [doi]
- A design method of low delay lowpass FIR filters with maximally flat characteristics in the passband and the transmission zeros in the stopbandN. Aikawa, M. Sato. 405-408 [doi]
- Class AB-D-G line driver for central office asymmetric digital subscriber line systemsJ. Shorb, David J. Allstot, R. Roze. 405-408 [doi]
- A low-power subscriber line interface circuit in a high-voltage CMOS technologyMohammad B. Vahidfar, Armin Tajalli, Seyed Mojtaba Atarodi. 409-412 [doi]
- Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning rangeN. Seshan, J. Rajagopalan, Kartikeya Mayaram. 409-412 [doi]
- Analysis and design of PWM regulators for large-signal stabilityYefim Berkovich, Adrian Ioinovici. 409-412 [doi]
- 38 GHz low-power static frequency divider in SiGe bipolar technologyG. Ritzberger, J. Bock, H. Knapp, L. Treitinger, Arpad L. Scholtz. 413-416 [doi]
- On designing FIR filters using windows based on Gegenbauer polynomialsAgnieszka Rowinska-Schwarzweller, Markus Wintermantel. 413-416 [doi]
- A method for predicting the ZVS condition for the class E amplifierTadashi Suetsugu, Marian K. Kazimierczuk. 413-416 [doi]
- A low-cost point-to-multi-point access system based on OFDM transmissionM. Schobinger, S. R. Meier. 417-420 [doi]
- Intelligent multipoint Arnoldi (IMA) approximations of FIR filters by low-order linear-phase IIR filtersHerng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng. 417-420 [doi]
- Magnetizing inrush current of a transformer and a new technique of its computationM. Ogawa. 417-420 [doi]
- Design of variable Laguerre filtersDavid B. H. Tay, Saman S. Abeysekera. 417-420 [doi]
- Lossless/lossy image compression based on non-separable two-dimensional L-SSKFSomchart Chokchaitam, Masahiro Iwahashi. 421-424 [doi]
- A new group distributed arithmetic design for the one dimensional discrete Fourier transformHun-Chen Chen, Jiun-In Guo, Chein-Wei Jen. 421-424 [doi]
- Design of variable fractional delay FIR filter using differentiator bankChien-Cheng Tseng. 421-424 [doi]
- Dynamics of high-frequency CMOS dividersU. Singh, M. Green. 421-424 [doi]
- Power line communication front-ends based on ADSL technologyJ. Van den Keybus, B. Bolsens, Johan Driesen, Ronnie Belmans. 425-428 [doi]
- A retargetable tool-suite for the design of application specific instruction set processors using a machine description languageA. Abbas, A. Ahmed, Waheed Uz Zaman Bajwa, A. Anwar, S. Abbasi. 425-428 [doi]
- Integer- and rational-coefficient M-band waveletWei Dai, Trac D. Tran, Soontorn Oraintara, Truong Q. Nguyen. 425-428 [doi]
- Design and implementation of a novel algorithm for general purpose median filtering on FPGAsKhaled Benkrid, Danny Crookes, Abdsamad Benkrid. 425-428 [doi]
- A quadrature-modulator for 0.6-2.6 GHz with frequency doublerEsa Tiiliharju, Kari Halonen. 429-432 [doi]
- Min-max interpolators and Lagrange interpolation formulaJean-Jacques Fuchs, Bernard Delyon. 429-432 [doi]
- Comparison of digital linearization methods for embedded sensor interfacesO. Betat, Luigi Carro. 429-432 [doi]
- A multistage filterbank-based channelizer and its multiplier-less realizationCheong Yiu Fung, S. C. Chan. 429-432 [doi]
- Dynamic range of allpass filter structuresRichard C. S. Morling, Izzet Kale. 433-436 [doi]
- A 6 channel array of 5 milliwatt, 500 MHz optical receivers in .5 /spl mu/m SOS CMOSAlyssa B. Apsel, Andreas G. Andreou, J. Liu. 433-436 [doi]
- Linear phase IIR filter bank design by LMI based H::infinity:: optimizationMin Li, Chi-Wah Kok. 437-440 [doi]
- Real-time streaming for the animation of talking faces in multiuser environmentsJörn Ostermann, Jürgen Rurainsky, M. Reha Civanlar. 437-440 [doi]
- Body effect compensated switch for low voltage switched-capacitor circuitsSangwook Kim, E. Greeneich. 437-440 [doi]
- A 2.5 Gbit/s CMOS optical receiver frontendPatrick Mitran, Felix Beaudoin, Mourad N. El-Gamal. 441-444 [doi]
- Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems441-444 [doi]
- A monolithic CMOS VCO for wireless LAN applicationsJ. Bhattacharjee, D. Mukherjee, J. Laskar. 441-444 [doi]
- Layered video over IP networks by using selective drop routersHsu-Feng Hsiao, Qiang Liu, Jenq-Neng Hwang. 441-444 [doi]
- Low complexity OFDM receiver using Log-FFT for coded OFDM systemYan Wang, Hing Mo Lam, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow. 445-448 [doi]
- MMSE matching for low noise amplifierJongrit Lerdworatawee, Won Namgoong. 445-448 [doi]
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- Video coding with virtual set partitioning in hierarchical treeEkram Khan, M. Ghanbari. 449-452 [doi]
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- A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo cancellerCheng-Shing Wu, An-Yeu Wu. 453-456 [doi]
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- An overview of design techniques for CMOS phase detectorsS. Soliman, F. Yuan, Kaamran Raahemifar. 457-460 [doi]
- A mixed-mode IF GFSK demodulator for BluetoothChunyu Xin, Bo Xia, Wenjun Sheng, Ari Y. Valero-López, Edgar Sánchez-Sinencio. 457-460 [doi]
- Response of coupled chaotic circuits to sinusoidal input signalT. Hayashi, Yoshifumi Nishio, M. Hasler, Akio Ushida. 461-464 [doi]
- A crystal oscillator with automatic amplitude control and digitally controlled pulling range of +-100 ppmV. Balan, T. Pan. 461-464 [doi]
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- 3D scheduling based on code space exploration for dynamically reconfigurable systemsM. Kaneko, J. Yokoyama, S. Tayu. 465-468 [doi]
- On start point selection for the time-optimal system design algorithmAlexander Zemliak. 465-468 [doi]
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- Chaotic optimization for quadratic assignment problemsTohru Ikeguchi, K. Sato, Mikio Hasegawa, Kazuyuki Aihara. 469-472 [doi]
- Synchronization of distributed simulations-a Kalman filter approachArasch Honarbacht, Fritz Boschen, Anton Kummert, N. Harle. 469-472 [doi]
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- Low depth carry lookahead addition using charge recycling threshold logicPeter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López. 469-472 [doi]
- An application level synthesis methodology for embedded systemsCesare Alippi, Andrea Galbusera, Marco Stellini. 473-476 [doi]
- A robust self-resetting CMOS 32-bit parallel adderGunok Jung, V. A. Sundarajan, Gerald E. Sobelman. 473-476 [doi]
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- Analysis of a type of digital chaotic cryptosystemGuoJie Hu, ZhengJin Feng, Lin Wang. 473-475 [doi]
- A discrete algorithm for the regularization of hierarchical VHDL-AMS modelsJochen Mades, D. E. Schwarz, Manfred Glesner. 477-480 [doi]
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- A prefiltering approach to frequency offset estimation in AWGNM. Rezki, L. Sabel, Izzet Kale. 480-483 [doi]
- Address code optimization using code scheduling for digital signal processorsYoonseo Choi, Taewhan Kim. 481-484 [doi]
- Cell library for automatic synthesis of analog error control decodersJie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel. 481-484 [doi]
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- Interconnect peak current reduction for wavelet array processor using self-timed signalingPasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen. 485-488 [doi]
- A new noise reduction method using linear prediction error filter and adaptive digital filterA. Kawamura, K. Fujii, Y. Itoh, Y. Fukui. 488-491 [doi]
- Accurate programming of analog floating-gate arraysPaul D. Smith, Matt Kucic, Paul E. Hasler. 489-492 [doi]
- Two-dimensional signal gating for low-power array multiplier designZhijun Huang, Milos D. Ercegovac. 489-492 [doi]
- Measurement time requirement for generalized cross-correlation based time-delay estimationQiyue Zou, Zhiping Lin. 492-495 [doi]
- Practical issues using e-pot circuitsC. Duffy, Ethan Farquhar, Paul E. Hasler. 493-496 [doi]
- A modified identification algorithm for linear systems with noisy input-output dataWei Xing Zheng. 496-499 [doi]
- Estimation of fast fading channel in impulse noise environmentCheong Yiu Fung, S. C. Chan. 497-500 [doi]
- A V/sub t/-zero equivalent MOSFET and its applicationsHiroki Sato, Akira Hyogo, Keitaro Sekine. 497-500 [doi]
- Application of the SD to LCTI systems 1Khier Benmahammed, Abdelaziz Hamzaoui. 500-502 [doi]
- A 10-bit 1 MS/s 3-step ADC with bitstream-based sub-DAC and sub-ADC calibrationBardia Pishdad, Gordon W. Roberts. 501-504 [doi]
- The norm constraint IQML beamforming algorithm for wideband and coherent jammers suppressionChung-Yao Chang, Shiunn-Jang Chern. 501-504 [doi]
- A low-voltage floating-gate CMOS transconductance amplifier, and a spin-off quasi frequency triplerJohannes Goplen Lomsdalen, Yngvar Berg, Renè Jensen. 501-504 [doi]
- Application of the SD to LCTI systems 2Khier Benmahammed, Abdelaziz Hamzaoui. 503-506 [doi]
- Intermodulation distortion measures in a stochastic resonatorF. R. Palomo, J. M. Quero, Leopoldo García Franquelo. 505-508 [doi]
- Voltage-clamped class E amplifier with a Zener diode across the choke coilTadashi Suetsugu, Marian K. Kazimierczuk. 505-508 [doi]
- An analog-to-digital converter with time-variant windowH. Imamura, Toshimichi Saito, Hiroyuki Torikai. 505-508 [doi]
- On inconsistent initial conditions for linear time-invariant differential-algebraic equationsGunther Reißig, Holger Boche, Paul I. Barton. 507-510 [doi]
- Class-E MOSFET low-voltage power oscillatorD. V. Chernov, Marian K. Kazimierczuk, V. G. Krizhanovski. 509-512 [doi]
- A CMOS companding-based third order Chebyshev filterLige Wang, M. N. El-Gamal. 509-512 [doi]
- Derivation algorithm of transfer functions of 2-D continuous-discrete systemsYang Xiao. 511-514 [doi]
- A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precisionAntti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara. 513-516 [doi]
- Fractional-N frequency synthesizer for wireless communicationsA. E. Hussein, Mohamed I. Elmasry. 513-516 [doi]
- Impact of boost converter parameters on open-loop dynamic performance for DCMAlberto Reatti, L. Pellegrini, Marian K. Kazimierczuk. 513-516 [doi]
- Cut-off frequencies in wide-band systemsSidnei Noceti Filho, Rui Seara. 515-518 [doi]
- Single-amplifier integrator-based low power CMOS filter for video frequency applicationsC. Hill, Yichuang Sun, Hsiao Wei Su. 517-520 [doi]
- Class-N high-frequency power amplifierA. N. Rudiakova, Marian K. Kazimierczuk, J. V. Rassokhin, V. G. Krizhanovski. 517-520 [doi]
- Frequency division using an injection-locked relaxation oscillatorChris van den Bos, Chris J. M. Verhoeven. 517-520 [doi]
- Stochastic resonance of a threshold detector: image visualization and explanationRobert J. Marks II, B. Thompson, Mohamed A. El-Sharkawi, Warren L. J. Fox, Robert T. Miyamoto. 521-523 [doi]
- Generalized state-plane analysis of soft-switching DC-DC convertersA. Alsharqawi, Issa Batarseh. 521-524 [doi]
- New circuits for realization of the 1st and 2nd order all-pass LC filters with a better technological feasibilityK. Hajek, Z. Sedlacek, B. Sviezeny. 523-526 [doi]
- An embedded DSP core for wireless communicationShyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao. 524-527 [doi]
- Complex low-pass filtersPeter Kiss, Vladimir I. Prodanov, Jack P. F. Glas. 525-528 [doi]
- Asymmetry half bridge soft-switching PFC converter with direct energy transferK. Rustom, Wenkai Wu, Weihong Qiu, Issa Batarseh. 525-528 [doi]
- Immitance data modelling via linear interpolation techniquesB. Siddik Yarman, Ahmet Aksen, Ali Kilinc. 527-530 [doi]
- Using a spectral technique, genetic algorithms and decision diagrams for finding unconditional table testsKaren O. Egiazarian, Radomir S. Stankovic, Jaakko Astola, Heikki Huttunen. 528-531 [doi]
- On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS processMing-Dou Ker, Kuo-Chun Hsu. 529-532 [doi]
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- ESD protection circuits with novel MOS-bounded diode structuresMing-Dou Ker, Che-Hao Chuang. 533-536 [doi]
- WCDMA channel selection filter with high IIP2Jarkko Jussila, Kari Halonen. 533-536 [doi]
- Minor and major subspace computation of large matricesM. A. Hasan, A. A. Hasan. 536-539 [doi]
- A limitation on active filter dynamic rangeJ. Harrison, Neil Weste. 537-540 [doi]
- Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuitsJeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang. 537-540 [doi]
- A robust method for equalizer design based on the impulse response symmetryM. Vucic, H. Babic. 539-542 [doi]
- Rate-distortion optimization of macroblock-based progressive fine granularity scalable video codecXiaodong Fan, Guobin Shen, Shipeng Li, T. D. Tran, Ya-Qin Zhang. 540-543 [doi]
- Modified long channel model for analytical study of DSM circuitsLi Ding 0002, Pinaki Mazumder. 541-544 [doi]
- Analysis and optimization of CMOS LNA noise performance with channel resistanceJiwei Chen, Bingxue Shi. 543-546 [doi]
- Constant quality rate control for streaming MPEG-4 FGS videoLifeng Zhao, JongWon Kim, C. C. Jay Kuo. 544-547 [doi]
- Continuous-time linear systems: folklore and factIrwin W. Sandberg. 545-548 [doi]
- CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuitsKyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai. 545-548 [doi]
- Revisiting the sifting integral: an interesting special caseAziz S. Inan, Peter M. Osterberg. 547-550 [doi]
- H.26L-based fine granularity scalable video codingYuwen He, Feng Wu, Shipeng Li, Yuzhuo Zhong, Shiqiang Yang. 548-551 [doi]
- A new hardware efficient design for the one dimensional discrete Fourier transformJiun-In Guo, Chien-Chang Lin. 549-552 [doi]
- An automatic tuning scheme for high frequency bandpass filtersHengsheng Liu, Aydin I. Karsilayan. 551-554 [doi]
- Effect of CNN shape segmentation on MPEG-4 shape bit-rateLauri Koskinen, Ari Paasio, Mika Laiho, Kari Halonen. 552-555 [doi]
- A fully programmable Reed Solomon 8-bit codec based on a re-shaped Berlekamp Massey algorithmE. Marconetti, R. Guenard, D. Savage, P. Crowe, I. Epelde, L. Bradley, Fabrizio Calì. 553-556 [doi]
- New method for tailoring ripple and spectral properties of chaotic DC-DC convertersJ. Weber, O. Woywode, H. Guldner, Alexander L. Baranovski, Wolfgang M. Schwarz. 556-559 [doi]
- Floating-gate EEPROM cell: threshold voltage sensibility to geometryJean Michel Portal, L. Forli, Didier Née. 557-560 [doi]
- Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 µm CMOS technologiesMohammed Sayed, Wael M. Badawy. 559-562 [doi]
- Statistical analysis of power spectra of signals governed by Markov chainsHanoch Lev-Ari, Alex M. Stankovic. 560-563 [doi]
- Analysis of power supply noise attenuation in a PTAT current sourceGianluca Giustolisi, Gaetano Palumbo. 561-564 [doi]
- Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithmJung Hoo Lee, Jae Sung Lee, Myung Hoon Sunwoo, Kyung Ho Kim. 561-564 [doi]
- A radix-2:::n::: vector inner productA. Aggoun, A. Farwan, M. K. Ibrahim. 563-566 [doi]
- Signal coding and compression based on discrete-time chaos: statistical approachesMaciej Ogorzalek. 564-567 [doi]
- Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design methodChao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen. 565-568 [doi]
- Tolerance analysis for electronic circuit design using the method of momentsWei Sun, Richard M. M. Chen, Yao-Lin Jiang. 565-568 [doi]
- Potential of chaos communication over noisy channels - channel coding using chaotic piecewise linear mapsMartin Hasler, Thomas Schimming. 568-571 [doi]
- Very high-speed BJT buffer for track-and-hold amplifiers with enhanced linearityDevrim Yilmaz Aksin, Franco Maloberti. 569-572 [doi]
- A polynomial-based division algorithmRobert Hägglund, Per Löwenborg, Mark Vesterbacka. 571-574 [doi]
- An approach to statistical analysis of coarsely time-Markov systemsRiccardo Rovatti, Gianluca Mazzini, Gianluca Setti. 572-575 [doi]
- A neural network approach to predict the crosstalk in non-uniform multiconductor transmission linesBarbara Cannas, Alessandra Fanni, F. Maradei. 573-576 [doi]
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- Sub-word and reduced-width Booth multipliers for DSP applicationsMeng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou. 575-578 [doi]
- Low power voltage regulator for EPROM applicationsJ. Shor, Y. Sofer, Y. Polansky, E. Maayan. 576-579 [doi]
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- Full current-mode techniques for high-speed CMOS SRAMsS. M. Wang, C. X. Wu. 580-582 [doi]
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- A low distortion MOS sampling circuitSameer R. Sonkusale, Jan Van der Spiegel. 585-588 [doi]
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- Automatic tuning of high frequency, high Q, multiple loop feedback bandpass filtersJ. R. Moritz, Y. Sun. 605-608 [doi]
- Simple parallel weighted order statistic filter implementationsMaria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas. 607-610 [doi]
- Biological learning modeled in an adaptive floating-gate systemChristal Gordon, Paul E. Hasler. 609-612 [doi]
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- A novel double sampled chopper stabilised integrator for switched capacitor Sigma-Delta modulatorsI. J. O Connell, C. Lyden. 619-622 [doi]
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- Low-power CDMA analog matched filters based on floating-gate technologyT. Yamasaki, T. Taguchi, T. Shibata. 625-628 [doi]
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- All digital transistor high gain operational amplifier using positive feedback techniqueM. M. Amourah, Randall L. Geiger. 701-704 [doi]
- Maximally flat allpass fractional Hilbert transformersSoo-Chang Pei, Peng-Hua Wang. 701-704 [doi]
- Delta-sigma modulator topologies with high immunity to pattern noiseG. Fischer, Deokhwan Hyun. 703-706 [doi]
- Heuristic assignment-driven scheduling for data-path synthesisK. Ohashi, M. Kaneko. 703-706 [doi]
- A truncated polynomial interpolation theorem and its application to the WLS design of IIR filtersHiroshi Hasegawa, M. Nakagawa, Isao Yamada, Kohichi Sakaniwa. 705-708 [doi]
- Novel high performance current-feedback op-ampAmr A. Tammam, Khaled Hayatleh, F. J. Lidgey. 705-708 [doi]
- An efficient technique to eliminate quantisation noise folding in double-sampling Sigma-Delta modulatorsPieter Rombouts, Johan Raman, Ludo Weyten. 707-710 [doi]
- Optimal circuit clustering with variable interconnect delayCliff C. N. Sze, Ting-Chi Wang. 707-710 [doi]
- A CMOS current feedback operational amplifier with active current mode compensationKin-Pui Ho, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun. 709-712 [doi]
- A structure of cascading multi-bit modulators without dynamic element matching or digital correctionBingxin Li, Hannu Tenhunen. 711-714 [doi]
- A design methodology for IP integrationPhilippe Coussy, Adel Baganne, Eric Martin. 711-714 [doi]
- A temperature independent trimmable current sourceS. Shah, S. Collins. 713-716 [doi]
- Motion re-estimation for HDTV to SDTV transcodingJun Xin, Ming-Ting Sun, Kang Wook Chun, Byung Sun Choi. 715-718 [doi]
- An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizerR. Batten, Terri S. Fiez. 715-718 [doi]
- Temperature compensated CMOS voltage referenceSebastien Laberge, Gordon W. Roberts. 717-720 [doi]
- Space-time vector delta-sigma modulationD. Scholnik, J. O. Coleman. 719-722 [doi]
- Methods and needs for transcoding MPEG-4 fine granularity scalability videoYongQing Liang, Yap-Peng Tan. 719-722 [doi]
- Determination of voltage source values in modern biasing techniques of analog circuitsE. Yildiz, Arturo Sarmiento-Reyes, Chris J. M. Verhoeven, Arie van Staveren. 721-724 [doi]
- Design of a body-effect reduced-source follower and its application to linearization techniqueKazuyuki Wada, Yoshiaki Tadokoro. 723-726 [doi]
- Reduced spatio-temporal transcoding using an intra refresh techniqueAnthony Vetro, Peng Yin, Bede Liu, Huifang Sun. 723-726 [doi]
- Mobility support for Bluetooth public accessA. Kansal, Uday B. Desai. 725-728 [doi]
- A low-noise nonlinear feedback technique for compensating offset in analog multipliersM. T. Dastjerdi, Rahul Sarpeshkar. 725-728 [doi]
- DCT-based edge detector for snapshot imagesMon Wei Wu, C. J. Kuo. 727-730 [doi]
- A wide-linear-range subthreshold CMOS transconductor employing the back-gate effectReid R. Harrison. 727-730 [doi]
- Area-efficient digital baseband module for Bluetooth wireless communicationsMyoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park. 729-732 [doi]
- An evolvable predictor for lossless image compressionD. Leon, Sina Balkir, Khalid Sayood. 731-734 [doi]
- Design of highly linear tunable CMOS OTASlawomir Koziel, Stanislaw Szczepanski, Rolf Schaumann. 731-734 [doi]
- Modified Gilbert transconductance multiplierJ. Lee, Khaled Hayatleh, F. J. Lidgey. 733-736 [doi]
- Pole-zero tracking frequency compensation for low dropout regulatorKa Chun Kwok, Philip K. T. Mok. 735-738 [doi]
- A highly linear low-voltage MOS transconductorAdrian Leuciuc, Yi Zhang. 735-738 [doi]
- Useful multipliers for low-voltage applicationsBrent Maundy, Peter B. Aronhime. 737-740 [doi]
- A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance valuesT. Oura, T. Yoneyama, S. Tantry, H. Asai. 739-742 [doi]
- Design and implementation of an H::infinity:: controller for a bi-directional DC-DC converterW. E. Bury, J. Dzieza, Dariusz Czarkowski, S. Lewis. 739-742 [doi]
- Modeling a new RTL semantics in C++Shuqing Zhao, Daniel Gajski. 741-744 [doi]
- Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loopA. Rao, W. McIntyre, J. Parry, Un-Ku Moon, Gabor C. Temes. 743-746 [doi]
- GENOM: circuit-level optimizer based on a modified genetic algorithm kernelJ. Silva, N. Horta. 745-748 [doi]
- Identification of complement single variable symmetry in Boolean functions through Walsh transformSudha Kannurao, Bogdan J. Falkowski. 745-748 [doi]
- Efficient algorithms for planar embedding of graphs with constraints in placing specified vertices on face boundariesT. Ozawa. 749-752 [doi]
- Tolerance design of DC-DC switching regulatorsMassimo Vitelli, Giovanni Spagnuolo, Nicola Femia. 751-754 [doi]
- A new approach to modeling statistical variations in MOS transistorsGülin Tulunay, Günhan Dündar, A. Ataman. 757-760 [doi]
- High-performance FIR generation based on a timing-driven architecture and component selection methodJ. C.-Y. Kao, C.-F. Su, Allen C.-H. Wu. 759-762 [doi]
- Design and implementation of multiplier-less tunable 2-D FIR filters using McClellan transformationK. S. Yeung, S. C. Chan. 761-764 [doi]
- Multiple sequence families with efficient hardware architecture for use in spread spectrum watermarkingC. S. Lim, Saman S. Abeysekera, Thambipillai Srikanthan, S. K. Amarasinghe. 761-764 [doi]
- An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT coreYi Yang, Chunyan Wang, M. Omair Ahmad, M. N. S. Swamy. 763-766 [doi]
- Tracking instantaneous frequency using two-sided linear predictionAbdellah Kacha, Khier Benmahammed. 765-768 [doi]
- A high performance JPEG2000 architectureKishore Andra, Chaitali Chakrabarti, Tinku Acharya. 765-768 [doi]
- New algorithms for computing the minimum eigenpair of the generalized symmetric eigenvalue problemM. A. Hasan. 767-770 [doi]
- An improvement of convergence of FFT-based numerical inversion of Laplace transformsA. Yonemoto, Takashi Hisakado, Kohshi Okumura. 769-772 [doi]
- Optimization of portable system architecture for real-time 3D graphicsJu-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo. 769-772 [doi]
- Efficient pass-parallel architecture for EBCOT in JPEG2000Jen-Shiun Chiang, Yu-Sen Lin, Chang-Yo Hsieh. 773-776 [doi]
- Designing multiplier blocks with low logic depthAndrew G. Dempster, Süleyman Sirri Demirsoy, Izzet Kale. 773-776 [doi]
- An efficient architecture of DCTQ module in MPEG-4 video codecKibum suh, SeongMo Park, Seongmin Kim, Bontae Koo, Igkyun Kim, Kyungsoo Kim, Hanjin Cho. 777-780 [doi]
- CMOS auto-ranging PLL for low-voltage wideband systemsYi-Cheng Chang, E. W. Greeneich. 779-782 [doi]
- Efficient digit-serial normal basis multipliers over GF(2/sup m/)Arash Reyhani-Masoleh, M. Anwar Hasan. 781-784 [doi]
- Lossless, near-lossless and lossy adaptive coding based on the lossless DCTSomchart Chokchaitam, Masahiro Iwahashi. 781-784 [doi]
- Programmable video clock synthesizer with sub 0.5 ns driftCyril Lahuec, J. Horan, J. Duigan. 783-786 [doi]
- Low power finite field multiplication and division in re-configurable Reed-Solomon codecZhan Yu. 785-788 [doi]
- Canny edge based image expansionHongjian Shi, R. Ward. 785-788 [doi]
- A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizersYiwu Tang, M. Ismail, S. Bibyk. 787-790 [doi]
- Lossless wavelet image coding using layered coefficient partitioningKwok-Wai Cheung, Lai-Man Po. 789-792 [doi]
- Systolic architectures for finite field inversion and divisionZhiyuan Yan, Dilip V. Sarwate. 789-792 [doi]
- A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scalingK. Shu, Edgar Sánchez-Sinencio, José Silva-Martínez. 791-794 [doi]
- Design of a high-speed Reed-Solomon decoderJae Hyun Baek, J. Y. Kang, Myung Hoon Sunwoo. 793-796 [doi]
- Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNATommy Kwong-Kin Tsang, Mourad N. El-Gamal. 795-798 [doi]
- Tradeoff analysis of FPGA based elliptic curve cryptographyMarcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi. 797-800 [doi]
- A hierarchical fast encoding algorithm for vector quantization with PSNR equivalent to full searchZhibin Pan, Koji Kotani, Tadahiro Ohmi. 797-800 [doi]
- Analysis of CMOS RF LNAs with ESD protectionV. Chandrasekhar, Kartikeya Mayaram. 799-802 [doi]
- Floating-gate EEPROM cell model based on MOS model 9Jean Michel Portal, L. Forli, Didier Née. 799-802 [doi]
- Power characterization of digital filters implemented on FPGAGian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re. 801-804 [doi]
- A monolithic 2.45 GHz, 0.56 W power amplifier with 45 PAE at 2.4 V in standard 25 GHz f::T:: Si-bipolarW. Bakalski, Werner Simbürger, Daniel Kehrer, Hans-Dieter Wohlmuth, M. Rest, Arpad L. Scholtz. 803-806 [doi]
- Efficient architecture for FPGA-based microcontrollersJúlio C. B. de Mattos, Luigi Carro. 805-808 [doi]
- A 2 GHz CMOS even harmonic mixer for direct conversion receiversSher Jiun Fang, See Taur Lee, David J. Allstot, A. Bellaouar. 807-810 [doi]
- A power-configurable bus for embedded systemsChuanjun Zhang, Frank Vahid. 809-812 [doi]
- Gain/phase imbalance and DC offset compensation in quadrature modulatorsXinping Huang, Mario Caron. 811-814 [doi]
- A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementationWei Wang 0003, M. N. S. Swamy, M. Omair Ahmad. 813-816 [doi]
- New design methods of FIR filters with signed power of two coefficients based on a new linear programming relaxation with triangle inequalitiesR. Ito, T. Fujie, K. Suyama, R. Hirabayashi. 813-816 [doi]
- Finite-length synthesis filters for non-uniformly time-interleaved analog-to-digital converterWon Namgoong. 815-818 [doi]
- A two-pass optimal motion-threading technique for 3D wavelet video codingLin Luo, Feng Wu, Shipeng Li, Zhenquan Zhuang, Ya-Qin Zhang. 819-822 [doi]
- Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithmL.-P. Lafrance, Marc-André Cantin, Yvon Savaria, S. H. Sung, Pierre Lavoie. 823-826 [doi]
- A robust frequency compensation scheme for LDO regulatorsC. K. Chava, J. Silva-Martinez. 825-828 [doi]
- An efficient approach for designing nearly perfect-reconstruction low-delay cosine-modulated filter banksRobert Bregovic, Tapio Saramäki. 825-828 [doi]
- Adaptive wavelet thresholding for time varying SNR signal denoisingGuangming Shi, Xiaoping Li, Licheng Jiao, Zhao Wei. 827-829 [doi]
- A compact DC/AC inverter for automotive applicationItsda Boonyaroonate, S. Mori. 829-832 [doi]
- Step-response-based characterization of nonuniform perfect-reconstruction filter banksSaed Samadi, Akinori Nishihara, M. Omair Ahmad, M. N. S. Swamy. 829-832 [doi]
- An improved bandgap reference with high power supply rejectionSiew Kuok Hoon, Jun Chen, Franco Maloberti. 833-836 [doi]
- Complex modulated critically sampled filter banks based on cosine and sine modulationAri Viholainen, Tobias Hidalgo Stitz, Juuso Alhava, Tero Ihalainen, Markku Renfors. 833-836 [doi]
- A simple simulation method for analyzing substrate couplingT. Kimura. 834-837 [doi]
- Application of unimodular matrices to signal compressionSee-May Phoong, Yuan-Pei Lin. 837-840 [doi]
- Analysis of a power topology for a quasi-resonant fast on-load tap changing regulatorR. Echavarría, V. Sanchez, Mario Ponce, M. Cotorogea, A. Claudio. 837-840 [doi]
- Timing analysis of tree-like RLC circuitsB. Rajendran, V. Kheterpal, A. Das, J. Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti. 838-841 [doi]
- Chip-interleaved block-spread CDMA for the downlink with inter-cell interference and soft hand-offShengli Zhou, Pengfei Xia, Geert Leus, Georgios B. Giannakis. 841-844 [doi]
- Derivation of the buck-boost PWM DC-DC converter circuit topologyBrad Bryant, Marian K. Kazimierczuk. 841-844 [doi]
- Blind equalization by sequential importance samplingJoaquín Míguez, Petar M. Djuric. 845-848 [doi]
- Performance analysis of online dual slope delta modulated PWM inverterR. Razali, V. Subbiah, M. A. Choudhury, R. Yusof. 845-848 [doi]
- Incorporation of input glitches into power macromodelingXun Liu, Marios C. Papaefthymiou. 846-849 [doi]
- A new algorithm for QAM signal classification in AWGN channelsT. A. Drumright, Zhi Ding. 849-852 [doi]
- Measurement of open-loop small-signal control-to-output transfer function of a PWM boost converter operated in DCMAlberto Reatti, L. Pellegrini, Marian K. Kazimierczuk. 849-851 [doi]
- A coefficient memory addressing scheme for VLSI implementation of FFT processorsM. Hasan, Tughrul Arslan. 850-853 [doi]
- Random number generator architecture and VLSI implementationNicolas Sklavos, Paris Kitsos, K. Papadomanolakis, Odysseas G. Koufopavlou. 854-857 [doi]
- Space-time codes for high bit rate wireless communications: asymptotic performance of space-time random codesM. Hayajneh, A. Scaglione. 857-860 [doi]
- A SET quantizer circuit aiming at digital communication systemSantanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq. 860-863 [doi]
- MIMO wireless channels made simpleAkbar M. Sayeed. 861-864 [doi]
- Rise time analysis of MOBILE circuitTetsuya Uemura, Pinaki Mazumder. 864-867 [doi]
- An adaptive data compression scheme for memory traffic minimization in processor-based systemsLuca Benini, Davide Bruni, Bruno Riccò, Alberto Macii, Enrico Macii. 866-869 [doi]
- Low cost floating-point unit design for audio applicationsSung-Won Lee, In-Cheol Park. 869-872 [doi]
- CASCADE - configurable and scalable DSP environmentTay-Jyi Lin, Chein-Wei Jen. 870-873 [doi]
- Register-based reordering networks for matrix transposeJ. H. Takala, T. S. Jarvinen, J. A. Nikara. 874-877 [doi]
- A novel floating-gate multiple-valued CMOS full-adderYngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin. 877-880 [doi]
- Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth systemParis Kitsos, Nicolas Sklavos, Nicolas G. Koufopavlou. 878-881 [doi]
- Multi-valued logic function implementation with novel current-mode logic gatesTurgay Temel, Avni Morgul. 881-884 [doi]
- VLSI architectures for the implementation of the Wigner distributionD. Zografos, Konstantina Karagianni, Thanos Stouraitis. 882-885 [doi]
- On the optimal labeling for pseudo-chaotic phase hoppingZbigniew Galias, Gian Mario Maggio. 883-886 [doi]
- Fast soft-output Viterbi decoding for duo-binary turbo codesYannick Saouter, Claude Berrou. 885-888 [doi]
- Architectural support for detection of sleepy eye behaviorA. Chihoub, Z. B. Miled. 886-889 [doi]
- High-speed add-compare-select units using locally self-resetting CMOSGunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi. 889-892 [doi]
- Folded sums of chaotic trajectories distribute uniformlySergio Callegari, Riccardo Rovatti, Gianluca Setti. 891-894 [doi]
- A reconfigurable superimposed 2D-mesh array for channel equalizationO. Gay-Bellile, X. Marchal, G. Burns, K. Vaidyanathan. 893-896 [doi]
- On the correlation of non-jittered and chaotically-jittered PWM signals carrying maximum informationRiccardo Rovatti, Sergio Callegari, Gianluca Setti. 895-898 [doi]
- Enabling high-speed turbo-decoding through concurrent interleavingMichael J. Thul, Norbert Wehn, L. P. Rao. 897-900 [doi]
- High speed VLSI architecture design for block turbo decoderZhipei Chi, Keshab K. Parhi. 901-904 [doi]
- Dynamic stage matching for parallel pipeline A/D convertersG. Bernardinis, Piero Malcovati, Franco Maloberti, E. Soenen. 905-908 [doi]
- High-speed pipelined A/D converter using time-shifted CDS techniqueJipeng Li, Un-Ku Moon. 909-912 [doi]
- A 115mW 12-bit 50 MSPS pipelined ADCS. Mathur, M. Das, Preetam Tadeparthy, S. Ray, S. Mukherjee, B. L. Dinakaran. 913-916 [doi]
- Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversionB. Vaz, Nuno F. Paulino, João Goes, R. Costa, Romero Tavares, Adolfo Steiger-Garção. 921-924 [doi]