Abstract is missing.
- Achieving high transition delay fault coverage with partial DTSFF scan chainsGefu Xu, Adit D. Singh. 1-9 [doi]
- California scan architecture for high quality and low power testingKyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey. 1-10 [doi]
- A novel scheme to reduce power supply noise for high-quality at-speed scan testingXiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang. 1-10 [doi]
- Verification and debugging of IDDQ test of low power chipsMichael Laisne, Triphuong Nguyen, Song-lin Zuo, Xiangdong Pan, Hailong Cui, Cher Bai, A. Street, M. Parley, Neetu Agrawal, K. Sundararaman. 1-7 [doi]
- High throughput non-contact SiP testingBrian Moore, Chris Sellathamby, Philippe Cauvet, Hérvé Fleury, M. Paulson, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Igor M. Filanovsky, Steven Slupsky. 1-10 [doi]
- A concurrent approach for testing address decoder faults in eFlash memoriesOlivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga. 1-10 [doi]
- SPARTAN: a spectral and information theoretic approach to partial-scanOmar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal. 1-10 [doi]
- The design-for-testability features of a general purpose microprocessorDa Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li 0001. 1-9 [doi]
- Silicon evaluation of longest path avoidance testing for small delay defectsRitesh P. Turakhia, W. Robert Daasch, Mark Ward, John Van Slyke. 1-10 [doi]
- A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failuresGuo Yu, Peng Li. 1-10 [doi]
- JTAG system test in a MicroTCA worldBradford G. Van Treuren, Adam W. Ley. 1-10 [doi]
- Real-time signal processing - a new PLL test approachHideo Okawara. 1-9 [doi]
- Delay defect diagnosis using segment network faultsOsei Poku, Ronald D. Blanton. 1-10 [doi]
- A bead probe CAD strategy for in-circuit testKenneth P. Parker, Don DeMille. 1-8 [doi]
- Cost effective manufacturing test using mission mode testsParmod Aggarwal. 1-8 [doi]
- An efficient SAT-based path delay fault ATPG with an unified sensitization modelShun-Yen Lu, Ming-Ting Hsieh, Jing-Jia Liou. 1-7 [doi]
- Testing for systematic defects based on DFM guidelinesDongok Kim, Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau. 1-10 [doi]
- Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching networkCarl Edward Gray, Odile Liboiron-Ladouceur, David C. Keezer, Keren Bergman. 1-9 [doi]
- Using built-in sensors to cope with long duration transient faults in future technologiesCarlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Egas Henes Neto, Gilson I. Wirth, Luigi Carro. 1-10 [doi]
- Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chipZahi S. Abuhamdeh, Vincent D'Alassandro, Richard Pico, Dale Montrone, Alfred L. Crouch, Andrew Tracy. 1-10 [doi]
- On using lossless compression of debug data in embedded logic analysisEhab Anis, Nicola Nicolici. 1-10 [doi]
- Rapid UHF RFID silicon debug and production testingUdaya Shankar Natarajan, Hemalatha Shanmugasundaram, Prachi Deshpande, Chin Soon Wah. 1-10 [doi]
- An algorithm to evaluate wide-band quadrature mixersKoji Asami. 1-7 [doi]
- A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTsJing Li, Swaroop Ghosh, Kaushik Roy. 1-10 [doi]
- Enhanced testing of clock faultsTeresa L. McLaurin, Rich Slobodnik, Kun-Han Tsai, Ana Keim. 1-9 [doi]
- A selt-testing BOST for high-frequency PLLs, DLLs, and SerDesStephen K. Sunter, Aubin Roy. 1-8 [doi]
- Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutionsSwarup Bhunia, Kaushik Roy. 1-10 [doi]
- A universal DC to logic performance correlationAndrew Marshall. 1-4 [doi]
- On-chip timing uncertainty measurements on IBM microprocessorsRobert L. Franch, Phillip Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem. 1-7 [doi]
- Implementing bead probe technology for in-circuit test: A case studyMike Farrell, Glen Leinbach. 1-8 [doi]
- Power-aware test: Challenges and solutionsSrivaths Ravi. 1-10 [doi]
- Critical roles of RF and microwave electromagnetic field solver simulators in multi-gigabit high-speed digital applicationsMinh Quach, Mark Hinton, Regee Petaja. 1-9 [doi]
- Statistical analysis and optimization of parametric delay testSean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir. 1-10 [doi]
- Testing of Vega2, a chip multi-processor with spare processorsSamy Makar, Tony Altinis, Niteen Patkar, Janet Wu. 1-10 [doi]
- Fully X-tolerant combinational scan compressionPeter Wohl, John A. Waicukauski, Sanjay Ramnath. 1-10 [doi]
- Faster defect localization in nanometer technology based on defective cell diagnosisManish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann. 1-10 [doi]
- Efficient power droop aware delay fault testingBin Li, Lei Fang, Michael S. Hsiao. 1-10 [doi]
- Diagnosis for MRAM write disturbance faultChin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao. 1-9 [doi]
- Dependable clock distribution for crosstalk aware designYukiya Miura. 1-9 [doi]
- Design-for-reliability: A soft error case studyMing Zhang. 1 [doi]
- Efficient simulation of parametric faults for multi-stage analog circuitsFang Liu, Sule Ozev. 1-9 [doi]
- Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patternsGaurav Bhargava, Dale Meehl, James Sage. 1-7 [doi]
- SiP-test: Predicting delivery qualityAlex S. Biewenga, Frans de Jong. 1-10 [doi]
- The new ATE: Protocol awareAndrew C. Evans. 1-10 [doi]
- A complete test set to diagnose scan chain failuresRuifeng Guo, Yu Huang 0005, Wu-Tung Cheng. 1-10 [doi]
- X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISRNur A. Touba. 1-10 [doi]
- Sigma-delta ADC characterization using noise transfer function pole-zero trackingHochul Kim, Kye-Shin Lee. 1-9 [doi]
- Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQKunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy. 1-10 [doi]
- IJTAG: The path to organized instrument connectivityAlfred L. Crouch. 1-10 [doi]
- Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applicationsJose Moreira, Heidi Barnes, Guenter Hoersch. 1-10 [doi]
- A matched expansion MEMS probe card with low CTE LTCC substrateSeong-Hun Choe, Shuji Tanaka, Masayoshi Esashi. 1-6 [doi]
- Statistical test: A new paradigm to improve test effectiveness & efficiencyPeter M. O'Neill. 1-10 [doi]
- Measurement ratio testing for improved quality and outlier detectionJeffrey L. Roehr. 1-10 [doi]
- Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCsQiang Xu, Yubin Zhang, Krishnendu Chakrabarty. 1-9 [doi]
- Mining-guided state justification with partitioned navigation tracksAnkur Parikh, Weixin Wu, Michael S. Hsiao. 1-10 [doi]
- Automotive IC's: less testing, more preventionDavide Appello. 1-2 [doi]
- A fully digital-compatible BIST strategy for ADC linearity testingHanqing Xing, Hanjun Jiang, Degang Chen, Randall L. Geiger. 1-10 [doi]
- Enhancing signal controllability in functional test-benches through automatic constraint extractionOnur Guzey, Li-C. Wang, Jayanta Bhadra. 1-10 [doi]
- Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challengesSachin Idgunji. 1-10 [doi]
- Pattern-directed circuit virtual partitioning for test power reductionQiang Xu, Dianwei Hu, Dong Xiang. 1-10 [doi]
- Redefining and testing interconnect faults in Mesh NoCsÉrika F. Cota, Fernanda Lima Kastensmidt, Maico Cassel, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski. 1-10 [doi]
- Management of common-mode currents in semiconductor ATEWilliam J. Bowhers. 1-9 [doi]
- Fundamentals of timing information for test: How simple can we get?Rohit Kapur, Jindrich Zejda, Thomas W. Williams. 1-7 [doi]
- A comparative study of continuous sampling plans for functional board testingJukka Antila, Timo Karhu. 1-7 [doi]
- Which defects are most critical? optimizing test sets to minimize failures due to test escapesJennifer Dworak. 1-10 [doi]
- Low cost automatic mixed-signal board test using IEEE 1149.4Srividya Sundar, Bruce C. Kim, Toby Byrd, Felipe Toledo, Sudhir Wokhlu, Erika Beskar, Raul Rousselin, David Cotton, Gary Kendall. 1-9 [doi]
- Novel compensation scheme for local clocks of high performance microprocessorsCecilia Metra, Martin Omaña, T. M. Mak, Simon Tam. 1-9 [doi]
- Data jitter measurement using a delta-time-to-voltage converter methodKiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma. 1-7 [doi]
- A practical approach to comprehensive system test & debug using boundary scan based test architectureTapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren. 1-10 [doi]
- Finding power/ground defects on connectors - a new approachKenneth P. Parker, Stephen Hird. 1-7 [doi]
- Advancements in at-speed array BIST: multiple improvementsKevin Gorman, Michael Roberge, Adrian Paparelli, Gary Pomichter, Stephen Sliva, William Corbin. 1-10 [doi]
- Functional testing of digital microfluidic biochipsTao Xu, Krishnendu Chakrabarty. 1-10 [doi]
- Gate delay ratio model for unified path delay analysisYukio Okuda. 1-10 [doi]
- Backside E-Beam Probing on Nano scale devicesRudolf Schlangen, Reiner Leihkauf, Uwe Kerst, Christian Boit, Rajesh Jain, Tahir Malik, Keneth R. Wilsher, Ted Lundquist, Bernd Krüger. 1-9 [doi]
- Interconnect open defect diagnosis with minimal physical informationChen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang. 1-10 [doi]
- A heuristic for thermal-safe SoC test schedulingZhiyuan He, Zebo Peng, Petru Eles. 1-10 [doi]
- Fast and effective fault simulation for path delay faults based on selected testable pathsDong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara. 1-10 [doi]
- Impact of Quad Flat No Lead package (QFN) on automated X-ray inspection (AXI)Tee Chwee Liong, Andy Pascual. 1-10 [doi]
- Where is car IC testing going?Steve Comen. 1 [doi]
- Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled DefectsJeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke. 1-10 [doi]
- Estimating stuck fault coverage in sequential logic using state traversal and entropy analysisSoumitra Bose, Vishwani D. Agrawal. 1-10 [doi]
- GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologiesMichael Nicolaidis. 1-10 [doi]
- Low cost characterization of RF transceivers through IQ data analysisErkan Acar, Sule Ozev. 1-10 [doi]
- Circuit failure prediction to overcome scaled CMOS reliability challengesSubhasish Mitra, Mridul Agarwal. 1-3 [doi]
- A scanisland based design enabling prebond testability in die-stacked microprocessorsDean L. Lewis, Hsien-Hsin S. Lee. 1-8 [doi]
- Design for test features of the ARM clock control macroFrank Frederick, Teresa L. McLaurin. 1-8 [doi]
- Multi-GHz loopback testing using MEMs switches and SiGe logicDavid C. Keezer, Dany Minier, Patrice Ducharme, Doris Viens, Greg Flynn, John McKillop. 1-10 [doi]
- New methods for receiver internal jitter measurementMike P. Li, Jinhua Chen. 1-10 [doi]
- Test yield estimation for analog/RF circuits over multiple correlated measurementsFang Liu, Erkan Acar, Sule Ozev. 1-10 [doi]
- A low cost test data compression technique for high n-detection fault coverageSeongmoon Wang, Zhanglei Wang, Wenlong Wei, Srimat T. Chakradhar. 1-10 [doi]
- Protocol requirements in an SJTAG/IJTAG environmentGunnar Carlsson, Johan Holmqvist, Erik Larsson. 1-9 [doi]
- On ATPG for multiple aggressor crosstalk faults in presence of gate delaysKunal P. Ganeshpure, Sandip Kundu. 1-7 [doi]
- Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generationAnis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise. 1-10 [doi]
- ERTG: A test generator for error-rate testingShideh Shahidi, Sandeep K. Gupta. 1-10 [doi]
- Analyzing the risk of timing modeling based on path delay testsPouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir. 1-10 [doi]
- Modeling facet roughening errors in self-assembly by snake tile setsXiaojun Ma, Jing Huang, Fabrizio Lombardi. 1-10 [doi]
- Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniquesAndreas Leininger, Martin Fischer, Michael Richter, Michael Gössel. 1-9 [doi]
- Diagnose compound scan chain and system logic defectsYu Huang 0005, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann. 1-10 [doi]
- A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan testV. R. Devanathan, C. P. Ravikumar, V. Kamakoti. 1-10 [doi]
- How to ensure zero defects from the beginning with semiconductor test methodsBernd Gessner. 1-2 [doi]
- An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test timeTakahiro J. Yamaguchi, H. X. Hou, Koji Takayama, Dave Armstrong, Masahiro Ishida, Mani Soma. 1-8 [doi]
- ACCE: Automatic correction of control-flow errorsRamtilak Vemu, Sankar Gurumurthy, Jacob A. Abraham. 1-10 [doi]
- A methodology for detecting performance faults in microprocessors via performance monitoring hardwareMiltiadis Hatzimihail, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis. 1-10 [doi]
- Programmable deterministic Built-In Self-TestAbdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef. 1-9 [doi]
- Principles and results of some test cost reduction methods for ASICsPeter Maxwell. 1-5 [doi]
- PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan testV. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti. 1-9 [doi]
- Delay fault simulation with bounded gate delay modeSoumitra Bose, Hillary Grimes, Vishwani D. Agrawal. 1-10 [doi]
- Test cost reduction for the AMD™ Athlon processor using test partitioningAnuja Sehgal, Jeff Fitzgerald, Jeff Rearick. 1-10 [doi]
- A stereo audio Σ∑ ADC architecture with embedded SNDR self-testLuís Rolíndez, Salvador Mir, Jean-Louis Carbonéro, Dimitri Goguet, Nabil Chouba. 1-10 [doi]
- On the saturation of n-detection test sets with increased nIrith Pomeranz, Sudhakar M. Reddy. 1-10 [doi]
- Car IC test changing but the same quality goalGary Wittie. 1 [doi]
- A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ataYongquan Fan, Yi Cai, Zeljko Zilic. 1-10 [doi]
- Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chipRobert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh. 1-8 [doi]
- IEEE P1581 can solve your board level memory cluster test problemsHeiko Ehrenberg. 1-9 [doi]