Abstract is missing.
- Power-Aware, Reliable Microprocessor DesignPradip Bose. 3 [doi]
- High-Speed Interconnect Technology: On-Chip and Off-ChipSachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani. 7 [doi]
- Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road AheadR. D. (Shawn) Blanton, Subhasish Mitra. 8-9 [doi]
- SoC Design Methodology: A Practical ApproachAtul Jain, Anindya Saha, Jagdish Rao. 10-11 [doi]
- Test Methodologies in the Deep Submicron Era -- Analog, Mixed-Signal, and RFAbhijit Chatterjee, Ali Keshavarzi, Amit Patra, Siddhartha Mukhopadhyay. 12-13 [doi]
- Recent Advances in Verification, Equivalence Checking and SAT-SolversDhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea. 14 [doi]
- Compact MOSFET Models for Low Power Analog CMOS DesignA. B. Bhattacharyya. 15 [doi]
- Physics and Technology: Towards Low-Power DSM DesignD. Mukhopadhyay, P. K. Basu, V. R. Rao. 16-17 [doi]
- Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded SystemsLuca Benini, Sandeep K. Shukla, Rajesh K. Gupta. 18 [doi]
- The High Walls have CrumpledC. L. Liu. 21 [doi]
- 65nm OmnibudsmanTed Vucurevich. 25 [doi]
- ESL - The Next Leadership Opportunity for India?Alan Naumann. 26 [doi]
- VLSI Design Challenges for Gigascale IntegrationShekhar Y. Borkar. 27 [doi]
- Moore s Law is UnconstitutionalWalden C. Rhines. 31-32 [doi]
- Configurable Processor the Building Block for SOC (System-On-a-Chip)Béatrice Fu. 35 [doi]
- Modeling Usable and Reusable Transactors in System VerilogJanick Bergeron. 36 [doi]
- Optimizing SoC ManufacturabilityYervant Zorian. 37-38 [doi]
- Tuple Detection for Path Delay Faults: A Method for Improving Test Set QualityIrith Pomeranz, Sudhakar M. Reddy. 41-46 [doi]
- A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor DefectsHaihua Yan, Adit D. Singh. 47-52 [doi]
- Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP CoresLei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan. 53-58 [doi]
- On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction RatiosHuaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz. 59-64 [doi]
- Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-ChipLoganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar. 65-70 [doi]
- Cellular Automata Based Test Structures with Logic FoldingBiplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das. 71-74 [doi]
- Electromigration-Aware Physical Design of Integrated CircuitsJens Lienig, Göran Jerke. 77-82 [doi]
- Variance Reduction in Monte Carlo Capacitance ExtractionShabbir H. Batterywala, Madhav P. Desai. 85-90 [doi]
- A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay ModelYibo Wang, Yici Cai, Xianlong Hong. 91-96 [doi]
- Improved Layout-Driven Area-Constrained Timing Optimization by Net BufferingRajeev Murgai. 97-102 [doi]
- Battery Model for Embedded SystemsVenkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet. 105-110 [doi]
- Rapid Embedded Hardware/Software System GenerationJorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran. 111-116 [doi]
- A Unified Architecture for Adaptive Compression of Data and Code on Embedded SystemsHaris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar. 117-123 [doi]
- A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode SystemsPraveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim, Thomas Chen. 124-129 [doi]
- A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCsAshok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar. 130-133 [doi]
- Implementing LDPC Decoding on Network-on-ChipTheo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin. 134-137 [doi]
- A RISC Hardware Platform for Low Power JavaPaul Capewell, Ian Watson. 138-143 [doi]
- A Low Power Reprogrammable Parallel Processing VLSI Architecture for Computation of B-Spline Based Medical Image Processing System for Fast Characterization of Tiny Objects Suspended in Cellular FluidSabyasachi Mondal, Arijit De, P. K. Biswas. 147-152 [doi]
- Design of a Low Power Image Watermarking Encoder Using Dual Voltage and FrequencySaraju P. Mohanty, N. Ranganathan, K. Balakrishnan. 153-158 [doi]
- Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold VoltagesAbdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh. 159-164 [doi]
- Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm CircuitsShengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang. 165-170 [doi]
- Charge-Recovery Power Clock Generators for Adiabatic Logic CircuitsMuhammad Arsalan, Maitham Shams. 171-174 [doi]
- Power Optimization in Current Mode CircuitsM. S. Bhat, H. S. Jamadagni. 175-180 [doi]
- Lazy Constraints and SAT Heuristics for Proof-Based AbstractionAarti Gupta, Malay K. Ganai, Pranav Ashar. 183-188 [doi]
- Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDsKameshwar Chandrasekar, Michael S. Hsiao. 189-194 [doi]
- A Verification System for Transient Response of Analog Circuits Using Model CheckingTathagato Rai Dastidar, P. P. Chakrabarti. 195-200 [doi]
- Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault ModelSayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix. 201-206 [doi]
- A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-ChipK. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti. 207-212 [doi]
- Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to ModulesPrasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti. 213-218 [doi]
- Design, Testing, and Applications of Digital Microfluidics-Based BiochipsKrishnendu Chakrabarty. 221-226 [doi]
- Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based NanotechnologiesRui Zhang, Pallav Gupta, Niraj K. Jha. 229-234 [doi]
- Design, Fabrication, Testing and Simulation of Porous Silicon Based Smart MEMS Pressure SensorC. Pramanik, T. Islam, H. Saha, J. Bhattacharya, S. Banerjee, Sagnik Dey. 235-240 [doi]
- A Nanosensor Array-Based VLSI Gas DiscriminatorKevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin. 241-246 [doi]
- Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic ArraysAvik Chakraborty. 249-254 [doi]
- Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel AdderHafiz Md. Hasan Babu, Ahsan Raja Chowdhury. 255-260 [doi]
- Optimization of Mixed Logic Circuits with Application to a 64-Bit Static AdderYuanzhong Wan, Maitham Shams. 261-266 [doi]
- Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy ImplementationXiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee. 267-273 [doi]
- Integrated On-Chip Storage Evaluation in ASIP SynthesisManoj Kumar Jain, M. Balakrishnan, Anshul Kumar. 274-279 [doi]
- Extracting Exact Finite State Machines from Behavioral SystemC DescriptionsVikram Singh Saun, Preeti Ranjan Panda. 280-285 [doi]
- A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback ModeAchintya Halder, Soumendu Bhattacharya, Ganesh Srinivasan, Abhijit Chatterjee. 289-294 [doi]
- Effects of Technology and Dimensional Scaling on Input Loss Prediction of RF MOSFETsTejasvi Das, Clyde Washburn, P. R. Mukund, Steve Howard, Ken Paradis, Jung-Geau Jang, Jan Kolnik, Jeff Burleson. 295-300 [doi]
- Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode LogicTin Wai Kwan, Maitham Shams. 301-306 [doi]
- Design of Second-Order Sub-Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage ApplicationsRajarshi Paul, Amit Patra, Shailendra Baranwal, Kaushik Dash. 307-312 [doi]
- A 160MSPS 8-Bit Pipeline Based ADCSamiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee. 313-318 [doi]
- A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm:::2::: Segmented Current Steering CMOS DACSamiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey. 319-322 [doi]
- Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip CommunicationAtul Katoch, Maurice Meijer, Sanjeev K. Jain. 325-329 [doi]
- An Efficient Methodology for Noise CharacterizationGaurav Kumar Varshney, Sreeram Chandrasekar. 330-335 [doi]
- Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS CircuitsSreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney. 336-341 [doi]
- Crosstalk Noise Analysis at Multiple FrequenciesSachin Shrivastava, Sreeram Chandrasekar. 342-347 [doi]
- Worst-Case Crosstalk Noise Analysis Based on Dual-Exponential Noise MetricsJiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye. 348-353 [doi]
- ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM ChipsAjoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel. 354-359 [doi]
- Impact of Process Variations on Multi-Level Signaling for On-Chip InterconnectsVishak Venkatraman, Wayne Burleson. 362-367 [doi]
- A Quasi-Delay-Insensitive Method to Overcome Transistor VariationC. Brej, Jim D. Garside. 368-373 [doi]
- Influence of Leakage Reduction Techniques on Delay/Leakage UncertaintyYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 374-379 [doi]
- Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local ExpansionBaohua Wang, Pinaki Mazumder. 380-385 [doi]
- Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETsA. Madan, S. C. Bose, P. J. George, Chandra Shekhar. 386-391 [doi]
- Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF ApplicationsR. Srinivasan, Navakanta Bhat. 392-396 [doi]
- A Methodology and Tooling Enabling Application Specific Processor DesignAndreas Hoffmann, Frank Fiedler, Achim Nohl, Surender Parupalli. 399-404 [doi]
- An Efficient End to End Design of Rijndael Cryptosystem in 0.18 ? CMOSDebdeep Mukhopadhyay, Dipanwita Roy Chowdhury. 405-410 [doi]
- ADOPT: An Approach to Activity Based Delay OptimizationGaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan. 411-416 [doi]
- Coding for Reliable On-Chip Buses: Fundamental Limits and Practical CodesSrinivasa R. Sridhara, Naresh R. Shanbhag. 417-422 [doi]
- False Path and Clock Scheduling Based Yield-Aware Gate SizingJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja. 423-426 [doi]
- Variable Resizing for Area Improvement in Behavioral SynthesisR. Gopalakrishnan, Rajat Moona. 427-430 [doi]
- Orthogonal Circuit Visualization Improved by Merging the Placement and Routing PhasesThomas Eschbach, Wolfgang Günther, Bernd Becker. 433-438 [doi]
- Lithography Driven Layout DesignManish Garg, Laurent Le Cam, Matthieu Gonzalez. 439-444 [doi]
- Non-Manhattan Routing Using a Manhattan RouterEdward Hursey, Nikhil Jayakumar, Sunil P. Khatri. 445-450 [doi]
- Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector MachinesR. Manimegalai, E. Siva Soumya, V. Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia. 451-456 [doi]
- Automatic Device Layout Generation for Analog Layout RetargetingRoy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi. 457-462 [doi]
- Floorplan-Based Crosstalk Estimation for Macrocell-Based DesignsSuvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran. 463-468 [doi]
- Distance Restricted Scan Chain Reordering to Enhance Delay Fault CoverageWei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy. 471-478 [doi]
- Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI CircuitsAniket, Ravishankar Arunachalam. 479-484 [doi]
- An Ultra-Fast, On-Chip BiST for RF Low Noise AmplifiersAnand Gopalan, Tejasvi Das, Clyde Washburn, P. R. Mukund. 485-490 [doi]
- On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST DesignSheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya. 491-496 [doi]
- A Framework for Distributed and Hierarchical Design-for-TestC. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar. 497-503 [doi]
- A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and WaveletsP. Kalpana, K. Gunavathi. 504-507 [doi]
- Conventional RC oscillators, though offer inexpensiveProgrammable High Frequency RC OscillatorFalguni Bala, Tapas Nandy. 511-515 [doi]
- Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring OscillatorsJaijeet S. Roychowdhury. 516-521 [doi]
- On-Chip Voltage Regulator with Improved Transient ResponseAshis Maity, R. G. Raghavendra, Pradip Mandal. 522-527 [doi]
- An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility ClassificationMengmeng Ding, Ranga Vemuri. 528-534 [doi]
- A Hierarchical Cost Tree Mutation Approach to Optimization of Analog CircuitsAbhishek Somani, P. P. Chakrabarti, Amit Patra. 535-538 [doi]
- A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device MismatchChih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi. 539-542 [doi]
- Dictionary Based Code Compression for Variable Length Instruction EncodingsDipankar Das, Rajeev Kumar, P. P. Chakrabarti. 545-550 [doi]
- Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible ProcessorsFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 551-556 [doi]
- Evaluation of Speed and Area of Clustered VLIW ProcessorsAndrei Terechko, Manish Garg, Henk Corporaal. 557-563 [doi]
- A Technique for Throughput and Register Optimization during Resource Constrained Pipelined SchedulingNagendran Rangan, Karam S. Chatha. 564-569 [doi]
- Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional UnitsKaushal R. Gandhi, Nihar R. Mahapatra. 570-575 [doi]
- Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power ModelsNikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar. 579-585 [doi]
- Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian NetworksSanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan. 586-591 [doi]
- Energy-Efficient Compressed Address TransmissionJiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra. 592-597 [doi]
- Variable Input Delay CMOS Logic for Low Power DesignTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell. 598-605 [doi]
- Gate Leakage and Its Reduction in Deep Submicron SRAMAnkur Goel, Baquer Mazhari. 606-611 [doi]
- Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open QuestionsParthasarathi Dasgupta. 615-620 [doi]
- ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network SynthesisKrishnan Srinivasan, Karam S. Chatha. 623-628 [doi]
- Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and InterconnectsDharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla. 629-633 [doi]
- A Low-Swing Differential Signaling Scheme for On-Chip Global InterconnectsAshok Narasimhan, Manish Kasotiya, Ramalingam Sridhar. 634-639 [doi]
- Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing OrientationDenis Deschacht, Alain Lopez. 640-643 [doi]
- On Physical-Aware Synthesis of Vertically Integrated 3D SystemsMadhubanti Mukherjee, Ranga Vemuri. 647-652 [doi]
- Energy Efficient Hardware Synthesis of Polynomial ExpressionsAnup Hosangadi, Farzan Fallah, Ryan Kastner. 653-658 [doi]
- Algorithmic Implementation of Low-Power High Performance FIR Filtering IP CoresC. H. Wang, Ahmet T. Erdogan, Tughrul Arslan. 659-662 [doi]
- On-Line Synthesis for Partially Reconfigurable FPGAsRenqiu Huang, Ranga Vemuri. 663-668 [doi]
- A Combinational Logic Mapper for Actel s SX/AX FamilySantanu Chattopadhyay, Manas Kumar Dewangan. 669-672 [doi]
- A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAsKrishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas. 673-676 [doi]
- Power Variability and Its Impact on DesignAnirudh Devgan, Sani R. Nassif. 679-682 [doi]
- An Accurate Energy and Thermal Model for Global Signal BusesKrishnan Sundaresan, Nihar R. Mahapatra. 685-690 [doi]
- Hot Spots and Zones in a Chip: A Geometrician s ViewSubhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty. 691-696 [doi]
- Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI TechnologiesRajiv V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez. 697-702 [doi]
- DFM: Linking Design and ManufacturingSrinivas Raghvendra, Philippe Hurat. 705-708 [doi]
- The Impact of Inductance on Transients Affecting Gate Oxide ReliabilityN. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell. 709-713 [doi]
- An Accurate Probalistic Model for Error DetectionThara Rejimon, Sanjukta Bhanja. 717-722 [doi]
- Using Contrapositive Law in an Implication Graph to Identify Logic RedundanciesKunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell. 723-729 [doi]
- Off-Line Testing of Asynchronous CircuitsDeepali Koppad, Alexandre V. Bystrov, Alexandre Yakovlev. 730-735 [doi]
- Detecting SEU-Caused Routing Errors in SRAM-Based FPGAsE. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan. 736-741 [doi]
- Multiple Fault Testing of Logic Resources of SRAM-Based FPGAsSaurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar. 742-747 [doi]
- A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC SystemsZahid Khan, Tughrul Arslan, Ahmet T. Erdogan. 751-756 [doi]
- Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS ModelsG. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman. 757-761 [doi]
- An Effective VHDL-AMS Simulation Algorithm with Event PartitioningHamid Reza Ghasemi, Zainalabedin Navabi. 762-767 [doi]
- Application of Alpha Power Law Models to PLL Design MethodologyB. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni. 768-773 [doi]
- Exploiting Radio Hierarchies for Power-Efficient Wireless Device Discovery and Connection SetupTrevor Pering, Vijay Raghunathan, Roy Want. 774-779 [doi]
- Fully Integrated CMOS Frequency Synthesizer for ZigBee ApplicationsSaurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta. 780-783 [doi]
- Computer Aided Test (CAT) Tool for Mixed Signal SOCsShibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury. 787-790 [doi]
- A Novel Low Power 16X16 Content Addressable Memory Using PAG. Josemin Bala, J. Raja Paul Perinbam. 791-794 [doi]
- A Principal Component Neural Network-Based Face Recognition System and Its ASIC ImplementationChakka Siva Sai Prasanna, N. Sudha, V. Kamakoti. 795-798 [doi]
- Synthesis of Asynchronous Circuits Using Early Data ValidityNitin Gupta, Doug A. Edwards. 799-803 [doi]
- A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP CoresSudarshan Bahukudumbi, Krishna Bharath. 804-807 [doi]
- A Methodology for Fast Vector Based Power Supply and Substrate Noise AnalysesSankar P. Debnath, Sukumar Jairam, H. Udayakumar. 808-811 [doi]
- An Operational Amplifier Model for Test Planning at Behavioral LevelEduardo Romero, Gabriela Peretti, Carlos A. Marqués. 812-815 [doi]
- Memory-Centric Motion EstimatorAleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan. 816-819 [doi]
- SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential CircuitsMarong Phadoongsidhi, Kewal K. Saluja. 820-823 [doi]
- A New Asymmetric Skewed Buffer Design for Runtime Leakage Power ReductionYu-Shiang Lin, Dennis Sylvester. 824-827 [doi]
- A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor ChipMukul Milind Ojha, Arun Kumar Anand, G. S. Visweswaran, D. Nagchoudhuri. 828-831 [doi]
- Applicability of General Purpose Processors to Network ApplicationsMurthy Durbhakula. 832-835 [doi]
- Power Switch Network Design for MTCMOSRamaprasath Vilangudipitchai, Poras T. Balsara. 836-839 [doi]
- Structural Fault Diagnosis in Charge-Pump Based Phase-Locked LoopsAdityaSankar Medury, Ingvar Carlson, Atila Alvandpour, John Stensby. 842-845 [doi]
- Dual-Edge Triggered Static Pulsed Flip-FlopsAliakbar Ghadiri, Hamid Mahmoodi-Meimand. 846-849 [doi]
- A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit DesignDebashis Dutta, Wouter A. Serdijn, Swapna Banerjee, Sriram Gupta. 850-853 [doi]
- A High Accuracy Bandgap Reference with Chopped Modulator to Compensate MOSFET MismatchLian-xi Liu, Yin-tang Yang, Zhang-ming Zhu. 854-857 [doi]
- A High-Efficiency, Dual-Mode, Dynamic, Buck-Boost Power Supply IC for Portable ApplicationsBiranchinath Sahu, Gabriel A. Rincón-Mora. 858-861 [doi]
- Design Issues in Switched Capacitor Ladder FiltersArindam Basu, Anindya Sundar Dhar. 862-865 [doi]
- ASIC Design of the Linearisation Circuit of a PTC ThermistorShubhajit Roy Chowdhury, C. Pramanik, H. Saha. 866-869 [doi]
- A Reconfigurable Oscillator Topology for Dual-Band OperationTien-Ling Hsieh, Ranjit Gharpurey. 870-873 [doi]
- Reducing Leakage with Mixed-V_th (MVT)Frank Sill, Frank Grassert, Dirk Timmermann. 874-877 [doi]
- System in a Package Design of a RF Front End System Using Application Specific Reduced Order ModelsGhanshyam Nayak, Clyde Washburn, P. R. Mukund. 878-881 [doi]