Abstract is missing.
- 3D stacking using ultra thin diesAntonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, K. J. Rebibis, W. Zhang, Eric Beyne. 1-5 [doi]
- Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC packageToru Ikeda, Masatoshi Oka, Shinya Kawahara, Noriyuki Miyazaki, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada. 1-6 [doi]
- Chip-level TSV integration for rapid prototyping of 3D system LSIsKazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang-Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi. 1-4 [doi]
- Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debondingAlain Phommahaxay, Anne Jourdain, Greet Verbinnen, Tobias Woitke, Peter Bisson, Markus Gabriel, Walter Spiess, Alice Guerrero, Jeremy McCutcheon, Rama Puligadda, Pieter Bex, Axel Van den Eede, Bart Swinnen, Gerald Beyer, Andy Miller, Eric Beyne. 1-4 [doi]
- A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stackFarhad Mehdipour, Krishna Chaitanya Nunna, Lovic Gauthier, Koji Inoue, Kazuaki Murakami. 1-4 [doi]
- 3D multiprocessor with 3D NoC architecture based on Tezzaron technologyMohamad Hairol Jabbar, Dominique Houzet, Omar Hammami. 1-5 [doi]
- A very low area ADC for 3-D stacked CMOS image processing systemKouji Kiyoyama, Kang-Wook Lee, Takafumi Fukushima, H. Naganuma, H. Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Ultra-compact micro-coil realized via multilevel dense TSV coil for MEMs applicationH. Y. Li, L. Xie, L. G. Ong, A. Baram, I. Herer, Arnon Hirshberg, S. C. Chong, D. L. Kwong. 1-4 [doi]
- High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIsK. W. Lee, J.-C. Bea, T. Fukushima, Yuki Ohara, T. Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testingXiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee. 1-8 [doi]
- Numerical analysis of bonding process-induced deformation for 3D packageSung-Hoon Choa, Haeng-Soo Lee, Kyoung-Ho Kim. 1-5 [doi]
- 200°C direct bonding copper interconnects : Electrical results and reliabilityLéa Di Cioccio, Rachid Taibi, C. Chappaz, S. Moreau, Laurent-Luc Chapelon, Thomas Signamarcheix. 1-4 [doi]
- Effect of planarity on the 3D integration in 3-D integrated CMOS image sensorNam Hee Kwon, S. M. Hong, Yong-Won Cha, Sun Jae Lee, Han Gyul Lee, Areum Kim, Soo-Won Kim, Chang-Hyun Kim, Sung Gyu Pyo. 1-3 [doi]
- Recent advances and new trends in nanotechnology and 3D integration for semiconductor industryJohn H. Lau. 1-23 [doi]
- Temporary bonding strength control for self-assembly-based 3D integrationTakafumi Fukushima, Yuki Ohara, Jichoel Bea, Mariappan Murugesan, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbarYuhao Wang, Chun Zhang, Revanth Nadipalli, Hao Yu, Roshan Weerasekera. 1-6 [doi]
- Current stressing effect on interfacial reaction characteristics of Cu pillar/Sn-3.5Ag microbumps for 3D integrationByung-Hyun Kwak, Sung-Hyuk Kim, Young-Bae Park. 1-2 [doi]
- Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architecturesMasoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 1-8 [doi]
- A miniaturized heterogeneous wireless sensor node in 3DICXin Liu, Lei Wang, Mini Jayakrishnan, Jingjing Lan, HongYu Li, Chong Ser Choong, M. Kumara-samy Raja, Yongxin Guo, Wang Ling Goh, Jin He, Shan Gao, Minkyu Je. 1-4 [doi]
- A 3D heterogeneous integration method using LTCC wafer for RF applicationsXiaoyu Mi, Osamu Toyoda, Satoshi Ueda, Fumihiko Nakazawa. 1-5 [doi]
- W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stressMariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Pre-bond testing of die logic and TSVs in high performance 3D-SICsBrandon Noia, Krishnendu Chakrabarty. 1-5 [doi]
- Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked diesKatsuyuki Ikeuchi, Makoto Takamiya, Takayasu Sakurai. 1-5 [doi]
- Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architectureTomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume. 1-6 [doi]
- Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV)F. X. Che, W. N. Putra, A. Heryanto, A. Trigg, S. Gao, C. L. Gan. 1-6 [doi]
- Coordinating 3D designs: Interface IP, standards or free form?Paul D. Franzon, W. Rhett Davis, Zheng Zhou, Shivam Priyadarshi, Matthew Hogan, Tanay Karnik, Ganapti Srinavas. 1-3 [doi]
- TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replicationSeyyed Hasan Moallempour, Seyyed Ahmad Razavi, Morteza Saheb Zamani. 1-5 [doi]
- A study on the edge traces technique for 3D stack chipJae-Hak Lee, Choong D. Yoo, Jun-Yeob Song, Seung S. Lee, Sun-Rak Kim. 1-4 [doi]
- Selection of underfill material in Cu hybrid bonding and its effect on the transistor keep-out-zoneDau Fatt Lim, K. C. Leong, C. S. Tan. 1-4 [doi]
- 3D integration demonstration of a wireless product with design partitioningG. Druais, Pascal Ancey, C. Aumont, V. Caubet, Laurent-Luc Chapelon, C. Chaton, Séverine Cheramy, S. Cordova, E. Cirot, J.-P. Colonna, P. Coudrain, T. Divel, Y. Dodo, Alexis Farcy, N. Guitard, K. Haxaire, N. Hotellier, F. Leverd, R. Liou, J. Michailos, A. Ostrovsky, S. Petitdidier, J. Pruvost, D. Riquet, O. Robin, E. Saugier, Nicolas Sillon. 1-5 [doi]
- Fabrication cost analysis for 2D, 2.5D, and 3D IC designsChao Zhang, Guangyu Sun. 1-4 [doi]
- TSV optimization for BEOL interconnection in logic processSinwoo Kang, Sungdong Cho, Kiyoung Yun, Sangwook Ji, Kisoon Bae, Woonseob Lee, Eunji Kim, Jangho Kim, Jonghoon Cho, Hyongyol Mun, Yeong L. Park. 1-4 [doi]
- High temperature bonding solutions enabling thin wafer process and handling on 3D-IC manufacturingToshiaki Itabashi, Masashi Kotani, Melvin P. Zussman, K. Zoschke, T. Fischer, M. Topper, Hiroyuki Ishida. 1-4 [doi]
- 3D integration of MEMS and CMOS via Cu-Cu bonding with simultaneous formation of electrical, mechanical and hermetic bondsR. Nadipalli, J. Fan, K. H. Li, K. H. Wee, H. Yu, C. S. Tan. 1-5 [doi]
- Effects of 3-D stacked vector cache on energy consumptionRyusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Yusuke Endo, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi. 1-6 [doi]
- Multi-step approach for thermal optimization of 3D-IC and packageAndy Heinig, Christoph Sohrmann. 1-5 [doi]
- Minimization of the local residual stress in 3DICs by controlling the structures and mechanical properties of 3D interconnectionsKota Nakahira, Fumiaki Endo, Ryosuke Furuya, Ken Suzuki, Hideo Miura. 1-6 [doi]
- Advanced TSV filling method with Sn alloy and its reliabilityYoung-Ki Ko, Myong-Suk Kang, Hiroyuki Kokawa, Yutaka S. Sato, Sehoon Yoo, Chang Woo Lee. 1-4 [doi]
- Scalable direct bond technology and applications driving adoptionP. Enquist. 1-5 [doi]
- Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space explorationOmar Hammami, A. M'zah, Khawla Hamwi. 1-4 [doi]
- Copper deep via superfilling by selective accelerator deactivationMasanori Hayase, Naoki Mizukoshi, Masayuki Nagao. 1-4 [doi]
- 2, 3D interconnect using adaptive timing control and low capacitance TSVFutoshi Furuta, Kenichi Osada. 1-4 [doi]
- Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integrationFumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi. 1-4 [doi]
- ∗-treeArtur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke. 1-5 [doi]
- Pathfinder 3D: A flow for system-level design space explorationShivam Priyadarshi, Jianchen Hu, Won Ha Choi, Samson Melamed, Xi Chen, W. Rhett Davis, Paul D. Franzon. 1-8 [doi]
- A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-DrivesTeruyoshi Hatanaka, Koh Johguchi, Ken Takeuchi. 1-4 [doi]
- Study on high performance and productivity of TSV's with new filling method and alloy for advanced 3D-SiPRyohei Sato, Akihiro Tsukada, Yukihiro Sato, Yoshiharu Iwata, Hidenori Murata, Shigenobu Sekine, Ryuji Kimura, Keijiroh Kishi. 1-4 [doi]
- Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking ICWon-Myoung Ki, Myong-Suk Kang, Sehoon Yoo, Chang Woo Lee. 1-4 [doi]
- Using NEM relay to improve 3DIC cost efficiencyTao Zhang, Guangyu Sun. 1-4 [doi]
- Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and designA. Ege Engin, N. Srinidhi Raghavan. 1-4 [doi]
- Analysis of microbump induced stress effects in 3D stacked IC technologiesAndrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, W. Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte. 1-5 [doi]
- Mechanical and electrical reliability of copper interconnections for 3DICNaoki Saito, Naokazu Murata, Kinji Tamakawa, Ken Suzuki, Hideo Miura. 1-6 [doi]
- High density Cu-TSVs and reliability issuesMariappan Murugesan, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Plasma etch and dielectric deposition processes for TSV RevealKeith Buchanan, Dave Thomas, Hefin Griffiths, Kathrine Crook, Daniel Archard, Mark Carruthers, Masahiko Tanaka. 1-2 [doi]
- Low temperature bonding for 3D interconnectsTadatomo Suga, Ryuichi Kondoh. 1-4 [doi]
- 3D stacking using Cu-Cu direct bondingY. H. Hu, C. S. Liu, M. J. Lii, K. J. Rebibis, Anne Jourdain, Antonio La Manna, Gerald Beyer, Eric Beyne, C. H. Yu. 1-4 [doi]
- Interconnect design and analysis for Through Silicon Interposers (TSIs)Joseph Romen Cubillo, Roshan Weerasekera, Zaw Zaw Oo, En-Xiao Liu, Bob Conn, Surya Bhattacharya, Robert Patti. 1-6 [doi]
- 3D interconnected technology by high speed copper electrodeposition using diallylamine levelersTaro Hayashi, Kazuo Kondo, Minoru Takeuchi, Yushi Suzuki, Takeyasu Saito, Naoki Okamoto, Masao Marunaka, Takayuki Tsuchiya, Masaru Bunya. 1-4 [doi]
- Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSIAkihiro Noriki, Kang-Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Fanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Vias-last process technology for thick 2.5D Si interposersErik Vick, Scott Goodwin, Garry Cunnigham, Dorota Temple. 1-4 [doi]
- A novel reconfigurable logic device base on 3D stack technologyQian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. 1-4 [doi]
- Low temperature Au-Au bonding with VUV/O3 treatmentAkiko Okada, Masatsugu Nimura, Naoko Unami, Akitsu Shigetou, Hirokazu Noma, Katsuyuki Sakuma, Jun Mizuno, Shuichi Shoji. 1-5 [doi]
- Void reduction in wafer bonding by simultaneously formed ventilation channelsMayu Aoki, Kazuyuki Hozawa, Kenichi Takeda. 1-5 [doi]
- HIBS - Novel inter-layer bus structure for stacked architecturesMasoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila. 1-7 [doi]
- Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yieldS. Mermoz, L. Sanchez, Léa Di Cioccio, J. Berthier, E. Deloffre, C. Fretigny. 1-5 [doi]
- Evolutional Directions of Smart Automotive Systems and SemiconductorsHideaki Ishihara. 1 [doi]
- Development of ultra-thinning technology for logic and memory heterogeneous stack applicationsN. Maeda, Y. S. Kim, Y. Hikosaka, T. Eshita, H. Kitada, K. Fujimoto, Y. Mizushima, K. Suzuki, Tadao Nakamura, A. Kawai, K. Arai, T. Ohba. 1-4 [doi]
- High frequency signal transmission characteristics of cone bump interconnectionsA. Ikeda, N. Watanabe, T. Asano. 1-5 [doi]
- TSV reveal etch for 3D integrationStephen Olson, Klaus Hummler. 1-4 [doi]
- Exploring AMBA AXI on-Chip interconnection for TSV-based 3D SoCsXiongfei Liao, Jun Zhou, Xin Liu. 1-4 [doi]
- In-tier diagnosis of power domains in 3D TSV ICsYuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne. 1-6 [doi]
- System level evaluation of Silicon imager based see-through Silicon applicationWei Zhou, Guest Max, Darcy Hart. 1-2 [doi]
- A built-in test circuit for open defects at interconnects between dies in 3D ICsWidianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume. 1-5 [doi]
- Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integrationSayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Yasumitsu Orii, Katsuyuki Sakuma, Takahiro Kinoshita, Takashi Kawakami. 1-7 [doi]
- Monolithic 3D-ICs with single crystal silicon layersDeepak C. Sekar, Zvi Or-Bach. 1-2 [doi]
- A low stress bond pad design optimization of low temperature solder interconnections on TSVs for MEMS applicationsXiaowu Zhang, Ranjan Rajoo, F. X. Che, C. S. Selvanayagam, W. K. Choi, Shan Gao, Guo-Qiang Lo, Dim-Lee Kwong. 1-5 [doi]
- A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectorsManuel Suarez, Victor M. Brea, F. Pardo, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez. 1-8 [doi]
- In-line metrology and inspection for process control during 3D stacking of IC'sSandip Halder, Ingrid De Wolf, Alain Phommahaxay, Andy Miller, Mireille Maenhoudt, Gerald Beyer, Bart Swinnen, Eric Beyne. 1-4 [doi]
- Low temperature through-Si via fabrication using electroless depositionFumihiro Inoue, Harold Philipsen, Alex Radisic, Silvia Armini, Peter Leunissen, Hiroshi Miyake, Ryohei Arima, Tomohiro Shimizu, Toshiaki Ito, Hirofumi Seki, Yuko Shinozaki, Tomohiko Yamamoto, Shoso Shingubara. 1-4 [doi]
- Characterization of local strain around trough silicon via interconnects in wafer-on-wafer structuresOsamu Nakatsuka, Hideki Kitada, Young-Suk Kim, Yoriko Mizushima, Tomoji Nakamura, Takayuki Ohba, Shigeaki Zaima. 1-4 [doi]
- ESD protection networks for 3D integrated circuitsElyse Rosenbaum, Vrashank Shukla, Min-Sun Keel. 1-7 [doi]
- Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologiesCheng-Ta Ko, Zhi-Cheng Hsiao, Y. J. Chang, P. S. Chen, J.-H. Huang, Hsin-Chia Fu, Y. J. Huang, C. W. Chiang, W. L. Tsat, Y. H. Chen, Wei-Chung Lo, Kuan-Neng Chen. 1-4 [doi]
- Stacked SOI pixel detector using versatile fine pitch μ-bump technologyMakoto Motoyoshi, Junichi Takanohashi, Takafumi Fukushima, Yasuo Arai, Mitsumasa Koyanagi. 1-4 [doi]
- A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliersJubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto. 1-6 [doi]
- Effect of frequency in the 3D integration of a PZT-actuated MEMS switch using a single crystal silicon asymmetric beamFumihiko Nakazawa, Takeaki Shimanouchi, Tadashi Nakatani, Takashi Katsuki, Hisao Okuda, Osamu Toyoda, Satoshi Ueda. 1-5 [doi]
- PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor systemKatsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka. 1-4 [doi]
- Mechanical reliability of Cu/low-k interconnects and underfillTaeshik Yoon, Inhwa Lee, Taek-Soo Kim. 1-4 [doi]
- Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integrationYuki Ohara, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- High-bandwidth data transmission of new transceiver module through optical interconnectionYuka Ito, Shinsuke Terada, Shinya Arai, Koji Choki, Takafumi Fukushima, Mitsumasa Koyanagi. 1-4 [doi]
- Mechanical characterization of residual stress around TSV through instrumented indentation algorithmGyujei Lee, Suk-woo Jeon, Kwang-yoo Byun, Dongil Kwon. 1-6 [doi]
- 3D-Scalable Adaptive Scan (3D-SAS)Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur. 1-6 [doi]
- Performance evaluation of 3D stacked multi-core processors with temperature considerationTakaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki Murakami. 1-5 [doi]
- Silicon interposer request-for-quote IC-package Co-design flowThomas Whipple, Thad McCracken. 1-7 [doi]
- Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnectsTomoji Nakamura, Hideki Kitada, Yoriko Mizushima, Nobuhide Maeda, Koji Fujimoto, Takayuki Ohba. 1-4 [doi]
- Development of pixel detectors for particle physics using SLID-ICV interconnection technologyHans-Günther Moser, Ladislav Andricek, Michael Beimforde, G. Liemann, Anna Macchiolo, Richard Nisius, Rainer Helmut Richter, Philipp Weigell. 1-4 [doi]
- Low-temperature bottom-up integration of carbon nanotubes for vertical interconnects in monolithic 3D integrated circuitsSten Vollebregt, Ryoichi Ishihara, Johan van der Cingel, Kees Beenakker. 1-4 [doi]
- Modeling and compare of through-silicon-via (TSV) in high frequencyRan Wang, Gary Charles, Paul D. Franzon. 1-6 [doi]
- Development of high accuracy wafer thinning and pickup technology for thin waferKosuke Kitaichi, Haruo Shimamoto, Chuichi Miyazaki, Yoshiyuki Abe, Sigeaki Saito, Shoji Yasunaga. 1-5 [doi]
- Damage evaluation of wet-chemical silicon-wafer thinning processNaoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa. 1-4 [doi]
- Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technologyHong-Yeol Lim, Gi-Ho Park. 1-5 [doi]
- Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directionsEric Beyne. 1-6 [doi]
- TSV process solution for 3D-ICS. Toyoda, A. Shibata, M. Harada, T. Murayama, T. Sakuishi, M. Hatanaka, Y. Morikawa, K. Suu. 1-5 [doi]
- Cu-based bonding technology for 3D integration applicationsKuan-Neng Chen, Z. Xu, F. Liu, Cheng-Ta Ko, Chuan-An Cheng, W. C. Huang, H.-L. Lin, C. Cabral, Zhi-Cheng Hsiao, N. Klymko, Hsin-Chia Fu, Y. H. Chen, Jian-Qiang Lu, Wei-Chung Lo. 1-4 [doi]
- Advances of 3M™ wafer support systemKazuta Saito, Richard J. Webb, Blake R. Dronen. 1-4 [doi]
- PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structureYoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda. 1-2 [doi]
- Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DICMyat Thu Linn Aung, Eric Lim, Takefumi Yoshikawa, Tony T. Kim. 1-4 [doi]
- Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integrationTakanori Shuto, Naoya Watanabe, Akihiro Ikeda, Tanemasa Asano. 1-4 [doi]
- Evaluation of wafer level Cu bonding for 3D integrationSung-Geun Kang, Youngrae Kim, Eun-Sol Kim, Naeun Lim, Teakgyu Jeong, Jieun Lee, Sarah Eunkyung Kim, Sungdong Kim. 1-2 [doi]