Table of Contents

• An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of InterconnectJing-Rebecca Li, Frank Wang, Jacob White. 1-6 [doi]
• Error Bounded Padé Approximation via Bilinear Conformal TransformationChung-Ping Chen, D. F. Wong. 7-12 [doi]
• Model-Reduction of Nonlinear Circuits Using Krylov-Space TechniquesPavan K. Gunupudi, Michel S. Nakhla. 13-16 [doi]
• Why is ATPG Easy?Mukul R. Prasad, Philip Chong, Kurt Keutzer. 22-28 [doi]
• Using Lower Bounds During Dynamic BDD MinimizationRolf Drechsler, Wolfgang Günther. 29-32 [doi]
• Optimization-Intensive Watermarking Techniques for Decision ProblemsGang Qu, Jennifer L. Wong, Miodrag Potkonjak. 33-36 [doi]
• Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio ProblemsAli Dasdan, Sandy Irani, Rajesh K. Gupta. 37-42 [doi]
• IP-based Design MethodologyDaniel Gajski. 43 [doi]
• ipChinook: an Integrated IP-based Design Framework for Distributed Embedded SystemsPai H. Chou, Ross B. Ortega, Ken Hines, Kurt Partridge, Gaetano Borriello. 44-49 [doi]
• Common-Case Computation: A High-Level Technique for Power and Performance OptimizationGanesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey. 56-61 [doi]
• Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based DesignsChing-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang. 62-67 [doi]
• Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven ApplicationsChing-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone. 68-71 [doi]
• Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply VoltagesVijay Sundararajan, Keshab K. Parhi. 72-75 [doi]
• HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the NightRaul Camposano, Kurt Keutzer, Jerry Fiddler, Alberto L. Sangiovanni-Vincentelli, Jim Lansford. 76-77 [doi]
• Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear ProgrammingsXiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan. 78-83 [doi]
• FAR-DS: Full-Plane AWE Routing with Driver SizingJiang Hu, Sachin S. Sapatnekar. 84-89 [doi]
• Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian RelaxationIris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang. 90-95 [doi]
• Simultaneous Routing and Buffer Insertion with Restrictions on Buffer LocationsHai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz. 96-99 [doi]
• Crosstalk Minimization Using Wire PerturbationsPrashant Saxena, C. L. Liu. 100-103 [doi]
• Practical Advances in Asynchronous Design and in Asynchronous/Synchronous InterfacesErik Brunvand, Steven M. Nowick, Kenneth Y. Yun. 104-109 [doi]
• Automatic Synthesis and Optimization of Partially Specified Asynchronous SystemsAlex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev. 110-115 [doi]
• CAD Directions for High Performance Asynchronous CircuitsKen S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken. 116-121 [doi]
• A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded SystemsJörg Henkel. 122-127 [doi]
• Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide BusesLuca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi. 128-133 [doi]
• Power Conscious Fixed Priority Scheduling for Hard Real-Time SystemsYoungsoo Shin, Kiyoung Choi. 134-139 [doi]
• Memory Exploration for Low Power, Embedded SystemsWen-Tsong Shiue, Chaitali Chakrabarti. 140-145 [doi]
• Distributed Application Development with InfernoRavi Sharma. 146-150 [doi]
• Embedded Application Design Using a Real-Time OSDavid Stepner, Nagarajan Rajan, David Hui. 151-156 [doi]
• The Jini Architecture: Dynamic Services in a Flexible NetworkKen Arnold. 157-162 [doi]
• Verifying Large-Scale Multiprocessors Using an Abstract Verification EnvironmentDennis Abts, Mike Roberts. 163-168 [doi]
• Functional Verification of the Equator MAP1000 MicroprocessorJian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-Chau Chu, Guanghui Hu. 169-174 [doi]
• Micro Architecture Coverage Directed Generation of Test ProgramsShmuel Ur, Yaov Yadin. 175-180 [doi]
• Verification of a Microprocessor Using Real World ApplicationsYou-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung. 181-184 [doi]
• High-Level Test Generation for Design Verification of Pipelined MicroprocessorsDavid Van Campenhout, Trevor N. Mudge, John P. Hayes. 185-188 [doi]
• Developing an Architecture Validation Suite: Applicaiton to the PowerPC ArchitectureLaurent Fournier, Anatoly Koyfman, Moshe Levinger. 189-194 [doi]
• Passive Reduced-Order Models for Interconnect Simulation and Their Computation via Krylov-Subspace AlgorithmsRoland W. Freund. 195-200 [doi]
• Model Order-Reduction of RC(L) Interconnect Including Variational AnalysisYing Liu, Lawrence T. Pileggi, Andrzej J. Strojwas. 201-206 [doi]
• Robust Rational Function Approximation Algorithm for Model GenerationCarlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira. 207-212 [doi]
• Behavioral Network Graph: Unifying the Domains of High-Level and Logic SynthesisReinaldo A. Bergamaschi. 213-218 [doi]
• Soft Scheduling in High Level SynthesisJianwen Zhu, Daniel Gajski. 219-224 [doi]
• Graph Coloring Algorithms for Fast Evaluation of Curtis DecompositionsMarek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko. 225-230 [doi]
• Maximizing Performance by Retiming and Clock Skew SchedulingXun Liu, Marios C. Papaefthymiou, Eby G. Friedman. 231-236 [doi]
• A Practical Approach to Multiple-Class RetimingKlaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl. 237-242 [doi]
• Performance-Driven Integration of Retiming and ResynthesisPeichen Pan. 243-246 [doi]
• Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction AlgorithmsLuca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino. 247-252 [doi]
• Functional Verification - Real Users, Real Problems, Real Opportunities (Panel)Jonah McLeod, Nozar Azarakhsh, Glen Ewing, Paul Gingras, Scott Reedstrom, Chris Rowen. 260-261 [doi]
• A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip FloorplanningHsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin. 262-267 [doi]
• An O-Tree Representation of Non-Slicing Floorplan and Its ApplicationsPei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura. 268-273 [doi]
• Module Placement for Analog Layout Using the Sequence-Pair RepresentationFlorin Balasa, Koen Lampaert. 274-279 [doi]
• Genetic List Scheduling Algorithm for Scheduling and Allocation on a Loosely Coupled Heterogeneous Multiprocessor SystemMartin Grajcar. 280-285 [doi]
• Performance-Driven Scheduling with Bit-Level ChainingSanghun Park, Kiyoung Choi. 286-291 [doi]
• A Model for Scheduling Protocol-Constrained Components and EnvironmentsSteve Haynal, Forrest Brewer. 292-295 [doi]
• A Reordering Technique for Efficient Code MotionLuiz C. V. dos Santos, Jochen A. G. Jess. 296-299 [doi]
• Coverage Estimation for Symbolic Model CheckingYatin Vasant Hoskote, Timothy Kam, Pei-Hsin Ho, Xudong Zhao. 300-305 [doi]
• Improving Symbolic Traversals by Means of Activity ProfilesGianpiero Cabodi, Paolo Camurati, Stefano Quer. 306-311 [doi]
• Improved Approximate Reachability Using Auxiliary State VariablesShankar G. Govindaraju, David L. Dill, Jules P. Bergmann. 312-316 [doi]
• Symbolic Model Checking Using SAT Procedures instead of BDDsArmin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro Fujita, Yunshan Zhu. 317-320 [doi]
• Power Efficient Mediaprocessors: Design Space ExplorationJohnson Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak. 321-326 [doi]
• Global Multimedia System Design Exploration Using Accurate Memory Organization FeedbackArnout Vandecappelle, Miguel Miranda, Erik Brockmeyer, Francky Catthoor, Diederik Verkest. 327-332 [doi]
• Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression SystemLode Nachtergaele, Bart Vanhoof, Mercedes Peón, Gauthier Lafruit, Jan Bormans, Ivo Bolsens. 333-336 [doi]
• A 10 Mbit/s Upstream Cable Modem with Automatic equalizationPatrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels. 337-340 [doi]
• Panel: Cell Libraries - Build vs. Buy; Static vs. DynamicKurt Keutzer, Kurt Wolf, David Pietromonaco, Jay Maxey, Jeff Lewis, Martin Lefebvre, Jeff Burns. 341-342 [doi]
• Multilevel ::::k::::-way Hypergraph PartitioningGeorge Karypis, Vipin Kumar. 343-348 [doi]
• Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and ReportingAndrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov. 349-354 [doi]
• Hypergraph Partitioning with Fixed VerticesAndrew E. Caldwell, Andrew B. Kahng, Igor L. Markov. 355-359 [doi]
• Relaxation and Clustering in a Local Search Framework: Application to Linear PlacementSung-Woo Hur, John Lillis. 360-366 [doi]
• An Approxmimate Algorithm for Delay-Constraint Technology MappingSumit Roy, Krishna P. Belkhale, Prithviraj Banerjee. 367-372 [doi]
• Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast InterconnectionsJason Cong, Yean-Yow Hwang, Songjie Xu. 373-378 [doi]
• Automated Phase Assignment for the Synthesis of Low Power Domino CircuitsPriyadarshan Patra, Unni Narayanan. 379-384 [doi]
• Enhancing Simulation with BDDs and ATPGMalay K. Ganai, Adnan Aziz, Andreas Kuehlmann. 385-390 [doi]
• Cycle-Based Symbolic Simulation of Gate-Level Synchronous CircuitsValeria Bertacco, Maurizio Damiani, Stefano Quer. 391-396 [doi]
• Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined MicroprocessorsMiroslav N. Velev, Randal E. Bryant. 397-401 [doi]
• Parametric Representations of Boolean ConstraintsMark Aagaard, Robert B. Jones, Carl-Johan H. Seger. 402-407 [doi]
• Vertical Benchmarks for CADChristopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass. 408-413 [doi]
• A Framework for User Assisted Design Space ExplorationXiaobo Hu, Garrison W. Greenwood, S. Ravichandran, Gang Quan. 414-419 [doi]
• Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor DesignBenoit Clement, Richard Hersemeule, Etienne Lantreibecq, Bernard Ramanadin, Pierre Coulomb, François Pogodalla. 420-424 [doi]
• Verification and Management of a Multimillion-Gate Embedded Core DesignJohann Notbauer, Thomas W. Albrecht, Georg Niedrist, Stefan Rohringer. 425-428 [doi]
• Parasitic Extraction Accuracy - How Much is Enough?Paul D. Franzon, Mark Basel, Aki Fujimara, Sharad Mehrotra, Ron Preston, Robin C. Sarma, Marty Walker. 429 [doi]
• Mixed-::::V::th:::::: (MVT) CMOS Circuit Design Methodology for Low Power ApplicationsLiqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De. 430-435 [doi]
• Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit SizingSupamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw. 436-441 [doi]
• Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOSMark C. Johnson, Dinesh Somasekhar, Kaushik Roy. 442-445 [doi]
• A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power DesignMasanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru. 446-451 [doi]
• Gradient-Based Optimization of Custom Circuits Using a Static-Timing FormulationAndrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan. 452-459 [doi]
• Simultaneous Circuit Partitioning/Clustering with Retiming for Performance OptimizationJason Cong, Honching Li, Chang Wu. 460-465 [doi]
• Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout TechniqueArindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long. 466-471 [doi]
• MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood SearchAmir H. Salek, Jinan Lou, Massoud Pedram. 472-478 [doi]
• Buffer Insertion with Accurate Gate and Interconnect Delay ComputationCharles J. Alpert, Anirudh Devgan, Stephen T. Quay. 479-484 [doi]
• Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath DesignJoon-Seo Yim, Chong-Min Kyung. 485-490 [doi]
• A Novel VLSI Layout Fabric for Deep Sub-Micron ApplicationsSunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli. 491-496 [doi]
• Improved Selay Prediction for On-Chip BusesReal G. Pomerleau, Paul D. Frazon, Griff L. Bilbro. 497-501 [doi]
• Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-MatchingChung-Ping Chen, Noel Menezes. 502-506 [doi]
• Interconnect Estimation and Dlanning for Deep Submicron DesignsJason Cong, David Zhigang Pan. 507-510 [doi]
• ECL: A Specification Environment for System-Level DesignLuciano Lavagno, Ellen Sentovich. 511-516 [doi]
• Representation of Function Variants for Embedded System Optimization and SynthesisKai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich. 517-522 [doi]
• Vex - A CAD ToolboxJules P. Bergmann, Mark Horowitz. 523-528 [doi]
• Constraint Management for Collaborative Electronic DesignJuan Antonio Carballo, Stephen W. Director. 529-534 [doi]
• MEMS CAD Beyond Multi-Million Transistors (Panel)Kristofer S. J. Pister, Albert P. Pisano, Nicholas Swart, Mike Horton, John Rychcik, John R. Gilbert, Gerry K. Fedder. 535-536 [doi]
• A Multiscale Method for Fast Capacitance ExtractionJohannes Tausch, Jacob K. White. 537-542 [doi]
• Efficient Capacitance Computation for Structures with Non-Uniform Adaptive Surface MeshesVikram Jandhyala, Scott Savage, J. Eric Bracken, Zoltan J. Cendes. 543-548 [doi]
• Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit SimulationTong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang. 549-554 [doi]
• Dynamic Power Management Based on Continuous-Time Markov Decision ProcessesQinru Qiu, Massoud Pedram. 555-561 [doi]
• Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit PartitioningMauro Chinosi, Roberto Zafalon, Carlo Guardiani. 562-567 [doi]
• Low-Power Behavioral Synthesis Optimization Using Multiple Precision ArithmeticMilos D. Ercegovac, Darko Kirovski, Miodrag Potkonjak. 568-573 [doi]
• A Methodology for the Verification of a System on Chip Daniel Geist, Giora Biran, Tamarah Arons, Michael Slavkin, Yvgeny Nustov, Monica Farkas, Karen Holtz, Andy Long, Dave King, Steve Barret. 574-579 [doi]
• ICEBERG: An Embedded In-Circuit Emulator Synthesizer for MicrocontrollersIng-Jer Huang, Tai-An Lu. 580-585 [doi]
• Microprocessor Based Testing for Core-Based System on ChipChristos A. Papachristou, F. Martin, Mehrdad Nourani. 586-591 [doi]
• Using Partitioning to Help Convergence in the Standard-Cell Design Automation MethodologyHema Kapadia, Mark Horowitz. 592-597 [doi]
• Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM ShaperImed Moussa, Zoltan Sugar, Rodolph Suescun, Mario Diaz-Nava, Marco Pavesi, Salvatore Crudo, Luca Gazi, Ahmed Amine Jerraya. 598-603 [doi]
• Engineering Change: Methodology and Applications to Behavioral and System SynthesisDarko Kirovski, Miodrag Potkonjak. 604-609 [doi]
• Reconfigurable Computing: What, Why, and Implications for Design AutomationAndré DeHon, John Wawrzynek. 610-615 [doi]
• An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP ApplicationsMeenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss. 616-622 [doi]
• Multi-Time Simulation of Voltage-Controlled OscillatorsOnuttom Narayan, Jaijeet S. Roychowdhury. 629-634 [doi]
• Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time ApproachDan Feng, Joel R. Phillips, Keith Nabors, Kenneth S. Kundert, Jacob White. 635-640 [doi]
• Time-Mapped Harmonic BalanceOgnen J. Nastov, Jacob White. 641-646 [doi]
• Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test CompactionRuifeng Guo, Sudhakar M. Reddy, Irith Pomeranz. 653-659 [doi]
• Multiple Error Diagnosis Based on XlistsVamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni. 660-665 [doi]
• Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement CoverageFarzan Fallah, Pranav Ashar, Srinivas Devadas. 666-671 [doi]
• A Two-State Methodology for RTL Logic SimulationLionel Bening. 672-677 [doi]
• An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL SpecificationsCordula Hansen, Francisco Nascimento, Wolfgang Rosenstiel. 678-683 [doi]
• A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable HardwareMiron Abramovici, José T. de Sousa, Daniel G. Saab. 684-690 [doi]
• Dynamic Fault Diagnosis on Reconfigurable HardwareFatih Kocan, Daniel G. Saab. 691-696 [doi]
• Hardware Compilation for FPGA-Based Configurable Computing MachinesXiaohan Zhu, Bill Lin. 697-702 [doi]
• SOI Digital CMOS VLSI - a Design PerspectiveChing-Te Chuang, Ruchir Puri. 709-714 [doi]
• Equivalent Elmore Delay for ::::RLC:::: Trees715-720 [doi]
• Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI CircuitsYehea I. Ismail, Eby G. Friedman. 721-724 [doi]
• Retiming for DSM with Area-Delay Trade-Offs and Delay ConstraintsAbdallah Tabbara, Robert K. Brayton, A. Richard Newton. 725-730 [doi]
• Functional Timing Analysis for IP CharacterizationHakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah. 731-736 [doi]
• Detecting False Timing Paths: Experiments on PowerPC MicroprocessorsRichard Raimi, Jacob A. Abraham. 737-741 [doi]
• On ILP Formulations for Built-In Self-Testable Data Path SynthesisHan Bin Kim, Dong Sam Ha, Takeshi Takahashi. 742-747 [doi]
• Improving the Test Quality for Scan-Based BIST Using a General Test Application SchemeHuan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik. 748-753 [doi]
• Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test SubsequencesIrith Pomeranz, Sudhakar M. Reddy. 754-759 [doi]
• Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron DevicesYi-Min Jiang, Kwang-Ting Cheng. 760-765 [doi]
• A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICsJoon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung. 766-771 [doi]
• Digital Aetection of Analog Parametric Faults in SC FiltersRamesh Harjani, Bapiraju Vinnakota. 772-777 [doi]
• Application of High Level Interface-Based Design to Telecommunications System HardwareDyson Wilkes, M. M. Kamal Hashmi. 778-783 [doi]
• Hardware Reuse at the Behavioral LevelPatrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels, Ivo Bolsens. 784-789 [doi]
• Description and Simulation of Hardware/Software Systems with JavaTommy Kuhn, Wolfgang Rosenstiel, Udo Kebschull. 790-793 [doi]
• Java Driven Codesign and Prototyping of Networked Embedded SystemsJosef Fleischmann, Klaus Buchenrieder, Rainer Kress. 794-797 [doi]
• Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel)Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser. 798 [doi]
• Subwavelength Lithography and Its Potential Impact on Design and EDAAndrew B. Kahng, Y. C. Pati. 799-804 [doi]
• Synthesis of Embedded Software Using Free-Choice Petri NetsMarco Sgroi, Luciano Lavagno. 805-810 [doi]
• Exact Memory Size Estimation for Array Computations without Loop UnrollingYing Zhao, Sharad Malik. 811-816 [doi]
• Constraint Driven Code Selection for Fixed-Point DSPsSteven Bashford, Rainer Leupers. 817-822 [doi]
• Rapid Development of Optimized DSP Code from a High Level Description Through Software EstimationsAlain Pegatoquet, Emmanuel Gresset, Michel Auguin, Luc Bianco. 823-826 [doi]
• Software Environment for a Multiprocessor DSPAsawaree Kalavade, Joe Othmer, Bryan D. Ackland, Kanwar Jit Singh. 827-830 [doi]
• Robust FPGA Intellectual Property Protection Through Multiple Small WatermarksJohn Lach, William H. Mangione-Smith, Miodrag Potkonjak. 831-836 [doi]
• Robust Techniques for Watermarking Sequential Circuit DesignsArlindo L. Oliveira. 837-842 [doi]
• Effective Iterative Techniques for Fingerprinting Design IPAndrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong. 843-848 [doi]
• Behavioral Synthesis Techniques for Intellectual Property ProtectionInki Hong, Miodrag Potkonjak. 849-854 [doi]
• Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC ConverterJames Goodman, Anantha Chandrakasan, Abram P. Dancy. 855-860 [doi]
• Design Considerations for Battery-Powered ElectronicsMassoud Pedram, Qing Wu. 861-866 [doi]
• Cycle-Accurate Simulation of Energy Consumption in Embedded SystemsTajana Simunic, Luca Benini, Giovanni De Micheli. 867-872 [doi]
• Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design StyleAhmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist. 873-878 [doi]
• A CAD Tool for Optical MEMSTimothy P. Kurzweg, Steven P. Levitan, Philippe J. Marchand, Jose A. Martinez, Kurt R. Prough, Donald M. Chiarulli. 879-884 [doi]
• On Thermal Effects in Deep Sub-Micron VLSI InterconnectsKaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu. 885-891 [doi]
• Converting a 64b PowerPC Processor from CMOS Bulk to SOI TechnologyD. Allen, D. Behrends, B. Stanisic. 892-897 [doi]
• A Framework for Collaborative and Distributed Web-Based DesignGangadhar Konduri, Anantha Chandrakasan. 898-903 [doi]
• Dealing with Inductance in High-Speed Chip DesignPhillip Restle, Albert E. Ruehli, Steven G. Walker. 904-909 [doi]
• Interconnect Analysis: From 3-D Structures to Circuit ModelsMattan Kamon, Nuno Alexandre Marques, Yehia Massoud, Luis Miguel Silveira, Jacob White. 910-914 [doi]
• IC Analyses Including Extracted Inductance ModelsMichael W. Beattie, Lawrence T. Pileggi. 915-920 [doi]
• On-Chip Inductance Issues in Multiconductor SystemsShannon V. Morton. 921-926 [doi]
• A Methodology for Accurate Performance Evaluation in Architecture ExplorationGeorge Hadjiyiannis, Pietro Russo, Srinivas Devadas. 927-932 [doi]
• LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP ArchitecturesStefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr. 933-938 [doi]
• MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog CellsMichael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley. 945-950 [doi]
• Behavioral Synthesis of Analog Systems Using Two-layered Design Space ExplorationAlex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri. 951-957 [doi]
• Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated CircuitsWalter Daems, Georges G. E. Gielen, Willy M. C. Sansen. 958-963 [doi]
• Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-VerificationLisa M. Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schläger, Bassam Tabbara, Vojin Zivojnovic. 964-969 [doi]
• A Study in Coverage-Driven Test GenerationMike Benjamin, Daniel Geist, Alan Hartman, Gérard Mas, Ralph Smeets, Yaron Wolfsthal. 970-975 [doi]
• IC Test Using the Energy Consumption RatioWanli Jiang, Bapiraju Vinnakota. 976-981 [doi]
• Design Strategy of On-Chip Inductors for Highly Integrated RF SystemsC. Patrick Yue, S. Simon Wong. 982-987 [doi]
• Optimization of Inductor Circuits via Geometric ProgrammingMaria del Mar Hershenson, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee. 994-998 [doi]
• Panel: What is the Proper System on Chip Design MethodologyRichard Goering, Pierre Bricaud, James G. Dougherty, Steve Glaser, Michael Keating, Robert Payne, Davoud Samani. 999 [doi]