Matthias Sauer - researchr alias

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Viewing Publication 1 - 64 from 64

2017

Specification and verification of security in reconfigurable scan networksMichael A. Kochte, Matthias Sauer, Laura Rodríguez Gómez, Pascal Raiola, Bernd Becker 0001, Hans-Joachim Wunderlich. ets 2017: 1-6 [doi]

Sensitized path PUF: A lightweight embedded physical unclonable functionMatthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker 0001, Ulrich Rührmair, Ilia Polian. date 2017: 680-685 [doi]

2016

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknownsDominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. aspdac 2016: 749-754 [doi]

On Metrics to Quantify the Inter-Device Uniqueness of PUFsLinus Feiten, Matthias Sauer, Bernd Becker. iacr, 2016:320, 2016. [doi]

Extracting the RC4 secret key of the Open Smart Grid ProtocolLinus Feiten, Matthias Sauer. iacr, 2016:455, 2016. [doi]

Systemic Frequency Biases in Ring Oscillator PUFs on FPGAsLinus Feiten, Jonathan Oesterle, Tobias Martin, Matthias Sauer, Bernd Becker. tmscs, 2(3):174-185, 2016. [doi]

Formal verification of secure reconfigurable scan network infrastructureMichael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich. ets 2016: 1-6 [doi]

Effective generation and evaluation of diagnostic SBST programsAndreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker. vts 2016: 1-6 [doi]

A Flexible Framework for the Automatic Generation of SBST ProgramsAndreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker. tvlsi, 24(10):3055-3066, 2016. [doi]

On Optimal Power-Aware Path SensitizationMatthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian. ats 2016: 179-184 [doi]

PHAETON: A SAT-Based Framework for Timing-Aware Path SensitizationMatthias Sauer, Bernd Becker, Ilia Polian. TC, 65(6):1869-1881, 2016. [doi]

SAT-Based Combinational and Sequential Dependency ComputationMathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer. hvc 2016: 1-17 [doi]

2015

Modeling Unknown Values in Test and VerificationBernd Becker, Matthias Sauer, Christoph Scholl, Ralf Wimmer. syde 2015: 122-150 [doi]

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defectsDominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker. vts 2015: 1-6 [doi]

Accurate QBF-Based Test Pattern Generation in Presence of Unknown ValuesDominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. tcad, 34(12):2025-2038, 2015. [doi]

Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biasesLinus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker. ets 2015: 1-6 [doi]

Formal Vulnerability Analysis of Security ComponentsLinus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker. tcad, 34(8):1358-1369, 2015. [doi]

Solving DQBF through quantifier eliminationKarina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker. date 2015: 1617-1622 [doi]

Identification of high power consuming areas with gate type and logic level informationKohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara. ets 2015: 1-6 [doi]

Improving diagnosis resolution of a fault detection test setAndreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker. vts 2015: 1-6 [doi]

On the automatic generation of SBST test programs for in-field testAndreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker. date 2015: 1186-1191 [doi]

2014

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimizationBernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer. dtis 2014: 1-10 [doi]

Efficient SMT-based ATPG for interconnect open defectsDominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker. date 2014: 1-6 [doi]

Circuit Parameter Independent Test Pattern Generation for Interconnect Open DefectsDominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker. ats 2014: 131-136 [doi]

Test pattern generation in presence of unknown values based on restricted symbolic logicDominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. itc 2014: 1-10 [doi]

Exact Logic and Fault Simulation in Presence of UnknownsDominik Erb, Michael A. Kochte, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker. todaes, 19(3):28, 2014. [doi]

Using MaxBMC for Pareto-optimal circuit initializationSven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker. date 2014: 1-6 [doi]

Incremental Encoding and Solving of Cardinality ConstraintsSven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker. ATVA 2014: 297-313 [doi]

QBF with Soft VariablesSven Reimer, Matthias Sauer, Paolo Marin, Bernd Becker. eceasst, 70, 2014. [doi]

An effective approach to automatic functional processor test generation for small-delay faultsAndreas Riefert, Lyl M. Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker. date 2014: 1-6 [doi]

Testing time - time to test?: using formal methods for the timing analysis of digital circuitsMatthias Sauer. PhD thesis, University of Freiburg, Freiburg im Breisgau, Germany, 2014. [doi]

Efficient SAT-Based Circuit Initialization for Larger DesignsMatthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker. vlsid 2014: 62-67 [doi]

Variation-aware deterministic ATPGMatthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker. ets 2014: 1-6 [doi]

2013

Accurate Computation of Sensitizable Paths Using Answer Set ProgrammingBenjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub. lpnmr 2013: 92-101 [doi]

Accurate Multi-cycle ATPG in Presence of X-ValuesDominik Erb, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. ats 2013: 245-250 [doi]

Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAsLinus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker. isjgp, 22(5-6):265-273, 2013. [doi]

Equivalence checking of partial designs using dependency quantified Boolean formulaeKarina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker. iccd 2013: 396-403 [doi]

Equivalence Checking for Partial Implementations RevisitedKarina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker. mbmv 2013: 61-70

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectricsYoung Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra. cicc 2013: 1-4 [doi]

Search Space Reduction for Low-Power Test GenerationKohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara. ats 2013: 171-176 [doi]

Identification of critical variables using an FPGA-based fault injection frameworkAndreas Riefert, Jörg Müller 0004, Matthias Sauer, Wolfram Burgard, Bernd Becker. vts 2013: 1-6 [doi]

Provably optimal test cube generation using quantified boolean formula solvingMatthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker. aspdac 2013: 533-539 [doi]

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable pathsMatthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker. date 2013: 448-453 [doi]

SAT-Based Analysis of Sensitizable PathsMatthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker. dt, 30(4):81-88, 2013. [doi]

Early-life-failure detection using SAT-based ATPGMatthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker. itc 2013: 1-10 [doi]

2012

Multi-conditional SAT-ATPG for power-droop testingAlexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker. ets 2012: 1-6 [doi]

Variation-Aware Fault GradingAlexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich. ats 2012: 344-349 [doi]

SAT-ATPG using preferences for improved detection of complex defect mechanismsAlexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker. vts 2012: 170-175 [doi]

#SAT-based vulnerability analysis of security components - A case studyLinus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker. dft 2012: 49-54 [doi]

On the optimality of K longest path generation algorithm under memory constraintsJie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian. date 2012: 418-423 [doi]

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig InterpolationMatthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker. vlsid 2012: 382-387 [doi]

Functional test of small-delay faults using SAT and Craig interpolationMatthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker. itc 2012: 1-8 [doi]

On the quality of test vectors for post-silicon characterizationMatthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian. ets 2012: 1-6 [doi]

Small-delay-fault ATPG with waveform accuracyMatthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker. iccad 2012: 30-36 [doi]

2011

1995

Error Analysis of CORDIC-Based Jacobi AlgorithmsSteffen Paul, Jürgen Götze, Matthias Sauer. TC, 44(7):947-951, 1995.

Algorithmustransformationen beim Entwurf anwendungsspezifischer integrierter SchaltungenMatthias Sauer. PhD thesis, Technical University Munich, Germany, 1995. [doi]

1994

Fault Location in Multistage Interconnection Networks with Global and Distributed ControlErnst G. Bernard, Matthias Sauer, Josef A. Nossek. ipps 1994: 830-834

A New Retiming Algorithm for Circuit DesignSven Simon, Ernst G. Bernard, Matthias Sauer, Josef A. Nossek. iscas 1994: 35-38

1993

An Efficient Jacobi-like Algorithm for Parallel Eigenvalue ComputationJürgen Götze, Steffen Paul, Matthias Sauer. TC, 42(9):1058-1065, 1993.

Block Sequential CORDIC ArchitecturesMatthias Sauer, Ernst G. Bernard, Josef A. Nossek. iscas 1993: 1591-1594

1991

Sorting on defective VLSI-arraysJosef G. Krammer, Ernst G. Bernard, Matthias Sauer, Josef A. Nossek. integration, 12(1):33-48, 1991. [doi]

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