Table of Contents

• MEMS for automotive and consumer electronicsJiri Marek. 9-17 [doi]
• Harnessing technology to advance the next-generation mobile user-experienceGreg Delagi. 18-24 [doi]
• Challenges of image-sensor developmentTomoyuki Suzuki 0002. 27-30 [doi]
• Nanoelectronics in retrospect, prospect and principleJames D. Meindl, Azad Naeemi, Muhannad S. Bakir, R. Murali. 31-35 [doi]
• A true time-delay-based bandpass multi-beam array at mm-waves supporting instantaneously wide bandwidthsTa-Shun Chu, Hossein Hashemi. 38-39 [doi]
• A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOSKuba Raczkowski, Walter De Raedt, Bart Nauwelaers, Piet Wambacq. 40-41 [doi]
• A 60GHz-band 2×2 phased-array transmitter in 65nm CMOSWei L. Chan, John R. Long, Marco Spirito, John J. Pekarik. 42-43 [doi]
• A 5.2-to-13GHz class-AB CMOS power amplifier with a 25.2dBm peak output power at 21.6% PAEHua Wang, Constantine Sideris, Ali Hajimiri. 44-45 [doi]
• A passive-mixer-first receiver with baseband-controlled RF impedance matching, ≪ 6dB NF, and ≫ 27dBm wideband IIP3Caroline Andrews, Alyosha C. Molnar. 46-47 [doi]
• 3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLLLuca Fanori, Antonio Liscidini, Rinaldo Castello. 48-49 [doi]
• Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz bandSalvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita. 50-51 [doi]
• A 9.2µA gen 2 compatible UHF RFID sensing tag with -12dBm Sensitivity and 1.25µVrms input-referred noise floorDaniel J. Yeager, Fan Zhang, Azin Zarrasvand, Brian P. Otis. 52-53 [doi]
• A quad-band class-39 RF CMOS receiver for evolved EDGEThomas Dellsperger, David Tschopp, Jürgen Rogin, Yangjian Chen, Thomas Burger, Qiuting Huang. 56-57 [doi]
• 2 all-digital SAW-less polar transmitter in 65nm EDGE SoCJaimin Mehta, Robert B. Staszewski, Oren Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John L. Wallberg, Patrick Cruise, Naveen K. Yanduru. 58-59 [doi]
• A tri-band SAW-less WCDMA/HSPA RF CMOS transceiver with on-chip DC-DC converter connectable to batteryQiuting Huang, Jürgen Rogin, Xinhua Chen, David Tschopp, Thomas Burger, Thomas Christen, Dimitris Papadopoulos, Ilian Kouchev, Chiara Martelli, Thomas Dellsperger. 60-61 [doi]
• A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-endXin He, Jan van Sinderen, Robert Rutten. 62-63 [doi]
• A 900MHz direct ΔΣ receiver in 65nm CMOSKimmo Koli, Jarkko Jussila, Pete Sivonen, Sami Kallioinen, Aarno Pärssinen. 64-65 [doi]
• A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearizationHiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe. 66-67 [doi]
• A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOSHyunwon Moon, Sangyoub Lee, Seung-Chan Heo, Hwayeal Yu, Jinhyuck Yu, Ji-Soo Chang, Seung-Il Choi, Byeong-ha Park. 68-69 [doi]
• A low-power low-noise direct-conversion front-end with digitally assisted IIP2 background self calibrationYiping Feng, Gaku Takemura, Shunji Kawaguchi, Nobuyuki Itoh, Peter R. Kinget. 70-71 [doi]
• A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°CMahdi Kashmiri, Michiel A. P. Pertijs, Kofi A. A. Makinwa. 74-75 [doi]
• A micropower chopper-correlated double-sampling amplifier with 2µV standard deviation offset and 37nV/√Hz input noise densityMassimiliano Belloni, Edoardo Bonizzoni, Andrea Fornasari, Franco Maloberti. 76-77 [doi]
• A single-trim CMOS bandgap reference with a 3σ inaccuracy of ±0.15% from -40°C to 125°CGuang Ge, Cheng Zhang, Gian Hoogzaad, Kofi A. A. Makinwa. 78-79 [doi]
• A 21nV/√Hz chopper-stabilized multipath current-feedback instrumentation amplifier with 2µV offsetQinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa. 80-81 [doi]
• A 10mW stereo audio CODEC in 0.13µm CMOSXicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu. 82-83 [doi]
• Class-G headphone driver in 65nm CMOS technologyAlex Lollio, Giacomino Bollati, Rinaldo Castello. 84-85 [doi]
• 45nm CMOS 8Ω Class-D audio driver with 79% efficiency and 100dB SNRSreekiran Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi. 86-87 [doi]
• A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOSChul Kim, Chang-Seok Chae, Young-sub Yuk, Yi-Gyeong Kim, Jong-Kee Kwon, Gyu-Hyeong Cho. 88-89 [doi]
• A 3.2GHz-sample-rate 800mHz bandwidth highly reconfigurable analog FIR filter in 45nm CMOSEoin O'hAnnaidh, Emmanuel Rouat, Sarah Verhaeren, Stéphane Le Tual, Christophe Garnier. 90-91 [doi]
• A 34dB SNDR instantaneously-companding baseband SC filter for 802.11a/g WLAN receiversVaibhav Maheshwari, Wouter A. Serdijn, John R. Long, John J. Pekarik. 92-93 [doi]
• Westmere: A family of 32nm IA processorsNasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Timothy M. Wilson, Mahadev Nemani, Muntaquim Chowdhury. 96-97 [doi]
• A 40nm 16-core 128-thread CMT SPARC SoC processorJinuk Luke Shin, Kenway Tam, Dawei Huang, Bruce Petrick, Ha Pham, Changku Hwang, Hongping Li, Alan Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong. 98-99 [doi]
• A 45nm 37.3GOPS/W heterogeneous multi-core SoCYoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, S. Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima. 100-101 [doi]
• TM: A highly parallel and scalable multi-core high-end server processorDieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, R. Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban. 102-103 [doi]
• TM processor: 2.3GHz 45nm SOI with 16 cores and 64 threadsCharles L. Johnson, David H. Allen, Jeffrey D. Brown, Steve Vanderwiel, Russ Hoover, Heather D. Achilles, Chen-Yong Cher, George A. May, Hubertus Franke, Jimi Xenidis, Claude Basso. 104-105 [doi]
• An x86-64 core implemented in 32nm SOI CMOSRavi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, A. Novak, Sam Naffziger. 106-107 [doi]
• A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOSJason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson. 108-109 [doi]
• A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOSMark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar. 110-111 [doi]
• A mobile-display-driver IC embedding a capacitive-touch-screen controller systemHyoung-rae Kim, Yoon Kyung Choi, San-Ho Byun, Sang-Woo Kim, Kwang-Ho Choi, Hae-Yong Ahn, Jong Kang Park, Dong-Yul Lee, Zhong-Yuan Wu, Hyung-Dal Kwon, Yong-Yeob Choi, Chang-ju Lee, Hwa-Hyun Cho, Jae-Suk Yu, Myunghee Lee. 114-115 [doi]
• A double-loop control LED backlight driver IC for medium-sized LCDsSeok-in Hong, Jin-Wook Han, Dong-Hee Kim, Oh-Kyong Kwon. 116-117 [doi]
• Stable RGBW AMOLED display with OLED degradation compensation using electrical feedbackG. Reza Chaji, Stefan Alexander, J. Marcel Dionne, Yaser Azizi, Corbin Church, John Hamer, Jeff Spindler, Arokia Nathan. 118-119 [doi]
• An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applicationsSeung-Bae Lee, Hyung-Min Lee, Mehdi Kiani, Uei-Ming Jow, Maysam Ghovanloo. 120-121 [doi]
• A 20µW neural recording tag with supply-current-modulated AFE in 0.13µm CMOSZhiming Xiao, Chun-ming Tang, Christopher M. Dougherty, Rizwan Bashirullah. 122-123 [doi]
• A 30µW Analog Signal Processor ASIC for biomedical signal monitoringRefet Firat Yazicioglu, Sunyoung Kim, Tom Torfs, Patrick Merken, Chris Van Hoof. 124-125 [doi]
• A 1V 22µW 32-channel implantable EEG recording ICXiaodan Zou, Wen-Sin Liew, Libin Yao, Yong Lian. 126-127 [doi]
• A timing controlled AC-DC converter for biomedical implantsK. F. E. Lee. 128-129 [doi]
• A CMOS electrochemical impedance spectroscopy biosensor array for label-free biomolecular detectionArun Manickam, Aaron Chevalier, Mark McDermott, Andrew D. Ellington, Arjang Hassibi. 130-131 [doi]
• A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glassWei Xiong, Ute Zschieschang, Hagen Klauk, Boris Murmann. 134-135 [doi]
• An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precisionHagen Marien, Michiel Steyaert, Nick A. J. M. van Aerle, Paul Heremans. 136-137 [doi]
• User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnectsKoichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai. 138-139 [doi]
• Robust digital design in organic electronics by dual-gate technologyKris Myny, Monique J. Beenhakkers, Nick A. J. M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans. 140-141 [doi]
• An integrated organic circuit array for flexible large-area temperature sensingDavid D. He, Ivan Nausieda, Kyungbum Kevin Ryu, Akintunde Ibitayo Akinwande, Vladimir Bulovic, Charles Sodini. 142-143 [doi]
• Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testingMutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai. 144-145 [doi]
• A wafer-level heterogeneous technology integration for flexible pseudo-SoCHiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki. 146-147 [doi]
• Design issues and considerations for low-cost 3D TSV IC technologyGeert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne. 148-149 [doi]
• Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applicationsFred Chen, Matthew Spencer, Rhesa Nathanael, Chengcheng Wang, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu-Jae King Liu, Dejan Markovic, Vladimir Stojanovic, Elad Alon. 150-151 [doi]
• Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyondAli Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam Shahidi. 152-153 [doi]
• A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOSFrank O'Mahony, Joseph T. Kennedy, James E. Jaussi, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper. 156-157 [doi]
• A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOSMasum Hossain, Anthony Chan Carusone. 158-159 [doi]
• A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOSRobert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz. 160-161 [doi]
• st-Tap FFE and 3-Tap DFE in 90nm CMOSHideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno. 162-163 [doi]
• A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalizationMassimo Pozzoni, Simone Erba, Davide Sanzogni, Marc Ganzerli, Paolo Viola, Daniele Baldi, Matteo Repossi, Giorgio Spelgatti, Francesco Svelto. 164-165 [doi]
• A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOSOleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto. 166-167 [doi]
• A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOSHisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh. 168-169 [doi]
• A 20Gb/s 40mW equalizer in 90nm CMOS technologySameh A. Ibrahim, Behzad Razavi. 170-171 [doi]
• Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processorSaurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar. 174-175 [doi]
• Low-skew clock distribution using zero-phase-clock-buffer DLLsTing Wu, Farshid Aryanfar, Hae-Chang Lee, Jie Shen, T. J. Chin, Carl Werner, Ken Chang. 176-177 [doi]
• TM local clocking and clocked storage elementsJames D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski. 178-179 [doi]
• A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processorCheolmin Park, Roy Badeau, Larry Biro, Jonathan Chang, Tejpal Singh, Jim Vash, Bo Wang, Tom Wang. 180-181 [doi]
• High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOSJae-sun Seo, Ron Ho, Jon K. Lexau, Michael Dayringer, Dennis Sylvester, David Blaauw. 182-183 [doi]
• A microcontroller-based PVT control system for a 65nm 72Mb synchronous SRAMSherif T. Eid, Morgan Whately, Sandeep Krishnegowda. 184-185 [doi]
• Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuitMesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy. 186-187 [doi]
• In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converterDavid Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik, Jae-sun Seo, Dennis Sylvester, David Blaauw. 188-189 [doi]
• Early detection of oxide breakdown through in situ degradation sensingPrashant Singh, Zhiyoong Foo, Michael Wieckowski, Scott Hanson, Matthew Fojtik, David Blaauw, Dennis Sylvester. 190-191 [doi]
• A precise-tracking NBTI-degradation monitor independent of NBTI recovery effectEisuke Saneyoshi, Koichi Nose, Masayuki Mizuno. 192-193 [doi]
• A two-phase switching hybrid supply modulator for polar transmitters with 9% efficiency improvementYing Wu, Philip K. T. Mok. 196-197 [doi]
• A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOSEric G. Soenen, Alan Roth, Justin Shi, Martin Kinyua, Justin Gaither, Elizabeth Ortynska. 198-199 [doi]
• A PLL-based high-stability single-inductor 6-channel output DC-DC buck converterKwang-Chan Lee, Chang-Seok Chae, Gyu-Ha Cho, Gyu-Hyeong Cho. 200-201 [doi]
• A 300mA 14mV-ripple digitally controlled buck converter using frequency domain ΔΣ ADC and hybrid PWM generatorHani H. Ahmad, Bertan Bakkaloglu. 202-203 [doi]
• A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis controlChen Zheng, Dongsheng Ma. 204-205 [doi]
• Digitally assisted discontinuous conduction mode 5V/100MHz and 10V/45MHz DC-DC boost converters with integrated Schottky diodes in standard 0.13µm CMOSPengfei Li, Lin Xue, Deepak Bhatia, Rizwan Bashirullah. 206-207 [doi]
• 2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOSYogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha Chandrakasan. 208-209 [doi]
• 2 at 81% efficiencyHanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon. 210-211 [doi]
• A 4-channel 4-beam 24-to-26GHz spatio-temporal RAKE radar transceiver in 90nm CMOS for vehicular radar applicationsHarish Krishnaswamy, Hossein Hashemi. 214-215 [doi]
• A fully integrated 77GHz FMCW radar system in 65nm CMOSYi-An Li, Meng-Hsiung Hung, Shih-Jou Huang, Jri Lee. 216-217 [doi]
• A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communicationsAlberto Valdes-Garcia, Sean Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Brian A. Floyd. 218-219 [doi]
• A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonatorsFederico Vecchi, Stefano Bozzola, Massimo Pozzoni, Davide Guermandi, Enrico Temporiti, Matteo Repossi, Ugo Decanis, Andrea Mazzanti, Francesco Svelto. 220-221 [doi]
• A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppressionXiongchuan Huang, Simonetta Rampu, Xiaoyan Wang, Guido Dolmans, Harmke de Groot. 222-223 [doi]
• A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodesSalvatore Drago, D. M. W. Leenaerts, Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Bram Nauta. 224-225 [doi]
• An Ultra-Low-Power interference-robust IR-UWB transceiver chipset using self-synchronizing OOK modulationMarco Crepaldi, Chen Li, Keith Dronson, Jorge R. Fernandes, Peter R. Kinget. 226-227 [doi]
• A fully integrated 802.15.4a IR-UWB Transceiver in 0.13µm CMOS with digital RRC synthesisSanghoon Joo, Wu-Hsin Chen, Tae Young Choi, Mi-Kyung Oh, Joo-Ho Park, Jae-Young Kim 0002, Byunghoo Jung. 228-229 [doi]
• A 0.92/5.3nJ/b UWB impulse radio SoC for communication and localizationYuanjin Zheng, Shengxi Diao, Chyuen-Wei Ang, Yuan Gao, Foo Chung Choong, Zhiming Chen, Xin Liu, Yisheng Wang, Xiaojun Yuan, Chun-Huat Heng. 230-231 [doi]
• Pain control on demand based on pulsed radio-frequency stimulation of the dorsal root ganglion using a batteryless implantable CMOS SoCChii-Wann Lin, Hung-Wei Chiu, Mu-Lien Lin, Chi-Heng Chang, I-Hsiu Ho, Po Hsiang Fang, Yi-Chin Li, Chang Lun Wang, Yao-Chuan Tsai, Yeong-Ray Wen, Win-Pin Shih, Yao-Joe Yang, Shey-Shi Lu. 234-235 [doi]
• Mixed-signal integrated circuits for self-contained sub-cubic millimeter biomedical implantsEric Y. Chow, Sudipto Chakraborty, William J. Chappell, Pedro Irazoqui. 236-237 [doi]
• An implantable 5mW/channel dual-wavelength optogenetic stimulator for therapeutic neuromodulation researchKunal Paralikar, Peng Cong, Wesley Santa, David Dinsmoor, Bob Hocken, Gordon Munns, Jon Giftakis, Timothy Denison. 238-239 [doi]
• Compact voltage and current stimulation buffer for high-density microelectrode arraysPaolo Livi, Flavio Heer, Urs Frey, Douglas J. Bakkum, Andreas Hierlemann. 240-241 [doi]
• A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillatorMichael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp. 244-245 [doi]
• A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/ODennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang. 246-247 [doi]
• 2 90-to-770MHz fractional-N Synthesizer for a digital TV tunerM. Kondou, A. Matsuda, H. Yamazaki, O. Kobayashi. 248-249 [doi]
• A low-noise frequency synthesizer for infrastructure applicationsShayan Farahvash, William Roberts, Jake Easter, Rachel Wei, David Stegmeir, Li Jin. 250-251 [doi]
• A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applicationsOlivier Richard, Alexandre Siligaris, Franck Badets, Cedric Dehos, Cedric Dufis, Pierre Busson, Pierre Vincent, Didier Belot, Pascal Urard. 252-253 [doi]
• Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOSDavid Halupka, Safeen Huda, W. Song, Ali Sheikholeslami, K. Tsunoda, C. Yoshida, M. Aoki. 256-257 [doi]
• A 64Mb MRAM with clamped-reference and adequate-reference schemesKenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe. 258-259 [doi]
• A 0.13µm 64Mb multi-layered conductive metal-oxide memoryChristophe J. Chevallier, Chang Hua Siau, Seow Fong Lim, Sri Rama Namala, Misako Matsuoka, Bruce L. Bateman, Darrell Rinerson. 260-261 [doi]
• A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAMDaisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama. 262-263 [doi]
• A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory cardShusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda. 264-265 [doi]
• A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applicationsMeng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi. 266-267 [doi]
• A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughputGuido De Sandre, Luca Bettini, Alessandro Pirola, Lionel Marmonier, Marco Pasotti, Massimo Borghi, Paolo Mattavelli, Paola Zuliani, Luca Scotti, Gianfranco Mastracchio, Ferdinando Bedeschi, Roberto Gastaldi, Roberto Bez. 268-269 [doi]
• A 45nm 1Gb 1.8V phase-change memoryCorrado Villa, Duane Mills, Gerald Barkley, Hari Giduturi, Stefan Schippers, Daniele Vimercati. 270-271 [doi]
• 2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOSChristoph Studer, Christian Benkeser, Sandro Belfanti, Quiting Huang. 274-275 [doi]
• A 4.5mW digital baseband receiver for level-A evolved EDGEChristian Benkeser, Andreas Bubenhofer, Qiuting Huang. 276-277 [doi]
• A 477mW NoC-based digital baseband for MIMO 4G SDRFabien Clermidy, Christian Bernard, Romain Lemaire, Jérôme Martin, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet, Norbert Wehn. 278-279 [doi]
• A 2Gb/s network processor with a 24mW IPsec offload for residential gatewaysYukikuni Nishida, Kenji Kawai, Keiichi Koike. 280-281 [doi]
• A 45nm resilient and adaptive microprocessor core for dynamic variation toleranceJames Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De. 282-283 [doi]
• A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variationDavid M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David Blaauw. 284-285 [doi]
• A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register fileGreg Burda, Yesh Kolla, Jim Dieffenderfer, Fadi Hamdan. 286-287 [doi]
• Millimeter-scale nearly perpetual sensor system with stacked battery and solar cellsGregory K. Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis Sylvester, David Blaauw. 288-289 [doi]
• A 16b 250MS/s IF-sampling pipelined A/D converter with background calibrationAhmed M. A. Ali, Ahmed Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed. 292-293 [doi]
• A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDRRobert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh. 294-295 [doi]
• A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOSBob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas. 296-297 [doi]
• A mostly digital variable-rate continuous-time ADC ΔΣ modulatorGerry Taylor, Ian Galton. 298-299 [doi]
• A 10b 100MS/s 4.5mW pipelined ADC with a time sharing techniqueYen-Chuan Huang, Tai-Cheng Lee. 300-301 [doi]
• A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opampBenjamin P. Hershberg, Skyler Weaver, Un-Ku Moon. 302-303 [doi]
• A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOSRahmi Hezar, Lars Risbo, Halil Kiper, Mounir Fares, Baher Haroun, G. Burra, Gabriel Gomez. 304-305 [doi]
• A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensorJun Yin, Jun Yi, Man Kay Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen. 308-309 [doi]
• A CMOS temperature sensor with an energy-efficient zoom ADC and an Inaccuracy of ±0.25°C (3s) from -40°C to 125°CKamran Souri, Mahdi Kashmiri, Kofi A. A. Makinwa. 310-311 [doi]
• A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°CFabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta. 312-313 [doi]
• A thermal-diffusivity-based temperature sensor with an untrimmed inaccuracy of ±0.2°c (3s) from -55°c to 125°cCaspar P. L. van Vroonhoven, Dan d'Aquino, Kofi A. A. Makinwa. 314-315 [doi]
• An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillatorsZhenning Wang, Richard Lin, Eshel Gordon, Hasnain Lakdawala, L. Richard Carley, Jonathan C. Jensen. 316-317 [doi]
• A 76dBΩ 1.7GHz 0.18µm CMOS tunable transimpedance amplifier using broadband current pre-amplifier for high frequency lateral micromechanical oscillatorsHossein Miri Lavasani, Wanling Pan, Brandon Harrington, Reza Abdolvand, Farrokh Ayazi. 318-319 [doi]
• A closed-loop SC interface for a ±1.4g accelerometer with 0.33% nonlinearity and 2µg/vHz input noise densityMikail Yücetas, Jarno Salomaa, Antti Kalanti, Lasse Aaltonen, Kari Halonen. 320-321 [doi]
• A 200MHz 300ps 0.5pJ/ns optical pulse generator array in 0.35µm CMOSBruce Rae, Jonathan McKendry, Zheng Gong, Erdan Gu, David R. Renshaw, Martin D. Dawson, Robert K. Henderson. 322-323 [doi]
• A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nmYu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki. 326-327 [doi]
• A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOSAmit Agarwal, Sanu Mathew, Steven Hsu, Mark Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar. 328-329 [doi]
• A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applicationsTzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang, Tsung-Chuan Ma, Yi-Hau Chen, Liang-Gee Chen. 330-331 [doi]
• A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognitionSeungjin Lee, Jinwook Oh, Minsu Kim, Junyoung Park, Joonsoo Kwon, Hoi-Jun Yoo. 332-333 [doi]
• A scalable massively parallel processor for real-time image processingTakashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto. 334-335 [doi]
• A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented realityJae-Sung Yoon, Jeong Hyun Kim, Hyo-Eun Kim, Won Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim. 336-337 [doi]
• A multimedia semantic analysis SoC (SASoC) with machine-learning engineTse-Wei Chen, Yi-ling Chen, Teng-Yuan Cheng, Chi-Sun Tang, Pei-Kuei Tsung, Tzu-Der Chuang, Liang-Gee Chen, Shao-Yi Chien. 338-339 [doi]
• A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cacheJohn Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, N. Cao. 342-343 [doi]
• A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processorJürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles Canada. 344-345 [doi]
• A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operationHyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang. 346-347 [doi]
• 2 cell in 32nm high-k metal-gate CMOSYuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe. 348-349 [doi]
• A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOSMasood Qazi, Kevin Stawiasz, Leland Chang, Anantha Chandrakasan. 350-351 [doi]
• PVT-and-aging adaptive wordline boosting for 8T SRAM power reductionArijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah. 352-353 [doi]
• SRAM stability characterization using tunable ring oscillators in 45nm CMOSJason Tsai, Seng Oon Toh, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu, Borivoje Nikolic. 354-355 [doi]
• A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body biasKoji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara. 356-357 [doi]
• 10Gb/s 15mW optical receiver with integrated Germanium photodetector and hybrid inductor peaking in 0.13µm SOI CMOS technologyDaniel Kucharski, Drew Guckenberger, Gianlorenzo Masini, Sherif Abdalla, J. Witzens, Subal Sahni. 360-361 [doi]
• An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communicationsDongmyung Lee, Jung-Won Han, Eunsoo Chang, Gunhee Han, Sung Min Park. 362-363 [doi]
• A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked OscillatorKenichi Maruko, Tatsuya Sugioka, Hiroaki Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Yuki Yagishita, Hironobu Konishi, Toshikyuki Ogata, Hisashi Owa, Taichi Niki, Kenji Konda, Masahiro Sato, Hiro Shiroshita, Takeshi Ogura, Takayuki Aoki, Hiroki Kihara, Sachiya Tanaka. 364-365 [doi]
• A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOSFulvio Spagna, Lidong Chen, Mamatha Deshpande, Yongping Fan, Doug Gambetta, Sujatha Gowder, Sitaraman Iyer, Rohit Kumar, Peter Kwok, Renuka Krishnamurthy, Chien-Chun Lin, Ravindran Mohanavelu, Roan Nicholson, Jeff Ou, M. Pasquarella, Kavitha Prasad, Hendra Rustam, Luke Tong, Amanda Tran, John Wu, Xuguang Zhang. 366-367 [doi]
• A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOSKoji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito. 368-369 [doi]
• A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOIWayne D. Dettloff, John C. Eble, Lei Luo, Pravin Kumar Venkatesan, Fred Heaton, Teva Stone, Barry Daly. 370-371 [doi]
• A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOSGanesh Balamurugan, Frank O'Mahony, Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Bryan Casper. 372-373 [doi]
• A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applicationsKe-Chung Wu, Jri Lee. 374-375 [doi]
• An 18b 12.5MHz ADC with 93dB SNRChristopher P. Hurrell, Colin Lyden, David Laing, Derek Hummerston, Mark Vickery. 378-379 [doi]
• 2 CMOS SAR ADC achieving over 90dB SFDRWenbo Liu, Pingli Huang, Yun Chiu. 380-381 [doi]
• 2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOSMasanori Furuta, Mai Nozawa, Tetsuro Itakura. 382-383 [doi]
• A 10b 50MS/s 820µW SAR ADC with on-chip digital calibrationMasato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto. 384-385 [doi]
• A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensationChun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai. 386-387 [doi]
• A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOSPieter Harpe, Cui Zhou, Xiaoyan Wang, Guido Dolmans, Harmke de Groot. 388-389 [doi]
• A 40GS/s 6b ADC in 65nm CMOSYuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang. 390-391 [doi]
• A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architectureYoungcheol Chae, Jimin Cheon, Seunghyun Lim, Dongmyung Lee, Minho Kwon, Kwisung Yoo, Wunki Jung, Dong-Hun Lee, Seogheon Ham, Gunhee Han. 394-395 [doi]
• A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple samplingYong Lim, Kyoungmin Koh, Kyungmin Kim, Han Yang, Juha Kim, Youngkyun Jeong, Seungjin Lee, Hansoo Lee, Sin-Hwan Lim, Yunseok Han, Jinwoo Kim, Jaecheol Yun, Seogheon Ham, Yun-Tae Lee. 396-397 [doi]
• A 2.7e- temporal noise 99.7% shutter efficiency 92dB dynamic range CMOS image sensor with dual global shutter pixelsKeita Yasutomi, Shinya Itoh, Shoji Kawahito. 398-399 [doi]
• A QVGA 143dB dynamic range asynchronous address-event PWM dynamic image sensor with lossless pixel-level video compressionChristoph Posch, Daniel Matolin, Rainer Wohlgenannt. 400-401 [doi]
• A CMOS image sensor for 10Mb/s 70m-range LED-based spatial optical communicationShinya Itoh, Isamu Takai, M. Shakowat Zaman Sarker, Moeta Hamai, Keita Yasutomi, Michinori Andoh, Shoji Kawahito. 402-403 [doi]
• A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binaryShingo Mandai, Makoto Ikeda, Kunihiro Asada. 404-405 [doi]
• An 80×60 range image sensor based on 10µm 50MHz lock-in pixels in 0.18µm CMOSDavid Stoppa, Nicola Massari, Lucio Pancheri, Mattia Malfatti, Matteo Perenzoni, Lorenzo Gonzo. 406-407 [doi]
• A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure techniqueTakeo Azuma, Taro Imagawa, Sanzo Ugawa, Yusuke Okada, Hiroyoshi Komobuchi, Motonori Ishii, Shigetaka Kasuga, Yoshihisa Kato. 408-409 [doi]
• A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS image sensorHayato Wakabayashi, Keiji Yamaguchi, Masafumi Okano, Souichiro Kuramochi, Oichi Kumagai, Seijiro Sakane, Masamichi Ito, Masahiro Hatano, Masaru Kikuchi, Yuuki Yamagata, Takeshi Shikanai, Ken Koseki, Keiji Mabuchi, Yasushi Maruyama, Kentaro Akiyama, Eiji Miyata, Tomoyuki Honda, Masanori Ohashi, Tetsuo Nomoto. 410-411 [doi]
• A millimeter-wave intra-connect solutionKenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri. 414-415 [doi]
• A SiGe quadrature transmitter and receiver chipset for emerging high-frequency applications at 160GHzUllrich R. Pfeiffer, Erik Öjefors, Yan Zhao. 416-417 [doi]
• A W-band 65nm CMOS transmitter front-end with 8GHz IF bandwidth and 20dB IR-ratioDan Sandström, Mikko Varonen, Mikko Kärkkäinen, Kari Halonen. 418-419 [doi]
• A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antennaAmin Arbabian, Bagher Afshar, Jun-Chau Chien, Shinwon Kang, Steven Callender, Ehsan Adabi, Stefano Dal Toso, Romain Pilard, Daniel Gloria, Ali M. Niknejad. 420-421 [doi]
• A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOSAndrea Mazzanti, Enrico Monaco, Massimo Pozzoni, Francesco Svelto. 422-423 [doi]
• A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOSJie-Wei Lai, Alberto Valdes-Garcia. 424-425 [doi]
• A high-gain 60GHz power amplifier with 20dBm output power in 90nm CMOSChi Y. Law, Anh-Vu Pham. 426-427 [doi]
• A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOSBaudouin Martineau, Vincent Knopik, Alexandre Siligaris, Frederic Gianesello, Didier Belot. 428-429 [doi]
• A 650GHz SiGe receiver front-end for terahertz imaging arraysErik Öjefors, Ullrich R. Pfeiffer. 430-431 [doi]
• A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restrictionTae-young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun Joong Kim, Jin Hyun Kim, Jin Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun. 434-435 [doi]
• 2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAMNoriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda. 436-437 [doi]
• A bitline sense amplifier for offset compensationMyoung Jin Lee, Ki Myung Kyung, Hyung-Sik Won, Myoung Su Lee, Kun-Woo Park. 438-439 [doi]
• A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stackingMitsuko Saito, Noriyuki Miura, Tadahiro Kuroda. 440-441 [doi]
• 2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interfaceHyunggon Kim, Jung-hoon Park, Ki Tae Park, Pansuk Kwak, Ohsuk Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyun Cho, Juseok Lee, Jungho Song, Soowoong Lee, Hyukjun Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, SungSoo Lee, Kyehyun Kyung, Yong-Ho Lim, Chilhee Chung. 442-443 [doi]
• A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/sG. G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, E. Sirizotti, F. Paolini, G. Imondi, G. Naso, G. Santin, L. Botticchio, L. De Santis, L. Pilolli, M. L. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. Di Francesco, Matt Goldman, Chris Haid, D. Di Cicco, D. Orlandi, F. Rori, Massimo Rossini, Tommaso Vali, R. Ghodsi, Frank Roohparvar. 444-445 [doi]
• A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOSChanghyuk Lee, Sok-Kyu Lee, Sunghoon Ahn, Jinhaeng Lee, Wonsun Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, In-Suk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jeakwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan Kim, Jeawon Choi, Taeho Jeon, Joong-Seob Yang, Yo-Hwan Koh. 446-447 [doi]
• A maximally-digital radio receiver front-endFrank Opteynde. 450-451 [doi]
• A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applicationsAli Afsahi, Arya Behzad, Lawrence E. Larson. 452-453 [doi]
• A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifierChungyeol P. Lee, Arya Behzad, Bojko Marholev, Vikram Magoon, Iqbal Bhatti, Dandan Li, Subhas Bothra, Ali Afsahi, Dayo Ojo, Rozi Roufoogaran, Tom Li, Yuyu Chang, Kishore Rama Rao, Stephen Au, Prasad Seetharam, Keith Carter, Jacob Rael, Malcolm Macintosh, Bobby Lee, Maryam Rofougaran, Reza Rofougaran, Amir Hadji-Abdolhamid, Mohammad Nariman, Shahla Khorram, Seema Anand, Ed Chien, Steve Wu, Carol Barrett, Lijun Zhang, Alireza Zolfaghari, Hooman Darabi, Ali Sarfaraz, Brima Ibrahim, Mark Gonikberg, Marcellus Forbes, Colin Fraser, Luis Gutierrez, Yury Gonikberg, Madjid Hafizi, Siukai Mak, Jesse Castaneda, Kimmer Kim, Zhenhua Liu, Stamatis Bouras, Kevin Chien, Vinay Chandrasekhar, Paul Chang, Edwin Li, ZhiMin Zhao. 454-455 [doi]
• A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifierChungyeol P. Lee, Arya Behzad, Bojko Marholev, Vikram Magoon, Iqbal Bhatti, Dandan Li, Subhas Bothra, Ali Afsahi, Dayo Ojo, Rozi Roufoogaran, Tom Li, Yuyu Chang, Kishore Rama Rao, Stephen Au, Prasad Seetharam, Keith Carter, Jacob Rael, Malcolm Macintosh, Bobby Lee, Maryam Rofougaran, Reza Rofougaran, Amir Hadji-Abdolhamid, Mohammad Nariman, Shahla Khorram, Seema Anand, Ed Chien, Steve Wu, Carol Barrett, Lijun Zhang, Alireza Zolfaghari, Hooman Darabi, Ali Sarfaraz, Brima Ibrahim, Mark Gonikberg, Marcellus Forbes, Colin Fraser, Luis Gutierrez, Yury Gonikberg, Madjid Hafizi, Siukai Mak, Jesse Castaneda, Kimmer Kim, Zhenhua Liu, Stamatis Bouras, Kevin Chien, Vinay Chandrasekhar, Paul Chang, Edwin Li, ZhiMin Zhao. 454-455 [doi]
• A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOSJun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada. 456-457 [doi]
• 2 40nm LP CMOS 0.1-to-3GHz multistandard transceiverMark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx. 458-459 [doi]
• A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoCMinsu Jeong, Bonkee Kim, Youngho Cho, Yanggyun Kim, Seyeob Kim, Heeyong Yoo, Junghwan Lee, Jae Kyung Lee, Kyung Soo Jung, Jeiyoung Lee, Junghun Lee, Huikwan Yang, Gerry Taylor, Bo-Eun Kim. 460-461 [doi]
• A multistandard multiband mobile TV RF SoC in 65nm CMOSJae-Hong Chang, Huijung Kim, Jeong-Hyun Choi, Hangun Chung, Jungwook Heo, Sanghoon Kang, Jong-Dae Bae, Heetae Oh, Youngwoon Kim, Taek Won Kwon, Ryan Kim, Wooseung Choo, Dojun Rhee, Byeong-ha Park. 462-463 [doi]
• A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body NetworksErwan Le Roux, Nicola Scolari, Budhaditya Banerjee, Claude Arm, Patrick Volet, Daniel Sigg, Pascal Heim, Jean-Félix Perotto, François Kaess, Nicolas Raemy, Alexandre Vouilloz, David Ruffieux, Matteo Contaldo, Frédéric Giroud, Daniel Séverac, Marc-Nicolas Morgan, Steve Gyger, Cedric Monneron, Thanh-Chau Le, Cesar Henzelin, Vincent Peiris. 464-465 [doi]
• A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensationColin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Marco Cusmai, Francesco Svelto. 468-469 [doi]
• A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDCTakashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi. 470-471 [doi]
• A calibration-free 800MHz fractional-N digital PLL with embedded TDCMike Shuo-Wei Chen, David Su, Srenik Mehta. 472-473 [doi]
• Spur-reduction techniques for PLLs using sub-sampling phase detectionXiang Gao, Eric A. M. Klumperink, Gerard Socci, Mounir Bohsali, Bram Nauta. 474-475 [doi]
• A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellationMarco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita. 476-477 [doi]
• A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOSWerner Grollitsch, Roberto Nonis, Nicola Da Dalt. 478-479 [doi]
• A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOSJonathan Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, Jan Craninckx. 480-481 [doi]
• A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOSSeon-Kyoo Lee, Young Hun Seo, Yunjae Suh, Hong June Park, Jae-Yoon Sim. 482-483 [doi]
• A batteryless thermoelectric energy-harvesting interface circuit with 35mV startup voltageYogesh K. Ramadass, Anantha P. Chandrakasan. 486-487 [doi]
• Palm NMR and one-chip NMRNan Sun, Tae-Jong Yoon, Hakho Lee, William Andress, Vasiliki Demas, Pablo Prado, Pablo Weissleder, Donhee Ham. 488-489 [doi]
• A 3.9mW 25-electrode reconfigured thoracic impedance/ECG SoC with body-channel transponderLong Yan, Joonsung Bae, Seulki Lee, Binhee Kim, Taehwan Roh, Kiseok Song, Hoi-Jun Yoo. 490-491 [doi]
• A multichannel DNA SoC for rapid point-of-care gene detectionDavid Garner, Hua Bai, Pantelis Georgiou, Timothy G. Constandinou, Samuel Reed, Leila Shepherd, Winston Wong, K. T. Lim, Christofer Toumazou. 492-493 [doi]
• A single-inductor AC-DC piezoelectric energy-harvester/battery-charger IC converting ±(0.35 to 1.2V) to (2.7 to 4.5V)Dongwon Kwon, Gabriel A. Rincón-Mora. 494-495 [doi]
• A 110µW 10Mb/s etextiles transceiver for body area networks with remote battery powerPatrick P. Mercier, Anantha P. Chandrakasan. 496-497 [doi]
• A 5.4dBm 42mW 2.4GHz CMOS BAW-based quasi-direct conversion transmitterMatteo Contaldo, David Ruffieux, Christian C. Enz. 498-499 [doi]
• An 8.6GHz 42ps pulse-width electrical mode-locked oscillatorMichael W. Chen, David S. Ricketts. 500-501 [doi]
• Ultra-low-voltage circuits for sensor applications powered by free-space opticsTravis Kleeburg, Jeffrey Loo, Nathaniel J. Guilar, Erin G. Fong, Rajeevan Amirtharajah. 502-503 [doi]
• Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applicationsToshishige Shimamura, Mamoru Ugajin, Kenji Suzuki, Kazuyoshi Ono, Norio Sato, Kei Kuwabara, Hiroki Morimura, Shin'ichiro Mutoh. 504-505 [doi]
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