Peter Y. K. Cheung - researchr alias

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2011

2010

Energy-Aware Optimisation for Run-Time ReconfigurationTobias Becker, Wayne Luk, Peter Y. K. Cheung. fccm 2010: 55-62 [doi]

Exploration of Heterogeneous FPGAs for Mapping Linear Projection DesignsChristos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung. tvlsi, 18(3):436-449, 2010. [doi]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010Peter Y. K. Cheung, John Wawrzynek, editors, ACM, 2010.

Process Variability and Degradation: New Frontier for ReconfigurablePeter Y. K. Cheung. arc 2010: 2 [doi]

Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case StudyBen Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes. TC, 59(4):433-448, 2010. [doi]

Benchmarking and evaluating reconfigurable architectures targeting the mobile domainPeter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu PitkÃ¤nen. todaes, 15(2), 2010. [doi]

GPU Versus FPGA for High Productivity ComputingDavid Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung. fpl 2010: 119-124 [doi]

A Salient Region Detector for GPU Using a Cellular Automata ArchitectureDavid Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung. iconip 2010: 501-508 [doi]

Efficient Heterogeneous Architecture Floorplan Optimization using Analytical MethodsAsma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. trets, 4(1):3, 2010. [doi]

Exploration of hardware sharing for image encodersSebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung. date 2010: 1737-1742 [doi]

Wave-pipelined intra-chip signaling for on-FPGA communicationsTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. integration, 43(2):188-201, 2010. [doi]

An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate ArraysAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. trets, 3(3):13, 2010. [doi]

FPGA Architecture Optimization Using Geometric ProgrammingAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. tcad, 29(8):1163-1176, 2010. [doi]

Fault tolerance and reliability in field-programmable gate arraysEdward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung. iet-cdt, 4(3):196-210, 2010. [doi]

Degradation in FPGAs: measurement and modellingEdward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung. fpga 2010: 229-238 [doi]

Degradation Analysis and Mitigation in FPGAsEdward A. Stott, Justin S. Wong, Peter Y. K. Cheung. fpl 2010: 428-433 [doi]

2009

Robust Real-Time Super-Resolution on FPGA and an Application to Video EnhancementMaria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides. trets, 2(4), 2009. [doi]

A sensor-based approach to linear blur identification for real-time video enhancementMaria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung. icip 2009: 141-144 [doi]

Parametric Design for Reconfigurable Software-Defined RadioTobias Becker, Wayne Luk, Peter Y. K. Cheung. arc 2009: 15-26 [doi]

Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAsChristos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung. trets, 1(4), 2009. [doi]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009Paul Chow, Peter Y. K. Cheung, editors, ACM, 2009.

Word-length selection for power minimization via nonlinear optimizationJonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung. todaes, 14(3), 2009. [doi]

High-throughput one-dimensional median and weighted median filters on FPGASuhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk. iet-cdt, 3(4):384-394, 2009. [doi]

Benchmarking Reconfigurable Architectures in the Mobile DomainPeter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu PitkÃ¤nen. fccm 2009: 131-138 [doi]

Heterogeneous Architecture Exploration: Analysis vs. Parameter SweepAsma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung. arc 2009: 133-144 [doi]

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systemsQiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. iet-cdt, 3(3):235-246, 2009. [doi]

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming FrameworkQiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. tcad, 28(3):305-315, 2009. [doi]

Hardware architectures for eigenvalue computation of real symmetric matricesYang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung. iet-cdt, 3(1):72-84, 2009. [doi]

A DP-network for optimal dynamic routing in network-on-chipTerrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam. codes 2009: 119-128 [doi]

Partition-based exploration for reconfigurable JPEG designsPhilip G. Potter, Wayne Luk, Peter Y. K. Cheung. date 2009: 886-889 [doi]

Compensating for variability in FPGAs by re-mapping and re-placementN. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung. fpl 2009: 613-616 [doi]

Area estimation and optimisation of FPGA routing fabricsAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. fpl 2009: 256-261 [doi]

Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor SizingLi Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung. iscas 2009: 1293-1296 [doi]

Self-Measurement of Combinatorial Circuit Delays in FPGAsJustin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung. trets, 2(2), 2009. [doi]

2008

Custom parallel caching schemes for hardware-accelerated image compressionSu-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung. jrtip, 3(4):289-302, 2008. [doi]

Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAsMaria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos. vlsisp, 51(1):3-21, 2008. [doi]

Video enhancement on an adaptive image sensorMaria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung. icip 2008: 681-684 [doi]

FPGA-based Real-time Super-Resolution on an Adaptive Image SensorMaria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides. arc 2008: 124-135 [doi]

Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance InformationSutjipto Arifin, Peter Y. K. Cheung. tmm, 10(7):1325-1341, 2008. [doi]

Towards benchmarking energy efficiency of reconfigurable architecturesTobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa. fpl 2008: 691-694 [doi]

Comments on the BCS Lecture The Future of Computer Technology and its Implications for the Computer Industry by Professor Steve FurberPeter Y. K. Cheung, Alexandre Yakovlev. cj, 51(6):741-742, 2008. [doi]

Glitch-aware output switching activity from word-level statisticsJonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith. iscas 2008: 1792-1795 [doi]

Using Reconfigurable Logic to Optimise GPU Memory AccessesBen Cope, Peter Y. K. Cheung, Wayne Luk. date 2008: 44-49 [doi]

Systematic design space exploration for customisable multi-processor architecturesBen Cope, Peter Y. K. Cheung, Wayne Luk. samos 2008: 57-64 [doi]

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming frameworkQiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. fpl 2008: 179-184 [doi]

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory OrganisationQiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. bcs 2008: 295-304 [doi]

High-throughput interconnect wave-pipelining for global communication in FPGAsTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. fpga 2008: 258 [doi]

Implementation of Wave-Pipelined Interconnects in FPGAsTerrence S. T. Mak, Crescenzo D Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk. nocs 2008: 213-214 [doi]

Interconnection lengths and delays estimation for communication links in FPGAsTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. slip 2008: 1-10 [doi]

Global interconnections in FPGAs: modeling and performance analysisTerrence S. T. Mak, Crescenzo D Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk. slip 2008: 51-58 [doi]

Characterisation of FPGA Clock VariabilityN. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung. isvlsi 2008: 322-328 [doi]

Measuring and modeling FPGA clock variabilityN. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung. fpga 2008: 258 [doi]

Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay VariationsN. Pete Sedcole, Peter Y. K. Cheung. trets, 1(2), 2008. [doi]

Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable DevicesAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. tvlsi, 16(6):733-744, 2008. [doi]

Fault tolerant methods for reliability in FPGAsEdward Stott, N. Pete Sedcole, Peter Y. K. Cheung. fpl 2008: 415-420 [doi]

Outer Loop Pipelining for Application Specific Datapaths in FPGAsKieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung. tvlsi, 16(10):1268-1280, 2008. [doi]

Combating process variation on FPGAS with a precise at-speed delay measurement methodJustin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole. fpl 2008: 703-704 [doi]

2007

A Hybrid Memory Sub-system for Video Coding ApplicationsSu-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung. fccm 2007: 317-318 [doi]

A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional informationSutjipto Arifin, Peter Y. K. Cheung. mm 2007: 68-77 [doi]

A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional InformationSutjipto Arifin, Peter Y. K. Cheung. icip 2007: 333-336 [doi]

A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on Working Memory Sutjipto Arifin, Peter Y. K. Cheung. semco 2007: 147-154 [doi]

Enhancing Relocatability of Partial Bitstreams for Run-Time ReconfigurationTobias Becker, Wayne Luk, Peter Y. K. Cheung. fccm 2007: 35-44 [doi]

Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAsChristos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung. fccm 2007: 141-150 [doi]

On the feasibility of early routing capacitance estimation for FPGAsJonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung. fpl 2007: 234-239 [doi]

Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing PerspectiveBen Cope, Peter Y. K. Cheung, Wayne Luk. asap 2007: 308-313 [doi]

Real-time hardware acceleration of the trace transformSuhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk. jrtip, 2(4):235-248, 2007. [doi]

Efficient mapping of a Kalman filter into an FPGA using Taylor ExpansionYang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung. fpl 2007: 345-350 [doi]

Automatic On-chip Memory Minimization for Data ReuseQiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. fccm 2007: 251-260 [doi]

A Hybrid Analog-Digital Routing Network for NoC Dynamic RoutingTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam. nocs 2007: 173-182 [doi]

ROM to DSP block transfer for resource constrained synthesisGareth W. Morris, George A. Constantinides, Peter Y. K. Cheung. iet-cdt, 1(1):17-26, 2007. [doi]

Run-Time Integration of Reconfigurable Video Processing SystemsN. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk. tvlsi, 15(9):1003-1016, 2007. [doi]

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysisN. Pete Sedcole, Peter Y. K. Cheung. fpga 2007: 178-187 [doi]

2006

A Flexible Multi-port Caching Scheme for Reconfigurable PlatformsSu-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk. arc 2006: 205-216 [doi]

A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentationSutjipto Arifin, Peter Y. K. Cheung. date 2006: 227-232 [doi]

User Attention Based Arousal Content ModelingSutjipto Arifin, Peter Y. K. Cheung. icip 2006: 433-436 [doi]

Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling SystemSutjipto Arifin, Peter Y. K. Cheung. fpl 2006: 1-4 [doi]

FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual CortexChristos-Savvas Bouganis, Peter Y. K. Cheung, Li Zhaoping. fpl 2006: 1-6 [doi]

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAsNicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko. fpl 2006: 1-6 [doi]

Yield enhancements of design-specific FPGAsNicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko. fpga 2006: 93-100 [doi]

Fast word-level power models for synthesis of FPGA-based arithmeticJonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung. iscas 2006: [doi]

Efficient Realtime FPGA Implementation of the Trace TransformSuhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk. fpl 2006: 1-6 [doi]

A Spatiotemporal Saliency FrameworkYang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung. icip 2006: 437-440 [doi]

Hardware efficient architectures for Eigenvalue computationYang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley. date 2006: 953-958 [doi]

On-FPGA Communication Architectures and Design FactorsTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. fpl 2006: 1-8 [doi]

On-Chip Communication in Run-Time Assembled Reconfigurable SystemsN. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk. samos 2006: 168-176 [doi]

A Novel Hueristic and Provable Bounds for Reconfigurable Architecture DesignAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. fccm 2006: 275-276 [doi]

A Novel Heuristic and Provable Bounds for Reconfigurable Architecture DesignAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. fpl 2006: 1-6 [doi]

2005

Heterogeneity Exploration for Multiple 2D Filter DesignsChristos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides. fpl 2005: 263-268

Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance SchemesNicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko. fpl 2005: 409-414

Reconfigurable Elliptic Curve Cryptosystems on a ChipRay C. C. Cheung, Wayne Luk, Peter Y. K. Cheung. date 2005: 24-29 [doi]

Automating custom-precision function evaluation for embedded processorsRay C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung. cases 2005: 22-31 [doi]

Have GPUs Made FPGAs Redundant in the Field of Video Processing?Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt. fpt 2005: 111-118

Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable LogicChun Te Ewe, Peter Y. K. Cheung, George A. Constantinides. fpl 2005: 124-129

Hardware Acceleration of Hidden Markov Model Decoding for Person DetectionSuhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk. date 2005: 8-13 [doi]

Power and Area Optimization for Multiple Restricted MultiplicationNalin Sidahao, George A. Constantinides, Peter Y. K. Cheung. fpl 2005: 112-117

A heuristic approach for multiple restricted multiplicationNalin Sidahao, George A. Constantinides, Peter Y. K. Cheung. iscas 2005: 692-695 [doi]

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