Malgorzata Marek-Sadowska - researchr alias

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Hailin Jiang, Malgorzata Marek-Sadowska. Power gating scheduling for power/ground noise reduction. dac 2008: 980-985 [doi]
Nilesh A. Modi, Malgorzata Marek-Sadowska. ECO-Map: Technology remapping for post-mask ECO using simulated annealing. iccd 2008: 652-657 [doi]
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Improving the Resolution of Single-Delay-Fault Diagnosis. tcad, 27(5):932-945, 2008. [doi]
Aida Todri, Malgorzata Marek-Sadowska. A study of reliability issues in clock distribution networks. iccd 2008: 101-106 [doi]
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Timing-Aware Multiple-Delay-Fault Diagnosis. isqed 2008: 246-253 [doi]
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz. Is there always performance overhead for regular fabric?. iccd 2008: 557-562 [doi]
Aida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya. Power supply noise aware workload assignment for multi-core systems. iccad 2008: 330-337 [doi]
Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska. Timing analysis considering IR drop waveforms in power gating designs. iccd 2008: 532-537 [doi]

Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski. Delay Fault Diagnosis for Non-Robust Test. isqed 2006: 463-472 [doi]
Hailin Jiang, Malgorzata Marek-Sadowska. Power/ground supply network optimization for power-gating. iccd 2006: [doi]
Chung-Kuan Tsai, Malgorzata Marek-Sadowska. Analysis of Process Variation s Effect on SRAM s Read Stability. isqed 2006: 603-610 [doi]
Yajun Ran, Malgorzata Marek-Sadowska. Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. tvlsi, 14(9):998-1009, 2006. [doi]
Qinghua Liu, Malgorzata Marek-Sadowska. Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. tcad, 25(4):611-624, 2006. [doi]
Yajun Ran, Malgorzata Marek-Sadowska. Designing via-configurable logic blocks for regular fabric. tvlsi, 14(1):1-14, 2006. [doi]
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Analysis and methodology for multiple-fault diagnosis. tcad, 25(3):558-575, 2006. [doi]

Chung-Kuan Tsai, Malgorzata Marek-Sadowska. An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. isqed 2005: 654-661 [doi]
Qinghua Liu, Malgorzata Marek-Sadowska. A congestion-driven placement framework with local congestion prediction. glvlsi 2005: 488-493 [doi]
Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif. Benefits and Costs of Power-Gating Technique. iccd 2005: 559-566 [doi]
Chao-Yang Yeh, Malgorzata Marek-Sadowska. Timing-aware power noise reduction in layout. iccad 2005: 627-634
Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska. mFAR: fixed-points-addition-based VLSI placement algorithm. ispd 2005: 239-241 [doi]
Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska. General skew constrained clock network sizing based on sequential linear programming. tcad, 24(5):773-782, 2005. [doi]
Qinghua Liu, Malgorzata Marek-Sadowska. Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. iccd 2005: 31-37 [doi]
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Delay-fault diagnosis using timing information. tcad, 24(9):1315-1325, 2005. [doi]
Chao-Yang Yeh, Malgorzata Marek-Sadowska. Skew-programmable clock design for FPGA and skew-aware placement. fpga 2005: 33-40 [doi]
Kai Wang, Malgorzata Marek-Sadowska. On-chip power-supply network optimization using multigrid-based technique. tcad, 24(3):407-417, 2005. [doi]
Yajun Ran, Malgorzata Marek-Sadowska. Via-configurable routing architectures and fast design mappability estimation for regular fabrics. iccad 2005: 25-32
Qinghua Liu, Malgorzata Marek-Sadowska. Wire length prediction-based technology mapping and fanout optimization. ispd 2005: 145-151 [doi]
Bo Hu, Malgorzata Marek-Sadowska. Multilevel fixed-point-addition-based VLSI placement. tcad, 24(8):1188-1203, 2005. [doi]
Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska. Eliminating false positives in crosstalk noise analysis. tcad, 24(9):1406-1419, 2005. [doi]
Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska. Clock skew bounds estimation under power supply and process variations. glvlsi 2005: 332-336 [doi]
Qinghua Liu, Malgorzata Marek-Sadowska. A study of netlist structure and placement efficiency. tcad, 24(5):762-772, 2005. [doi]

Kai Wang, Malgorzata Marek-Sadowska. Potential Slack Budgeting with Clock Skew Optimization. iccd 2004: 265-271 [doi]
Bo Hu, Malgorzata Marek-Sadowska. Fine granularity clustering-based placement. tcad, 23(4):527-536, 2004. [doi]
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska. Eliminating False Positives in Crosstalk Noise Analysis. date 2004: 1192-1197 [doi]
Qinghua Liu, Malgorzata Marek-Sadowska. A study of netlist structure and placement efficiency. ispd 2004: 198-203 [doi]
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Delay Fault Diagnosis Using Timing Information. isqed 2004: 485-490 [doi]
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Diagnosis of Hold Time Defects. iccd 2004: 192-199 [doi]
Kai Wang, Malgorzata Marek-Sadowska. Buffer sizing for clock power minimization subject to general skew constraints. dac 2004: 159-164 [doi]
Yajun Ran, Malgorzata Marek-Sadowska. An integrated design flow for a via-configurable gate array. iccad 2004: 582-589 [doi]
Yajun Ran, Malgorzata Marek-Sadowska. The Magic of a Via-Configurable Regular Fabric. iccd 2004: 338-343 [doi]
Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska. Pipelining Sequential Circuits with Wave Steering. TC, 53(9):1205-1210, 2004. [doi]
Yajun Ran, Malgorzata Marek-Sadowska. On designing via-configurable cell blocks for regular fabrics. dac 2004: 198-203 [doi]
Kai Wang, Malgorzata Marek-Sadowska. Clock network sizing via sequential linear programming with time-domain analysis. ispd 2004: 182-189 [doi]
Qinghua Liu, Malgorzata Marek-Sadowska. Pre-layout wire length and congestion estimation. dac 2004: 582-587 [doi]
Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen. Fast postplacement optimization using functional symmetries. tcad, 23(1):102-118, 2004. [doi]
Chao-Yang Yeh, Malgorzata Marek-Sadowska. Sequential delay budgeting with interconnect prediction. tvlsi, 12(10):1028-1037, 2004. [doi]
Bo Hu, Malgorzata Marek-Sadowska. Multilevel expansion-based VLSI placement with blockages. iccad 2004: 558-564 [doi]
Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska. Individual wire-length prediction with application to timing-driven placement. tvlsi, 12(10):1004-1014, 2004. [doi]

Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Multiple Fault Diagnosis Using n-Detection Tests. iccd 2003: 198 [doi]
Chao-Yang Yeh, Malgorzata Marek-Sadowska. Delay budgeting in sequential circuit with application on FPGA placement. dac 2003: 202-207 [doi]
Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska. Synthesis and placement flow for gain-based programmable regular fabrics. ispd 2003: 197-203 [doi]
Bo Hu, Malgorzata Marek-Sadowska. Fine granularity clustering for large scale placement problems. ispd 2003: 67-74 [doi]
Kai Wang, Malgorzata Marek-Sadowska. Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. date 2003: 10850-10855 [doi]
Bo Hu, Malgorzata Marek-Sadowska. Wire length prediction based clustering and its application in placement. dac 2003: 800-805 [doi]
Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska. A new reasoning scheme for efficient redundancy addition and removal. tcad, 22(7):945-951, 2003. [doi]
Yajun Ran, Malgorzata Marek-Sadowska. Crosstalk noise in FPGAs. dac 2003: 944-949 [doi]
Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer. Buffer delay change in the presence of power and ground noise. tvlsi, 11(3):461-473, 2003. [doi]
Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen. Minimizing coupling jitter by buffer resizing for coupled clock networks. iscas 2003: 509-512 [doi]
Chung-Kuan Tsai, Malgorzata Marek-Sadowska. Modeling Crosstalk Induced Delay. isqed 2003: 189-194 [doi]
Arindam Mukherjee, Malgorzata Marek-Sadowska. Wave steering to integrate logic and physical syntheses. tvlsi, 11(1):105-120, 2003. [doi]
Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska. Gain-based technology mapping for discrete-size cell libraries. dac 2003: 574-579 [doi]
Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska. PITIA: an FPGA for throughput-intensive applications. tvlsi, 11(3):354-363, 2003. [doi]
Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski. An Efficient and Effective Methodology on the Multiple Fault Diagnosis. itc 2003: 329-338 [doi]
Chao-Yang Yeh, Malgorzata Marek-Sadowska. Sequential delay budgeting with interconnect prediction. slip 2003: 23-30 [doi]
Kai Wang, Malgorzata Marek-Sadowska. On-chip power supply network optimization using multigrid-based technique. dac 2003: 113-118 [doi]
Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen. A crosstalk aware two-pin net router. iscas 2003: 485-488 [doi]
Arindam Mukherjee, Malgorzata Marek-Sadowska. Clock and Power Gating with Timing Closure. dt, 20(3):32-39, 2003. [doi]
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska. Temporofunctional crosstalk noise analysis. dac 2003: 860-863 [doi]
Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska. Wire length prediction in constraint driven placement. slip 2003: 99-105 [doi]
Chao-Yang Yeh, Malgorzata Marek-Sadowska. Minimum-Area Sequential Budgeting for FPGA. iccad 2003: 813-817 [doi]
Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen. Minimizing Inter-Clock Coupling Jitter. isqed 2003: 333-338 [doi]

Luca Macchiarulo, Malgorzata Marek-Sadowska. Wave-steering one-hot encoded FSMs. dac 2000: 357-360 [doi]
Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska. Star test: the theory and its applications. tcad, 19(9):1052-1064, 2000. [doi]
Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska. Wave Steered FSMs. date 2000: 270-276 [doi]
Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong. OBDD Minimization Based on Two-Level Representation of Boolean Functions. TC, 49(12):1371-1379, 2000. [doi]
Tong Xiao, Malgorzata Marek-Sadowska. Efficient Delay Calculation in Presence of Crosstalk. isqed 2000: 491-498 [doi]
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska. A novel high throughput reconfigurable FPGA architecture. fpga 2000: 22-29 [doi]
Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska. Fast post-placement rewiring using easily detectable functional symmetries. dac 2000: 286-289 [doi]
Tong Xiao, Malgorzata Marek-Sadowska. Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. iccd 2000: 115-120 [doi]
Lauren Hui Chen, Malgorzata Marek-Sadowska. Aggressor alignment for worst-case coupling noise. ispd 2000: 48-54 [doi]

Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang. Modeling Crosstalk in Resistive VLSI Interconnections. vlsid 1999: 470-475 [doi]
Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska. STAR-ATPG: a high speed test pattern generator for large scan designs. itc 1999: 1021-1030
Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska. Circuit Optimization by Rewiring. TC, 48(9):962-970, 1999.
Amit Singh, Malgorzata Marek-Sadowska. Circuit clustering using graph coloring. ispd 1999: 164-169 [doi]
Tong Xiao, Malgorzata Marek-Sadowska. Crosstalk Reduction by Transistor Sizing. aspdac 1999: 137-140 [doi]
Douglas Chang, Malgorzata Marek-Sadowska. Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. TC, 48(6):565-578, 1999.
Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long. Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. dac 1999: 466-471 [doi]
Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang. Crosstalk in VLSI interconnections. tcad, 18(12):1817-1824, 1999. [doi]
Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska. Logic synthesis for engineering change. tcad, 18(3):282-292, 1999. [doi]

Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak. Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ismvl 1997: 287-292 [doi]
Douglas Chang, Malgorzata Marek-Sadowska. Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. fpga 1997: 142-148 [doi]
Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang. Decomposition of Multiple-Valued Relations . ismvl 1997: 13-18 [doi]
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska. Post-Layout Logic Restructuring for Performance Optimization. dac 1997: 662-665 [doi]
Chien-Chung Tsai, Malgorzata Marek-Sadowska. Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. TC, 46(2):173-186, 1997.
Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng. A Test Synthesis Approach to Reducing BALLAST DFT Overhead. dac 1997: 466-471 [doi]
Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska. STARBIST: Scan Autocorrelated Random Pattern Generation. dac 1997: 472-477 [doi]
Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski. Scan-Encoded Test Pattern Generation for BIST. itc 1997: 548-556
Ashok Vittal, Malgorzata Marek-Sadowska. Crosstalk reduction for VLSI. tcad, 16(3):290-298, 1997. [doi]
Yu-Liang Wu, Malgorzata Marek-Sadowska. Routing for array-type FPGA s. tcad, 16(5):506-518, 1997. [doi]
Chih-Chang Lin, Malgorzata Marek-Sadowska. On designing universal logic blocks and their application to FPGA design. tcad, 16(5):519-527, 1997. [doi]
Ashok Vittal, Malgorzata Marek-Sadowska. Low-power buffered clock tree design. tcad, 16(9):965-975, 1997. [doi]
Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska. Postlayout logic restructuring using alternative wires. tcad, 16(6):587-596, 1997. [doi]

Chien-Chung Tsai, Malgorzata Marek-Sadowska. Logic Synthesis for Testability. glvlsi 1996: 118-121 [doi]
Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang. Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. tcad, 15(10):1226-1236, 1996. [doi]
Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng. Perturb and simplify: multilevel Boolean network optimizer. tcad, 15(12):1494-1504, 1996. [doi]
Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska. Graph based analysis of 2-D FPGA routing. tcad, 15(1):33-44, 1996. [doi]
Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska. Clock skew optimization for ground bounce control. iccad 1996: 395-399 [doi]
Chien-Chung Tsai, Malgorzata Marek-Sadowska. Generalized Reed-Muller Forms as a Tool to Detect Symmetries. TC, 45(1):33-40, 1996.
Chien-Chung Tsai, Malgorzata Marek-Sadowska. Multilevel Logic Synthesis for Arithmetic Functions. dac 1996: 242-247 [doi]
David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska. A New Hybrid Methodology for Power Estimation. dac 1996: 439-444 [doi]
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee. Test Point Insertion: Scan Paths through Combinational Logic. dac 1996: 268-273 [doi]
Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska. Fast Boolean optimization by rewiring. iccad 1996: 262-269 [doi]

Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska. Stepwise equivalent conductance circuit simulation technique. tcad, 12(5):672-683, 1993. [doi]

Shih-Chieh Chang, Malgorzata Marek-Sadowska. Technology Mapping via Transformations of Function Graphs. iccd 1992: 159-162

Malgorzata Marek-Sadowska, Majid Sarrafzadeh. The Crossing Distribution Problem. iccad 1991: 528-531

Malgorzata Marek-Sadowska. Pad Assignment for Power Nets in VLSI Circuits. tcad, 6(4):550-560, 1987. [doi]

Malgorzata Marek-Sadowska. Two-dimensional router for double layer layout. dac 1985: 117-123 [doi]

Jeong-Tyng Li, Malgorzata Marek-Sadowska. Global Routing for Gate Array. tcad, 3(4):298-307, 1984. [doi]
Malgorzata Marek-Sadowska. An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. tcad, 3(3):184-190, 1984. [doi]
Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh. An Efficient Single-Row Routing Algorithm. tcad, 3(3):178-183, 1984. [doi]

Malgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng. Single-Layer Routing for VLSI: Analysis and Algorithms. tcad, 2(4):246-259, 1983. [doi]