2009
- Spare Cells With Constant Insertion for Engineering ChangeYu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska. tcad, 28(3):456-460, 2009. [doi]
- Timing-Aware Multiple-Delay-Fault DiagnosisVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. tcad, 28(2):245-258, 2009. [doi]
- A study of decoupling capacitor effectiveness in power and ground grid networksAida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron. isqed 2009: 653-658 [doi]
2008
- Power gating scheduling for power/ground noise reductionHailin Jiang, Malgorzata Marek-Sadowska. dac 2008: 980-985 [doi]
- Is there always performance overhead for regular fabric?Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz. iccd 2008: 557-562 [doi]
- Timing-Aware Multiple-Delay-Fault DiagnosisVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. isqed 2008: 246-253 [doi]
- Improving the Resolution of Single-Delay-Fault DiagnosisVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. tcad, 27(5):932-945, 2008. [doi]
- ECO-Map: Technology remapping for post-mask ECO using simulated annealingNilesh A. Modi, Malgorzata Marek-Sadowska. iccd 2008: 652-657 [doi]
- A study of reliability issues in clock distribution networksAida Todri, Malgorzata Marek-Sadowska. iccd 2008: 101-106 [doi]
- Power supply noise aware workload assignment for multi-core systemsAida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya. iccad 2008: 330-337 [doi]
- Timing analysis considering IR drop waveforms in power gating designsShih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska. iccd 2008: 532-537 [doi]
2007
- Power-Gating Aware FloorplanningHailin Jiang, Malgorzata Marek-Sadowska. isqed 2007: 853-860 [doi]
- Engineering change using spare cells with constant insertionYu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska. iccad 2007: 544-547 [doi]
- OPC-Free and Minimally Irregular IC Design StyleWojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska. dac 2007: 954-957 [doi]
- An Efficient Mechanism for Performance Optimization of Variable-Latency DesignsYu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska. dac 2007: 976-981 [doi]
- Electromigration and voltage drop aware power grid optimization for power gated ICsAida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska. islped 2007: 391-394 [doi]
- Analysis and optimization of power-gated ICs with multiple power gating configurationsAida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang. iccad 2007: 783-790 [doi]
- Timing-Aware Power-Noise Reduction in PlacementChao-Yang Yeh, Malgorzata Marek-Sadowska. tcad, 26(3):527-541, 2007. [doi]
2006
- Power/ground supply network optimization for power-gatingHailin Jiang, Malgorzata Marek-Sadowska. iccd 2006: [doi]
- Semi-Individual Wire-Length Prediction With Application to Logic SynthesisQinghua Liu, Malgorzata Marek-Sadowska. tcad, 25(4):611-624, 2006. [doi]
- Delay Fault Diagnosis for Non-Robust TestVishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski. isqed 2006: 463-472 [doi]
- Designing via-configurable logic blocks for regular fabricYajun Ran, Malgorzata Marek-Sadowska. tvlsi, 14(1):1-14, 2006. [doi]
- Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular FabricsYajun Ran, Malgorzata Marek-Sadowska. tvlsi, 14(9):998-1009, 2006. [doi]
- Analysis of Process Variation s Effect on SRAM s Read StabilityChung-Kuan Tsai, Malgorzata Marek-Sadowska. isqed 2006: 603-610 [doi]
- Analysis and methodology for multiple-fault diagnosisZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. tcad, 25(3):558-575, 2006. [doi]
2005
- Multilevel fixed-point-addition-based VLSI placementBo Hu, Malgorzata Marek-Sadowska. tcad, 24(8):1188-1203, 2005. [doi]
- mFAR: fixed-points-addition-based VLSI placement algorithmBo Hu, Yue Zeng, Malgorzata Marek-Sadowska. ispd 2005: 239-241 [doi]
- Benefits and Costs of Power-Gating TechniqueHailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif. iccd 2005: 559-566 [doi]
- Clock skew bounds estimation under power supply and process variationsHailin Jiang, Kai Wang, Malgorzata Marek-Sadowska. glvlsi 2005: 332-336 [doi]
- A congestion-driven placement framework with local congestion predictionQinghua Liu, Malgorzata Marek-Sadowska. glvlsi 2005: 488-493 [doi]
- A study of netlist structure and placement efficiencyQinghua Liu, Malgorzata Marek-Sadowska. tcad, 24(5):762-772, 2005. [doi]
- Wire length prediction-based technology mapping and fanout optimizationQinghua Liu, Malgorzata Marek-Sadowska. ispd 2005: 145-151 [doi]
- Pre-layout Physical Connectivity Prediction with Application in Clustering-Based PlacementQinghua Liu, Malgorzata Marek-Sadowska. iccd 2005: 31-37 [doi]
- Via-configurable routing architectures and fast design mappability estimation for regular fabricsYajun Ran, Malgorzata Marek-Sadowska. iccad 2005: 25-32
- Eliminating false positives in crosstalk noise analysisYajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska. tcad, 24(9):1406-1419, 2005. [doi]
- An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing AnalysisChung-Kuan Tsai, Malgorzata Marek-Sadowska. isqed 2005: 654-661 [doi]
- Delay-fault diagnosis using timing informationZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. tcad, 24(9):1315-1325, 2005. [doi]
- General skew constrained clock network sizing based on sequential linear programmingKai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska. tcad, 24(5):773-782, 2005. [doi]
- On-chip power-supply network optimization using multigrid-based techniqueKai Wang, Malgorzata Marek-Sadowska. tcad, 24(3):407-417, 2005. [doi]
- Skew-programmable clock design for FPGA and skew-aware placementChao-Yang Yeh, Malgorzata Marek-Sadowska. fpga 2005: 33-40 [doi]
- Timing-aware power noise reduction in layoutChao-Yang Yeh, Malgorzata Marek-Sadowska. iccad 2005: 627-634
2004
- Fast postplacement optimization using functional symmetriesChih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen. tcad, 23(1):102-118, 2004. [doi]
- Multilevel expansion-based VLSI placement with blockagesBo Hu, Malgorzata Marek-Sadowska. iccad 2004: 558-564 [doi]
- Fine granularity clustering-based placementBo Hu, Malgorzata Marek-Sadowska. tcad, 23(4):527-536, 2004. [doi]
- Individual wire-length prediction with application to timing-driven placementQinghua Liu, Bo Hu, Malgorzata Marek-Sadowska. tvlsi, 12(10):1004-1014, 2004. [doi]
- A study of netlist structure and placement efficiencyQinghua Liu, Malgorzata Marek-Sadowska. ispd 2004: 198-203 [doi]
- Pre-layout wire length and congestion estimationQinghua Liu, Malgorzata Marek-Sadowska. dac 2004: 582-587 [doi]
- Pipelining Sequential Circuits with Wave SteeringLuca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska. TC, 53(9):1205-1210, 2004. [doi]
- Eliminating False Positives in Crosstalk Noise AnalysisYajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska. date 2004: 1192-1197 [doi]
- On designing via-configurable cell blocks for regular fabricsYajun Ran, Malgorzata Marek-Sadowska. dac 2004: 198-203 [doi]
- The Magic of a Via-Configurable Regular FabricYajun Ran, Malgorzata Marek-Sadowska. iccd 2004: 338-343 [doi]
- An integrated design flow for a via-configurable gate arrayYajun Ran, Malgorzata Marek-Sadowska. iccad 2004: 582-589 [doi]
- Clock network sizing via sequential linear programming with time-domain analysisKai Wang, Malgorzata Marek-Sadowska. ispd 2004: 182-189 [doi]
- Diagnosis of Hold Time DefectsZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. iccd 2004: 192-199 [doi]
- Buffer sizing for clock power minimization subject to general skew constraintsKai Wang, Malgorzata Marek-Sadowska. dac 2004: 159-164 [doi]
- Delay Fault Diagnosis Using Timing InformationZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. isqed 2004: 485-490 [doi]
- Potential Slack Budgeting with Clock Skew OptimizationKai Wang, Malgorzata Marek-Sadowska. iccd 2004: 265-271 [doi]
- Sequential delay budgeting with interconnect predictionChao-Yang Yeh, Malgorzata Marek-Sadowska. tvlsi, 12(10):1028-1037, 2004. [doi]
2003
- Temporofunctional crosstalk noise analysisDonald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska. dac 2003: 860-863 [doi]
- A new reasoning scheme for efficient redundancy addition and removalChih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska. tcad, 22(7):945-951, 2003. [doi]
- Buffer delay change in the presence of power and ground noiseLauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer. tvlsi, 11(3):461-473, 2003. [doi]
- Minimizing coupling jitter by buffer resizing for coupled clock networksMing-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen. iscas 2003: 509-512 [doi]
- A crosstalk aware two-pin net routerMing-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen. iscas 2003: 485-488 [doi]
- Minimizing Inter-Clock Coupling JitterMing-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen. isqed 2003: 333-338 [doi]
- Fine granularity clustering for large scale placement problemsBo Hu, Malgorzata Marek-Sadowska. ispd 2003: 67-74 [doi]
- Gain-based technology mapping for discrete-size cell librariesBo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska. dac 2003: 574-579 [doi]
- Wire length prediction based clustering and its application in placementBo Hu, Malgorzata Marek-Sadowska. dac 2003: 800-805 [doi]
- Synthesis and placement flow for gain-based programmable regular fabricsBo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska. ispd 2003: 197-203 [doi]
- Wire length prediction in constraint driven placementQinghua Liu, Bo Hu, Malgorzata Marek-Sadowska. slip 2003: 99-105 [doi]
- Wave steering to integrate logic and physical synthesesArindam Mukherjee, Malgorzata Marek-Sadowska. tvlsi, 11(1):105-120, 2003. [doi]
- Clock and Power Gating with Timing ClosureArindam Mukherjee, Malgorzata Marek-Sadowska. dt, 20(3):32-39, 2003. [doi]
- Crosstalk noise in FPGAsYajun Ran, Malgorzata Marek-Sadowska. dac 2003: 944-949 [doi]
- PITIA: an FPGA for throughput-intensive applicationsAmit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska. tvlsi, 11(3):354-363, 2003. [doi]
- Modeling Crosstalk Induced DelayChung-Kuan Tsai, Malgorzata Marek-Sadowska. isqed 2003: 189-194 [doi]
- On-chip power supply network optimization using multigrid-based techniqueKai Wang, Malgorzata Marek-Sadowska. dac 2003: 113-118 [doi]
- An Efficient and Effective Methodology on the Multiple Fault DiagnosisZhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski. itc 2003: 329-338 [doi]
- Multiple Fault Diagnosis Using n-Detection TestsZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. iccd 2003: 198 [doi]
- Power/Ground Mesh Area Optimization Using Multigrid-Based TechniqueKai Wang, Malgorzata Marek-Sadowska. date 2003: 10850-10855 [doi]
- Sequential delay budgeting with interconnect predictionChao-Yang Yeh, Malgorzata Marek-Sadowska. slip 2003: 23-30 [doi]
- Minimum-Area Sequential Budgeting for FPGAChao-Yang Yeh, Malgorzata Marek-Sadowska. iccad 2003: 813-817 [doi]
- Delay budgeting in sequential circuit with application on FPGA placementChao-Yang Yeh, Malgorzata Marek-Sadowska. dac 2003: 202-207 [doi]
2002
- ATPG-based logic synthesis: an overviewChih-Wei Jim Chang, Malgorzata Marek-Sadowska. iccad 2002: 786-789 [doi]
- Efficient Closed-Form Crosstalk Delay MetricsLauren Hui Chen, Malgorzata Marek-Sadowska. isqed 2002: 431-436 [doi]
- Closed-Form Crosstalk Noise Metrics for Physical Design ApplicationsLauren Hui Chen, Malgorzata Marek-Sadowska. date 2002: 812-819 [doi]
- Incremental delay change due to crosstalk noiseLauren Hui Chen, Malgorzata Marek-Sadowska. ispd 2002: 120-125 [doi]
- Coping with buffer delay change due to power and ground noiseLauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer. dac 2002: 860-865 [doi]
- Congestion minimization during placement without estimationBo Hu, Malgorzata Marek-Sadowska. iccad 2002: 739-745 [doi]
- FAR: fixed-points addition & relaxation based placementBo Hu, Malgorzata Marek-Sadowska. ispd 2002: 161-166 [doi]
- Sizing Power/Ground Meshes for Clocking and Computing Circuit ComponentsArindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska. date 2002: 176-185 [doi]
- Efficient circuit clustering for area and power reduction in FPGAsAmit Singh, Malgorzata Marek-Sadowska. fpga 2002: 59-66 [doi]
- Efficient circuit clustering for area and power reduction in FPGAsAmit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska. todaes, 7(4):643-663, 2002. [doi]
- FPGA interconnect planningAmit Singh, Malgorzata Marek-Sadowska. slip 2002: 23-30 [doi]
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