Takayasu Sakurai - researchr alias

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2011

0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting ApplicationsPo-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai. ieicet, 94-C(4):598-604, 2011. [doi]

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V::DD::) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V::DD:: between flip-flops and combinational logicsHiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. islped 2010: 163-168 [doi]

Reduction of minimum operating voltage (V::DDmin::) of CMOS logic circuits with post-fabrication automatically selective charge injectionKentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. islped 2010: 175-180 [doi]

1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted SignalingKatsuyuki Ikeuchi, Hideki Kusamitsu, Mutsuo Daito, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai. ieicet, 94-C(6):992-998, 2011. [doi]

0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB ReceiverLechang Liu, Takayasu Sakurai, Makoto Takamiya. ieicet, 94-C(6):985-991, 2011. [doi]

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7 Current Efficiency in 65 nm CMOSYasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai. ieicet, 94-C(6):938-944, 2011. [doi]

Designing ultra-low voltage logicTakayasu Sakurai. islped 2010: 57-58 [doi]

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOSTadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. islped 2010: 21-26 [doi]

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route LayoutTadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai. ieicet, 94-C(6):1072-1075, 2011. [doi]

A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57 Ripple Reduction at Low Output VoltageXin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya. ieicet, 94-C(6):953-959, 2011. [doi]

An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOSXin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. aspdac 2011: 109-110 [doi]

2010

3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP sKoichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai. 3dic 2010: 1-4 [doi]

A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systemsGil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai. 3dic 2010: 1-4 [doi]

A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOSLechang Liu, Zhiwei Zhou, Takayasu Sakurai, Makoto Takamiya. ieicet, 93-C(6):796-802, 2010. [doi]

Misleading energy and performance claims in sub/near threshold digital systemsYu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai. iccad 2010: 625-631 [doi]

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designsYoungsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai. todaes, 15(4), 2010. [doi]

Design of large area electronics with organic transistorsMakoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai. iccad 2010: 500-503 [doi]

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic CircuitsTadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai. ieicet, 93-C(3):332-339, 2010. [doi]

Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash MemoriesTadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi. ieicet, 93-C(3):317-323, 2010. [doi]

2009

A capacitive coupling interface with high sensitivity for wireless wafer testingGil-Su Kim, Makoto Takamiya, Takayasu Sakurai. 3dic 2009: 1-5 [doi]

A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiverLechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. aspdac 2009: 97-98 [doi]

A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOSLechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. ieicet, 92-C(6):769-776, 2009. [doi]

An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply NoiseYasumi Nakamura, Makoto Takamiya, Takayasu Sakurai. ieicet, 92-C(4):468-474, 2009. [doi]

Effect of resistance of TSV s on performance of boost converter for low power 3D SSD with NAND flash memoriesTadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi. 3dic 2009: 1-4 [doi]

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memoriesTadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi. islped 2009: 87-92 [doi]

2008

2007

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled TransistorsKoichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai. ieicet, 90-C(4):786-792, 2007. [doi]

Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC LinesHiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai. ieicet, 90-A(12):2669-2681, 2007. [doi]

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS LinkKiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda. ieicet, 90-C(4):829-835, 2007. [doi]

Meeting with the forthcoming IC designTakayasu Sakurai. sbcci 2007: 2 [doi]

Meeting with the Forthcoming IC Design The Era of Power, Variability and NRE Explosion and a Bit of the Future Takayasu Sakurai. aspdac 2007: [doi]

A Self-Alignment Row-by-Row Variable-::::V::DD:::::: Scheme Reducing 90 of Active-Leakage Power in SRAM sFayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai. ieicet, 90-C(4):743-748, 2007. [doi]

2006

Trends of On-Chip Interconnects in Deep Sub-Micron VLSIDanardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai. ieicet, 89-C(3):392-394, 2006. [doi]

Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI sDanardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai. ieicet, 89-A(12):3569-3578, 2006. [doi]

A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppressionKoichi Ishida, Atit Tamtrakarn, Takayasu Sakurai. aspdac 2006: 98-99 [doi]

Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIsKyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai. tvlsi, 14(4):430-435, 2006. [doi]

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications TechnologyDaisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda. ieicet, 89-C(3):320-326, 2006. [doi]

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V::TH::/V::DD:: and Micro-V::DD::-HoppingCanh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai. ieicet, 89-C(3):280-286, 2006. [doi]

2005

/spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applicationsHiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai. tmm, 7(1):67-74, 2005. [doi]

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-::::V::DD:::::: SRAM sKyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai. ieicet, 88-C(4):760-767, 2005. [doi]

Frequency-voltage cooperative CPU power control: A design rule and its application by feedback predictionKeisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai. scjapan, 36(6):39-48, 2005. [doi]

More than two orders of magnitude leakage current reduction in look-up table for FPGAsCanh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai. iscas 2005: 4701-4704 [doi]

2003

Reshaping EDA for powerJan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang. dac 2003: 15 [doi]

2002

Energy-Constrained V::DD:: Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI SystemsSeongsoo Lee, Seungjun Lee, Takayasu Sakurai. jcsc, 11(6):601-620, 2002. [doi]

CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuitsKyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai. iscas 2002: 545-548 [doi]

Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technologyKoichi Nose, Takayasu Sakurai. islped 2002: 24-29 [doi]

Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited)Takayasu Sakurai. isqed 2002: 445-450 [doi]

Minimizing power across multiple technology and design levelsTakayasu Sakurai. iccad 2002: 24-27 [doi]

2001

2000

Compact yet high performance (CyHP) library for short time-to-market with new technologiesNguyen Minh Duc, Takayasu Sakurai. aspdac 2000: 475-480 [doi]

Run-time power control scheme using software feedback loop for low-power real-time applicationSeongsoo Lee, Takayasu Sakurai. aspdac 2000: 381-386 [doi]

Run-time voltage hopping for low-power real-time systemsSeongsoo Lee, Takayasu Sakurai. dac 2000: 806-809 [doi]

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)Koichi Nose, Soo-Ik Chae, Takayasu Sakurai. islped 2000: 228-230 [doi]

Optimization of VDD and VTH for low-power and high speed applicationsKoichi Nose, Takayasu Sakurai. aspdac 2000: 469-474 [doi]

Analysis and future trend of short-circuit powerKoichi Nose, Takayasu Sakurai. tcad, 19(9):1023-1030, 2000. [doi]

Reducing Power Consumption of CMOS VLSI s through VDD and VTH ControlTakayasu Sakurai. isqed 2000: 417-424 [doi]

Design challenges for 0.1um and beyond: embedded tutorialTakayasu Sakurai. aspdac 2000: 553-558 [doi]

Power Optimization of Real-Time Embedded Systems on Variable Speed ProcessorsYoungsoo Shin, Kiyoung Choi, Takayasu Sakurai. iccad 2000: 365-368

1998

Delay and Noise Formulas for Capacitively Coupled Distributed RC LinesHiroshi Kawaguchi, Takayasu Sakurai. aspdac 1998: 35-43

Integrated Current Sensing Device for Micro IDDQ TestKoichi Nose, Takayasu Sakurai. ats 1998: 323-326 [doi]

1996

Substrate noise influence on circuit performance in variable threshold-voltage schemeTadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai. islped 1996: 309-312 [doi]

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI designTadahiro Kuroda, Takayasu Sakurai. vlsisp, 13(2-3):191-201, 1996. [doi]

1993

High-Speed Circuit Design with Scaled-Down MOSFET s and Low Supply VoltageTakayasu Sakurai. iscas 1993: 1487-1490

1992

Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extractionTakayasu Sakurai, Bill Lin, A. Richard Newton. tcad, 11(2):228-234, 1992. [doi]