| 2357 | -- | 2370 | Debesh Bhatta, Nicholas Tzou, Joshua W. Wells, Sen-Wen Hsiao, Abhijit Chatterjee. Incoherent Undersampling-Based Waveform Reconstruction Using a Time-Domain Zero-Crossing Metric |
| 2371 | -- | 2383 | HoKyu Lee, Aurangozeb, Sejin Park, Jintae Kim, Chulwoo Kim. A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter |
| 2384 | -- | 2394 | Muhammad Ahmadi, Won Namgoong. Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation |
| 2395 | -- | 2407 | Jintae Kim, Siamak Modjtahedi, Chih-Kong Ken Yang. A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters |
| 2408 | -- | 2416 | Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony Tae-Hyoung Kim. An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications |
| 2417 | -- | 2430 | Ivan Ukhov, Petru Eles, Zebo Peng. Temperature-Centric Reliability Analysis and Optimization of Electronic Systems Under Process Variation |
| 2431 | -- | 2437 | Yuejian Wu, Sandy Thomson, Han Sun, David Krause, Song Yu, George Kurio. Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs |
| 2438 | -- | 2446 | Ghasem Pasandi, Sied Mehdi Fakhraie. A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations |
| 2447 | -- | 2460 | Michail Maniatakos, Maria K. Michael, Yiorgos Makris. Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving |
| 2461 | -- | 2472 | Salomon Beer, Ran Ginosar. A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance |
| 2473 | -- | 2486 | Bo-Cheng Charles Lai, Kuan-Ting Chen, Ping-Ru Wu. A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems |
| 2487 | -- | 2496 | Ching-Che Chung, Duo Sheng, Chang-Jun Li. A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector |
| 2497 | -- | 2507 | Enrique F. Cantó-Navarro, Mariano Lopez Garcia, Rafael Ramos-Lara, Raul Sánchez-Reillo. Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units |
| 2508 | -- | 2518 | Jun Lin, Zhiyuan Yan. An Efficient List Decoder Architecture for Polar Codes |
| 2519 | -- | 2530 | Ying Teng, Baris Taskin. ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design |
| 2531 | -- | 2539 | Gian Domenico Licciardo, Antonio D'Arienzo, Alfredo Rubino. Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images |
| 2540 | -- | 2551 | Babak Zamanlooy, Mitra Mirhassani. CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning |
| 2552 | -- | 2565 | Mahdi Nikdast, Jiang Xu, Luan Huu Kinh Duong, Xiaowen Wu, Xuan Wang, Zhehui Wang, Zhe Wang, Peng Yang, Yaoyao Ye, Qinfen Hao. Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison |
| 2566 | -- | 2580 | Leibo Liu, Chen Wu, Chenchen Deng, Shouyi Yin, Qinghua Wu, Jie Han, Shaojun Wei. A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures |
| 2581 | -- | 2594 | Dajiang Liu, Shouyi Yin, Yu Peng, Leibo Liu, Shaojun Wei. Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures |
| 2595 | -- | 2605 | Liuxi Qian, Zhaori Bi, Dian Zhou, Xuan Zeng. Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework |
| 2606 | -- | 2616 | Jia Wang, Xuanxing Xiong, Xingwu Zheng. Deterministic Random Walk: A New Preconditioner for Power Grid Analysis |
| 2617 | -- | 2628 | Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification |
| 2629 | -- | 2638 | Irith Pomeranz. Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction |
| 2639 | -- | 2647 | Xiaolong Zhang, Huiyun Li, Li Jiang, Qiang Xu. A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method |
| 2648 | -- | 2656 | Mohamed Elshamy, Hassan Mostafa, Yehya H. Ghallab, Mohamed Sameh Said. A Novel Nondestructive Read/Write Circuit for Memristor-Based Memory Arrays |
| 2657 | -- | 2670 | Marjan Asadinia, Mohammad Arjomand, Hamid Sarbazi-Azad. Variable Resistance Spectrum Assignment in Phase Change Memory Systems |
| 2671 | -- | 2675 | Myonglae Chu, Byoungho Kim, Byung Geun Lee. A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-µm CMOS Technology |
| 2676 | -- | 2679 | Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls. Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages |
| 2680 | -- | 2684 | Dandan Zhang, Hai-Gang Yang, Wen-rui Zhu, Wei Li, Zhihong Huang, Lin Li, Tianyi Li. A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter |
| 2685 | -- | 2689 | Hyun Kim, Chae-Eun Rhee, Hyuk-Jae Lee. An Effective Combination of Power Scaling for H.264/AVC Compression |
| 2690 | -- | 2694 | Alex Pappachen James, Dinesh Sasi Kumar, Arun Ajayan. Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication |
| 2695 | -- | 2699 | Ke Chen, Jie Han, Fabrizio Lombardi. On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells |
| 2700 | -- | 2704 | Zhu Wang, Zonghua Gu, Zili Shao. WCET-Aware Energy-Efficient Data Allocation on Scratchpad Memory for Real-Time Embedded Systems |
| 2705 | -- | 2708 | David Money Harris. Sequential Element Timing Parameter Definition Considering Clock Uncertainty |
| 2709 | -- | 2713 | Jae-Hoon Kim, Wook Kim, Young-Hwan Kim. Efficient Statistical Timing Analysis Using Deterministic Cell Delay Models |
| 2714 | -- | 2718 | Xiaobin Yuan, Pawel Owczarczyk, Alan J. Drake, Marshall D. Tiner, David T. Hui, John P. Pennings, Francesco A. Campisano, Richard L. Willaman, Leana M. Cropp, Rudolph D. Dussault. Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths |
| 2719 | -- | 2723 | Chien-Hui Liao, Charles H.-P. Wen. Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization |
| 2724 | -- | 2727 | Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha. Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations |
| 2728 | -- | 2732 | Chao Wang, Yuwei Yan, Xiaoyu Fu. 3 FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems |
| 2733 | -- | 2737 | Yongtae Kim, Yong Zhang, Peng Li. Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic Computing |
| 2738 | -- | 2742 | Roger Yubtzuan Chen, Zong-Yi Yang. CMOS Transimpedance Amplifier for Visible Light Communications |
| 2743 | -- | 2747 | Hao Wang, Kai Zhao, Jiangpeng Li, Tong Zhang 0002. Optimizing the Use of STT-RAM in SSDs Through Data-Dependent Error Tolerance |
| 2748 | -- | 2752 | Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung. Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology |
| 2753 | -- | 2756 | Kung Chi Cinnati Loi, Seok-Bum Ko. Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves |