Alex Orailoglu - researchr alias

researchr

You are not signed in
Sign in
Sign up

2011

Toward Future Systems with Nanoscale Devices: Overcoming the Reliability ChallengeWenjing Rao, Chengmo Yang, Ramesh Karri, Alex Orailoglu. Computer, 44(2):46-53, 2011. [doi]

Migration-aware adaptive MPSoC static schedules with dynamic reconfigurabilityYuping Zhang, Chun Jason Xue, Chengmo Yang, Alex Orailoglu. jpdc, 71(10):1400-1410, 2011. [doi]

2010

Delay test quality maximization through process-aware selection of test set sizeBaris Arslan, Alex Orailoglu. iccd 2010: 390-395 [doi]

Performance and energy efficient cache migrationapproach for thermal management in embedded systemsRaid Ayoub, Alex Orailoglu. glvlsi 2010: 365-368 [doi]

Dynamic, non-linear cache architecture for power-sensitive mobile processorsGaro Bournoutian, Alex Orailoglu. codes 2010: 187-194 [doi]

Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test schemeMingjing Chen, Alex Orailoglu. date 2010: 63-68 [doi]

VDDmin test optimization for overscreening minimization through adaptive scan chain maskingMingjing Chen, Alex Orailoglu. vts 2010: 313-318 [doi]

DiSC: A New Diagnosis Method for Multiple Scan Chain FailuresSunghoon Chun, Alex Orailoglu. tcad, 29(12):2051-2055, 2010. [doi]

High durability in NAND flash memory through effective page reuse mechanismsKwangyoon Lee, Alex Orailoglu. codes 2010: 205-212 [doi]

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010João Antonio Martino, Guido Araujo, Alex Orailoglu, Felipe Klein, editors, ACM, 2010.

Fine-grained adaptive CMP cache sharing through access history exploitationChengmo Yang, Chun Jason Xue, Alex Orailoglu. vlsi 2010: 420-425 [doi]

Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurationsChengmo Yang, Alex Orailoglu. vlsi 2010: 396-401 [doi]

2009

Filtering Global History: Power and Performance Efficient Branch PredictorRaid Ayoub, Alex Orailoglu. asap 2009: 203-206 [doi]

Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructionsGaro Bournoutian, Alex Orailoglu. cases 2009: 117-126 [doi]

Flip-Flop Hardening and Selection for Soft Error and Delay Fault ResilienceMingjing Chen, Alex Orailoglu. dft 2009: 49-57 [doi]

Deflecting crosstalk by routing reconsideration through refined signal correlation estimationMingjing Chen, Alex Orailoglu. glvlsi 2009: 369-374 [doi]

Scan power reduction in linear test data compression schemeMingjing Chen, Alex Orailoglu. iccad 2009: 78-82 [doi]

Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancySaturnino Garcia, Alex Orailoglu. date 2009: 898-901 [doi]

Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008Alex Orailoglu, L. Pozzi. tcad, 28(12):1786-1787, 2009. [doi]

Logic Mapping in Crossbar-Based NanoarchitecturesWenjing Rao, Alex Orailoglu, Ramesh Karri. dt, 26(1):68-77, 2009. [doi]

Scan Cell Positioning for Boosting the Compression of Fan-Out NetworksOzgur Sinanoglu, Mohammed Al-Mulla, Noora A. Shunaiber, Alex Orailoglu. jcst, 24(5):939-948, 2009. [doi]

Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan ArchitectureDong Xiang, Dianwei Hu, Qiang Xu, Alex Orailoglu. tcad, 28(7):1101-1105, 2009. [doi]

Squashing microcode stores to size in embedded systems while delivering rapid microcode accessesChengmo Yang, Mingjing Chen, Alex Orailoglu. codes 2009: 249-256 [doi]

Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitudeChengmo Yang, Alex Orailoglu. date 2009: 63-68 [doi]

Processor reliability enhancement through compiler-directed register file peak temperature reductionChengmo Yang, Alex Orailoglu. dsn 2009: 468-477 [doi]

2008

Miss reduction in embedded processors through dynamic, power-friendly cache designGaro Bournoutian, Alex Orailoglu. dac 2008: 304-309 [doi]

Test cost minimization through adaptive test developmentMingjing Chen, Alex Orailoglu. iccd 2008: 234-239 [doi]

Scheduling Power-Constrained Tests through the SoC Functional BusFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara. ieicet, 91-D(3):736-746, 2008. [doi]

Application specific non-volatile primary memory for embedded systemsKwangyoon Lee, Alex Orailoglu. codes 2008: 31-36 [doi]

Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded SystemsKwangyoon Lee, Alex Orailoglu. sasp 2008: 69-74 [doi]

Towards fault tolerant parallel prefix adders in nanoelectronic systemsWenjing Rao, Alex Orailoglu. date 2008: 360-365 [doi]

A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronizationChengmo Yang, Alex Orailoglu. cases 2008: 11-20 [doi]

2007

Power efficient register file update approach for embedded processorsRaid Ayoub, Alex Orailoglu. iccd 2007: 431-437 [doi]

Architectures for Silicon Nanoelectronics and BeyondR. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram. Computer, 40(1):25-33, 2007. [doi]

Circuit-level mismatch modelling and yield optimization for CMOS analog circuitsMingjing Chen, Alex Orailoglu. iccd 2007: 526-532 [doi]

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional BusesFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara. aspdac 2007: 720-725 [doi]

On the identification of modular test requirements for low cost hierarchical test path constructionYiorgos Makris, Alex Orailoglu. integration, 40(3):315-325, 2007. [doi]

Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual MemoryPeter Petrov, Alex Orailoglu. ijpp, 35(2):157-177, 2007. [doi]

Towards Nanoelectronics Processor ArchitecturesWenjing Rao, Alex Orailoglu, Ramesh Karri. et, 23(2-3):235-254, 2007. [doi]

Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAsWenjing Rao, Alex Orailoglu, Ramesh Karri. date 2007: 865-869 [doi]

Fault Tolerant Approaches to Nanoelectronic Programmable Logic ArraysWenjing Rao, Alex Orailoglu, Ramesh Karri. dsn 2007: 216-224 [doi]

Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedulesChengmo Yang, Alex Orailoglu. codes 2007: 15-20 [doi]

Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCsChengmo Yang, Alex Orailoglu. cases 2007: 150-154 [doi]

2006

Decision Tree Based Mismatch Diagnosis in Analog CircuitsMingjing Chen, Hosam Haggag, Alex Orailoglu. vts 2006: 278-285 [doi]

Power-Constrained SOC Test Schedules through Utilization of Functional BusesFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara. iccd 2006: [doi]

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic FabricsWenjing Rao, Alex Orailoglu, Ramesh Karri. emnets 2006: 63-68 [doi]

Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault ToleranceWenjing Rao, Alex Orailoglu, Ramesh Karri. vts 2006: 214-221 [doi]

Topology aware mapping of logic functions onto nanowire-based crossbar architecturesWenjing Rao, Alex Orailoglu, Ramesh Karri. dac 2006: 723-726 [doi]

Power efficient branch prediction through early identification of branch addressesChengmo Yang, Alex Orailoglu. cases 2006: 169-178 [doi]

Power-efficient instruction delivery through trace reuseChengmo Yang, Alex Orailoglu. IEEEpact 2006: 192-201 [doi]

2005

A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor busesRaid Ayoub, Alex Orailoglu. aspdac 2005: 729-734 [doi]

The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective ImplementationsIsmet Bayraktaroglu, Alex Orailoglu. TC, 54(1):61-75, 2005. [doi]

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005Carlos Galup-Montoro, Sergio Bampi, Alex Orailoglu, editors, ACM, 2005.

A reprogrammable customization framework for efficient branch resolution in embedded processorsPeter Petrov, Alex Orailoglu. tecs, 4(2):452-468, 2005. [doi]

Energy-effcient physically tagged caches for embedded processors with virtual memoryPeter Petrov, Daniel Tracy, Alex Orailoglu. dac 2005: 17-22 [doi]

Fault tolerant nanoelectronic processor architecturesWenjing Rao, Alex Orailoglu, Ramesh Karri. aspdac 2005: 311-316 [doi]

Architectural-Level Fault Tolerant Computation in Nanoelectronic ProcessorsWenjing Rao, Alex Orailoglu, Ramesh Karri. iccd 2005: 533-542 [doi]

Efficient RT-Level Fault DiagnosisOzgur Sinanoglu, Alex Orailoglu. jcst, 20(2):166-174, 2005. [doi]

Test power reductions through computationally efficient, decoupled scan chain modificationsOzgur Sinanoglu, Alex Orailoglu. tr, 54(2):215-223, 2005. [doi]

Forward discrete probability propagation method for device performance characterization under process variationsRasit Onur Topaloglu, Alex Orailoglu. aspdac 2005: 220-223 [doi]

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACsRasit Onur Topaloglu, Alex Orailoglu. dac 2005: 851-856 [doi]

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operandsTongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu. aspdac 2005: 1192-1195 [doi]

2004

Extending the Applicability of Parallel-Serial Scan DesignsBaris Arslan, Ozgur Sinanoglu, Alex Orailoglu. iccd 2004: 200-203 [doi]

CircularScan: A Scan Architecture for Test Cost ReductionBaris Arslan, Alex Orailoglu. date 2004: 1290-1295 [doi]

Test Cost Reduction Through A Reconfigurable Scan ArchitectureBaris Arslan, Alex Orailoglu. itc 2003: 945-952 [doi]

Design space exploration for aggressive test cost reduction in CircularScan architecturesBaris Arslan, Alex Orailoglu. iccad 2004: 726-731 [doi]

Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent testYiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu. tr, 53(2):269-278, 2004. [doi]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004Alex Orailoglu, Pai H. Chou, Petru Eles, Axel Jantsch, editors, ACM, 2004.

Seamless Test of Digital Components in Mixed-Signal PathsSule Ozev, Ismet Bayraktaroglu, Alex Orailoglu. dt, 21(1):44-55, 2004. [doi]

Design of concurrent test Hardware for Linear analog circuits with constrained hardware overheadSule Ozev, Alex Orailoglu. tvlsi, 12(7):756-765, 2004. [doi]

End-to-End Testability Analysis and DfT Insertion for Mixed-Signal PathsSule Ozev, Alex Orailoglu. iccd 2004: 72-77 [doi]

Transforming Binary Code for Low-Power Embedded ProcessorsPeter Petrov, Alex Orailoglu. micro, 24(3):21-33, 2004. [doi]

Low-power instruction bus encoding for embedded processorsPeter Petrov, Alex Orailoglu. tvlsi, 12(8):812-826, 2004. [doi]

Tag compression for low power in dynamically customizable embedded processorsPeter Petrov, Alex Orailoglu. tcad, 23(7):1031-1047, 2004. [doi]

Frugal linear network-based test decompression for drastic test cost reductionsWenjing Rao, Alex Orailoglu, G. Su. iccad 2004: 721-725 [doi]

Fault Tolerant Arithmetic with Applications in Nanotechnology based SystemsWenjing Rao, Alex Orailoglu, Ramesh Karri. itc 2003: 472-478 [doi]

Efficient RT-level fault diagnosis methodologyOzgur Sinanoglu, Alex Orailoglu. aspdac 2004: 212-217 [doi]

Scan Power Minimization through Stimulus and Response TransformationsOzgur Sinanoglu, Alex Orailoglu. date 2004: 404-409 [doi]

Fast and energy-frugal deterministic test through efficient compression and compaction techniquesOzgur Sinanoglu, Alex Orailoglu. jsa, 50(5):257-266, 2004. [doi]

Autonomous Yet Deterministic Test of SOC CoresOzgur Sinanoglu, Alex Orailoglu. itc 2003: 1359-1368 [doi]

On mismatch in the deep sub-micron era - from physics to circuitsRasit Onur Topaloglu, Alex Orailoglu. aspdac 2004: 62-67 [doi]

Searching for Global Test Costs Optimization in Core-Based SystemsÉrika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu. et, 20(4):357-373, 2004. [doi]

2003

Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault InformationBaris Arslan, Alex Orailoglu. ats 2003: 230-235 [doi]

Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan DesignsIsmet Bayraktaroglu, Alex Orailoglu. TC, 52(11):1480-1489, 2003. [doi]

Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and CompressionIsmet Bayraktaroglu, Alex Orailoglu. vts 2003: 113-120 [doi]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003Rajesh Gupta, Yukihiro Nakamura, Alex Orailoglu, Pai H. Chou, editors, ACM, 2003.

Guest Editors Introduction: Application-Specific MicroprocessorsAlex Orailoglu, Alexander V. Veidenbaum. dt, 20(1):6-7, 2003.

Guest Editor s IntroductionAlex Orailoglu. ijpp, 31(6):407-409, 2003. [doi]

Low-power Branch Target Buffer for Application-Specific Embedded ProcessorsPeter Petrov, Alex Orailoglu. dsdm 2003: 158-165 [doi]

Application-Specific Instruction Memory Customizations for Power-Efficient Embedded ProcessorsPeter Petrov, Alex Orailoglu. dt, 20(1):18-25, 2003. [doi]

Virtual Page Tag Reduction for Low-power TLBsPeter Petrov, Alex Orailoglu. iccd 2003: 371-374 [doi]

Power Efficiency through Application-Specific Instruction Memory TransformationsPeter Petrov, Alex Orailoglu. date 2003: 10030-10035 [doi]

Customizable Embedded Processor ArchitecturesPeter Petrov, Alex Orailoglu. dsdm 2003: 468-475 [doi]

Test application time and volume compression through seed overlappingWenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu. dac 2003: 732-737 [doi]

Virtual Compression through Test Vector Stitching for Scan Based DesignsWenjing Rao, Alex Orailoglu. date 2003: 10104-10109 [doi]

Reducing Average and Peak Test Power Through Scan Chain ModificationOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu. et, 19(4):457-467, 2003. [doi]

Compacting Test Responses for Deeply Embedded SoC CoresOzgur Sinanoglu, Alex Orailoglu. dt, 20(4):22-30, 2003. [doi]

Partial Core Encryption for Performance-Efficient Test of SOCsOzgur Sinanoglu, Alex Orailoglu. iccad 2003: 91-94 [doi]

Aggressive Test Power Reduction Through Test Stimuli TransformationOzgur Sinanoglu, Alex Orailoglu. iccd 2003: 542-547 [doi]

Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan TestOzgur Sinanoglu, Alex Orailoglu. ats 2003: 202-209 [doi]

PreviousNext