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2025

Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA ResearchVidya A. Chhabria, Jiang Hu, Andrew B. Kahng, Sachin S. Sapatnekar. ispd 2025: 93-101 [doi]

Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC AcceleratorsHadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang. todaes, 30(1):1-34, 2025. [doi]

Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background ClusteringShiyu Guo, Yuhao Ju, Xi Chen, Sachin S. Sapatnekar, Jie Gu 0001. jssc, 60(1):125-135, January 2025. [doi]

Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACsNibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar. tcad, 44(4):1210-1223, April 2025. [doi]

Towards Designing and Deploying Ising MachinesSachin S. Sapatnekar. ispd 2025: 1 [doi]

2024

A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed RouteVidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar. todaes, 29(1), January 2024. [doi]

OpenROAD and CircuitOps: Infrastructure for ML EDA Research and EducationVidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu. vts 2024: 1-4 [doi]

Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool AssistantsVidya A. Chhabria, Bing-Yue Wu, Utsav Sharma, Kishor Kunal, Austin Rovinski, Sachin S. Sapatnekar. iccad 2024: [doi]

On Gate Flip Errors in Computing-In-MemoryZamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu. date 2024: 1-6 [doi]

On Error Correction for Nonvolatile Processing-In-MemoryHüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. isca 2024: 678-692 [doi]

An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning AcceleratorsHadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng. todaes, 29(4):1-33, 2024. [doi]

2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile DevicesShiyu Guo, Sachin S. Sapatnekar, Jie Gu 0003. isscc 2024: 44-46 [doi]

Software-Hardware Codesign of Ray-Tracing Accelerator for Edge AR/VR With Viewpoint-Focused 3D Construction and Efficient Data StructureShiyu Guo, Sachin S. Sapatnekar, Jie Gu 0001. mwscas 2024: 267-271 [doi]

IR-Aware ECO Timing Optimization Using Reinforcement LearningWenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar. mlcad 2024: [doi]

Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power AmplifiersNibedita Karmokar, Sai-Wang Tam, Thanh Viet Dinh, Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar. iccad 2024: [doi]

Automated synthesis of mixed-signal ML inference hardware under accuracy constraintsKishor Kunal, Jitesh Poojary, S. Ramprasath 0001, Ramesh Harjani, Sachin S. Sapatnekar. aspdac 2024: 478-483 [doi]

Reinforcing the Connection between Analog Design and EDA (Invited Paper)Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath 0001, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar. aspdac 2024: 665-670 [doi]

MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACsYishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. tcad, 43(12):4740-4752, December 2024. [doi]

Hardware Acceleration of Inference on Dynamic GNNsSudipta Mondal, Sachin S. Sapatnekar. islped 2024: 1-6 [doi]

Stress-based Electromigration Modeling in IC Design: Moving from Theory to PracticeSusann Rothe, Jens Lienig, Sachin S. Sapatnekar. smacd 2024: 1-4 [doi]

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear GradientsArvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar. tcad, 43(12):4373-4385, December 2024. [doi]

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSIChetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria. hpca 2024: 671-685 [doi]

2023

Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM DesignVidya A. Chhabria, Sachin S. Sapatnekar. isqed 2023: 1-7 [doi]

Encoder-Decoder Networks for Analyzing Thermal and Power Delivery NetworksVidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar. todaes, 28(1), January 2023. [doi]

Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment InterconnectsNestor E. Evmorfopoulos, Mohammad Abdullah Al Shohel, Olympia Axelou, Pavlos Stoikos, Vidya A. Chhabria, Sachin S. Sapatnekar. ispd 2023: 115-123 [doi]

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal LayoutsRamprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar. todaes, 28(5), September 2023. [doi]

AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit CellsSumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun. date 2023: 1-6 [doi]

Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor ArraysNibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar. date 2023: 1-2 [doi]

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACsNibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar. tcad, 42(9):2782-2795, September 2023. [doi]

GNN-Based Hierarchical Annotation for Analog CircuitsKishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar. tcad, 42(9):2801-2814, September 2023. [doi]

Performance-driven Wire Sizing for Analog Integrated CircuitsYaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. todaes, 28(2), March 2023. [doi]

MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACsYishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. mlcad 2023: 1-6 [doi]

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET TechnologyMeghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani. essderc 2023: 69-72 [doi]

Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN AcceleratorsSusmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar. aspdac 2023: 475-482 [doi]

A Multicore GNN Training AcceleratorSudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar. islped 2023: 1-6 [doi]

A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific CachingSudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S 0001, Ziqing Zeng, Sachin S. Sapatnekar. tcad, 42(12):4844-4857, December 2023. [doi]

PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel ComputingSalonik Resch, Hüsrev Cilasun, Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Jian-Ping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. icrc 2023: 1-10 [doi]

On Endurance of Processing in (Nonvolatile) MemorySalonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. isca 2023: [doi]

The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open IssuesSachin S. Sapatnekar. ispd 2023: 101-102 [doi]

Frequency-Domain Transient Electromigration Analysis Using Circuit TheoryMohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar. iccad 2023: 1-8 [doi]

Energy-efficient Hardware Acceleration of Shallow Machine Learning ApplicationsZiqing Zeng, Sachin S. Sapatnekar. date 2023: 1-6 [doi]

2022

A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment InterconnectsOlympia Axelou, Nestor E. Evmorfopoulos, George Floros 0002, George Stamoulis, Sachin S. Sapatnekar. iccad 2022: 27 [doi]

From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing PredictionVidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar. mlcad 2022: 7-14 [doi]

OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network SynthesisVidya A. Chhabria, Sachin S. Sapatnekar. tcad, 41(10):3515-3528, 2022. [doi]

CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAMZamshed I. Chowdhury, S. Karen Khatamifard, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Meisam Razaviyayn, Jian-Ping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. tetc, 10(4):2055-2071, 2022. [doi]

A Charge Flow Formulation for Guiding Analog/Mixed-Signal PlacementTonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar. date 2022: 148-153 [doi]

Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML AlgorithmsHadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng. mlcad 2022: 119-126 [doi]

Common-Centroid Layout for Active and Passive Devices: A Review and the Road AheadNibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar. aspdac 2022: 114-121 [doi]

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor ArraysNibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar. date 2022: 166-171 [doi]

Are Analytical Techniques Worthwhile for Analog IC Placement?Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. date 2022: 154-159 [doi]

GNNIE: GNN inference engine with load-balancing and graph-specific cachingSudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar. dac 2022: 565-570 [doi]

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating ConditionsSalonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. tecs, 21(5), September 2022. [doi]

Analog/Mixed-Signal Layout Optimization using Optimal Well TapsRamprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar. ispd 2022: 159-166 [doi]

EDAML 2022 Invited Speaker 7: Analog and Digital Circuit and Layout Optimization using Machine LearningSachin S. Sapatnekar. ipps 2022: 1188 [doi]

2021

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder NetworksVidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar. aspdac 2021: 690-696 [doi]

BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based MethodologyVidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar. iccad 2021: 1-8 [doi]

MAVIREC: ML-Aided Vectored IR-Drop Estimation and ClassificationVidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar. date 2021: 1825-1828 [doi]

CAMeleon: Reconfigurable B(T)CAM in Computational RAMZamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jian-Ping Wang, Ulya R. Karpuzcu. glvlsi 2021: 57-63 [doi]

Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAMM. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu. seed 2021: 70-75 [doi]

Spiking Neural Networks in Spintronic Computational RAMM. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. taco, 18(4), 2021. [doi]

Aging of Current DACs and its Impact in Equalizer CircuitsTonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar. irps 2021: 1-6 [doi]

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning ModelsTonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar. aspdac 2021: 158-163 [doi]

Machine Learning Techniques in Analog Layout AutomationTonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar. ispd 2021: 71-72 [doi]

ALIGN: A System for Automating Analog LayoutTonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar. dt, 38(2):8-18, 2021. [doi]

VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware SynthesisHadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu 0003, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng. iccad 2021: 1-7 [doi]

A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient ControlLuke R. Everson, Sachin S. Sapatnekar, Chris H. Kim. jssc, 56(7):2281-2290, 2021. [doi]

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor SizingYaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. mlcad 2021: 1-6 [doi]

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer LearningJuzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen. iccad 2021: 1-9 [doi]

Analog Layout Generation using Optimized PrimitivesMeghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani. date 2021: 1234-1239 [doi]

DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning AcceleratorsSusmita Dey Manasi, Sachin S. Sapatnekar. aspdac 2021: 235-241 [doi]

Common-Centroid Layouts for Analog Circuits: Advantages and LimitationsArvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar. date 2021: 1224-1229 [doi]

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog CircuitsArvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar. iccad 2021: 1-9 [doi]

Analytical Modeling of Transient Electromigration Stress based on Boundary ReflectionsMohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar. iccad 2021: 1-8 [doi]

A New, Computationally Efficient "Blech Criterion" for Immortality in General InterconnectsMohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar. dac 2021: 913-918 [doi]

SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized ThresholdsFarhana Sharmin Snigdha, Susmita Dey Manasi, Jiang Hu, Sachin S. Sapatnekar. tcad, 40(7):1423-1436, 2021. [doi]

2020

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN TechniquesVidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu. aspdac 2020: 44-49 [doi]

CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAMHüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu. dac 2020: 1-6 [doi]

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk)Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar. iccad 2020: 1-2 [doi]

Adaptive-Length Coding of Image Data for Low-Cost Approximate StorageQianqian Fan, David J. Lilja, Sachin S. Sapatnekar. TC, 69(2):239-252, 2020. [doi]

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog CircuitsKishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar. date 2020: 55-60 [doi]

Learning from Experience: Applying ML to Analog Circuit DesignKishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar. ispd 2020: 55 [doi]

A general approach for identifying hierarchical symmetry constraints for analog circuit layoutKishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar. iccad 2020: 1-8 [doi]

Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin ChipsTengtao Li, Sachin S. Sapatnekar. isqed 2020: 237-242 [doi]

A Customized Graph Neural Network Model for Guiding Analog IC PlacementYaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. iccad 2020: 1-9 [doi]

Exploring a Machine Learning Approach to Performance Driven Analog IC PlacementYaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. isvlsi 2020: 24-29 [doi]

NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile ClientsSusmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar. tvlsi, 28(8):1844-1857, 2020. [doi]

MOUSE: Inference In Non-volatile Memory for Energy Harvesting ApplicationsSalonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Hüsrev Cilasun, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu. micro 2020: 400-414 [doi]

PIMBALL: Binary Neural Networks in Spintronic MemorySalonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. taco, 16(4), 2020. [doi]

2019

Impact of Self-heating on Performance and Reliability in FinFET and GAAFET DesignsVidya A. Chhabria, Sachin S. Sapatnekar. isqed 2019: 235-240 [doi]

Reliability Analysis of a Delay-Locked Loop Under HCI and BTI DegradationTonmoy Dhar, Sachin S. Sapatnekar. irps 2019: 1-6 [doi]

A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient ControlLuke R. Everson, Sachin S. Sapatnekar, Chris H. Kim. isscc 2019: 50-52 [doi]

Using DCT-based Approximate Communication to Improve MPI Performance in Parallel ClustersQianqian Fan, David J. Lilja, Sachin S. Sapatnekar. ipccc 2019: 1-10 [doi]

Improving QoS for Global Dual-Criticality Scheduling on MultiprocessorsLin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu. rtcsa 2019: 1-11 [doi]

ALIGN: Open-Source Analog Layout Automation from the Ground UpKishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar. dac 2019: 77 [doi]

Stress-Induced Performance Shifts in 3D DRAMsTengtao Li, Sachin S. Sapatnekar. todaes, 24(5), 2019. [doi]

Fast Mapping-Based High-Level Synthesis of Pipelined CircuitsChaofan Li, Sachin S. Sapatnekar, Jiang Hu. isqed 2019: 33-38 [doi]

Electromigration-Aware Interconnect DesignSachin S. Sapatnekar. ispd 2019: 83-90 [doi]

Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation PlatformMasoud Zabihi, Zhengyang Zhao, D. C. Mahendra, Zamshed I. Chowdhury, Salonik Resch, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar. isqed 2019: 52-57 [doi]

True In-memory Computing with the CRAM: From Technology to ApplicationsMasoud Zabihi, Zhengyang Zhao, Zamshed I. Chowdhury, Salonik Resch, Mahendra DC, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar. glvlsi 2019: 379 [doi]

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application MappingMasoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang 0006, Sachin S. Sapatnekar. TC, 68(8):1159-1173, 2019. [doi]

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