Janak H. Patel - researchr alias

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2005

Hardware Ef.cient LBISTWith Complementary WeightsLiyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng. iccd 2005: 479-484 [doi]

2004

2003

Application of Saluja-Karpovsky Compactors to Test Responses with Many UnknownsJanak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy. vts 2003: 107-112 [doi]

Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan ArchitectureManish Sharma, Janak H. Patel, Jeff Rearick. vts 2003: 15-21 [doi]

2002

An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based DesignsAmit R. Pandey, Janak H. Patel. date 2002: 368-375 [doi]

Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs Amit R. Pandey, Janak H. Patel. vts 2002: 9-15 [doi]

Finding a Small Set of Longest Testable Paths that Cover Every GateManish Sharma, Janak H. Patel. itc 2002: 974-982 [doi]

2001

2000

Test set compaction algorithms for combinational circuitsIlker Hamzaoglu, Janak H. Patel. tcad, 19(8):957-963, 2000. [doi]

Deterministic Test Pattern Generation Techniques for Sequential CircuitsIlker Hamzaoglu, Janak H. Patel. iccad 2000: 538-543

Reducing Test Application Time for Built-in-Self-Test Test Pattern GeneratorsIlker Hamzaoglu, Janak H. Patel. vts 2000: 369-376 [doi]

Peak power estimation of VLSI circuits: new peak power measuresMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. tvlsi, 8(4):435-439, 2000. [doi]

Dynamic state traversal for sequential circuit test generationMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. todaes, 5(3):548-565, 2000. [doi]

Enhanced delay defect coverage with path-segmentsManish Sharma, Janak H. Patel. itc 2000: 385-392

Bounding Circuit Delay by Testing a Very Small Subset of PathsManish Sharma, Janak H. Patel. vts 2000: 333-342 [doi]

1999

1998

Test set compaction algorithms for combinational circuitsIlker Hamzaoglu, Janak H. Patel. iccad 1998: 283-289 [doi]

New Techniques for Deterministic Test Pattern GenerationIlker Hamzaoglu, Janak H. Patel. vts 1998: 446-452 [doi]

Compact two-pattern test set generation for combinational and full scan circuitsIlker Hamzaoglu, Janak H. Patel. itc 1998: 944-953 [doi]

Application of genetically engineered finite-state-machine sequences to sequential circuit ATPGMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. tcad, 17(3):239-254, 1998. [doi]

Partial Scan Selection Based on Dynamic Reachability and Observability InformationMichael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel. vlsid 1998: 174-180 [doi]

High-level variable selection for partial-scan implementationFrank F. Hsu, Janak H. Patel. iccad 1998: 79-84 [doi]

High-Level Controllability and Observability Analysis for Test SynthesisFrank F. Hsu, Janak H. Patel. et, 13(2):93-103, 1998. [doi]

A Low-Overhead Coherence Solution for Multiprocessors with Private Cache MemoriesMark S. Papamarcos, Janak H. Patel. isca 1998: 284-290 [doi]

Improving the Throughput of a Pipeline by Insertion of DelaysJanak H. Patel, Edward S. Davidson. isca 1998: 132-137 [doi]

Retrospective: Improving the Throughput of a Pipeline by Insertion of DelaysJanak H. Patel. isca 1998: 5 [doi]

Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache MemoriesJanak H. Patel. isca 1998: 39-41 [doi]

Diagnostic Simulation of Sequential Circuits Using Fault SamplingSrikanth Venkataraman, W. Kent Fuchs, Janak H. Patel. vlsid 1998: 476-481 [doi]

1997

BART: A Bridging Fault Test Generation for Sequential CircuitsJames P. Cusey, Janak H. Patel. itc 1997: 838-847

Dynamic Fault Grouping for PROOFS: A Win for Large Sequential CircuitsCharles R. Graham, Elizabeth M. Rudnick, Janak H. Patel. vlsid 1997: 542-544 [doi]

Diagnostic Test Pattern Generation for Sequential CircuitsIsmed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs. vts 1997: 196-202 [doi]

Fast identification of untestable delay faults using implicationsKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. iccad 1997: 642-647 [doi]

Improving a nonenumerative method to estimate path delay fault coverageKeerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel. tcad, 16(7):759-762, 1997. [doi]

Effects of delay models on peak power estimation of VLSI sequential circuitsMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. iccad 1997: 45-51 [doi]

K2: an estimator for peak sustainable power of VLSI circuitsMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. islped 1997: 178-183 [doi]

Sequential circuit test generation using dynamic state traversalMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. date 1997: 22-28 [doi]

Fast Algorithms for Static Compaction of Sequential Circuit Test VectorsMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. vts 1997: 188-195 [doi]

Design for Testability Using State DistancesFrank F. Hsu, Janak H. Patel. et, 11(1):93-100, 1997. [doi]

SPITFIRE: scalable parallel algorithms for test set partitioned fault simulationDilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee. vts 1997: 274-281 [doi]

Asynchronous Parallel Algorithms for Test Set Partitioned Fault SimulationDilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel. pads 1997: 30-37 [doi]

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test GenerationDilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee. vlsid 1997: 475-481 [doi]

Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault SimulationElizabeth M. Rudnick, Janak H. Patel. vlsid 1997: 495-503 [doi]

A genetic algorithm framework for test generationElizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann. tcad, 16(9):1034-1044, 1997. [doi]

Putting the Squeeze on Test SequencesElizabeth M. Rudnick, Janak H. Patel. itc 1997: 723-732

Partial Scan beyond Cycle CuttingGurjeet S. Saund, Michael S. Hsiao, Janak H. Patel. ftcs 1997: 320-328

Algorithms to compute bridging fault coverage of ::::I::DDQ:::::: test setsPaul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel. todaes, 2(3):281-305, 1997. [doi]

Static logic implication with application to redundancy identificationJian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel. vts 1997: 288-295 [doi]

1996

A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient FaultsHungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi. TC, 45(11):1248-1256, 1996.

SIGMA: a simulator for segment delay faultsKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. iccad 1996: 502-508 [doi]

Segment delay faults: a new fault modelKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. vts 1996: 32-41 [doi]

Improving accuracy in path delay fault coverage estimationKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. vlsid 1996: 422-425 [doi]

Automatic test generation using genetically-engineered distinguishing sequencesMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. vts 1996: 216-223 [doi]

Testability Insertion in Behavioral DescriptionsFrank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel. isss 1996: 139-144 [doi]

Enhancing high-level control-flow for improved testabilityFrank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel. iccad 1996: 322-328 [doi]

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuitsTerry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel. vts 1996: 456-462 [doi]

Hierarchical test generation under architectural level functional constraintsJaushin Lee, Janak H. Patel. tcad, 15(9):1144-1151, 1996. [doi]

On Double Transition Faults as a Delay Fault ModelIrith Pomeranz, Sudhakar M. Reddy, Janak H. Patel. glvlsi 1996: 282-287 [doi]

On Potential Fault Detection in Sequential CircuitsElizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz. itc 1996: 142-149

Simulation-based techniques for dynamic test sequence compactionElizabeth M. Rudnick, Janak H. Patel. iccad 1996: 67-73 [doi]

Partial Scan Design Based on Circuit State InformationDong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel. dac 1996: 807-812 [doi]

A Global Algorithm for the Partial Scan Design Problem Using Circuit State InformationDong Xiang, Janak H. Patel. itc 1996: 548-557

1995

Cyclic stress tests for full scan circuitsVinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel. vts 1995: 89-94 [doi]

Overhead reduction techniques for hierarchical fault simulationEiji Harada, Janak H. Patel. ats 1995: 79-85 [doi]

A new architectural-level fault simulation using propagation prediction of grouped fault-effectsMichael S. Hsiao, Janak H. Patel. iccd 1995: 628 [doi]

A distance reduction approach to design for testabilityFrank F. Hsu, Janak H. Patel. vts 1995: 158-163 [doi]

A parallel algorithm for fault simulation based on PROOFS Steven Parkes, Prithviraj Banerjee, Janak H. Patel. iccd 1995: 616 [doi]

Sequential circuit testability enhancement using a nonscan approachElizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel. tvlsi, 3(2):333-338, 1995. [doi]

Combining Deterministic and Genetic Approaches for Sequential Circuit Test GenerationElizabeth M. Rudnick, Janak H. Patel. dac 1995: 183-188 [doi]

A genetic approach to test application time reduction for full scan and partial scan circuitsElizabeth M. Rudnick, Janak H. Patel. vlsid 1995: 288-293 [doi]

Fault Simulation of::::I::DDQ:::::: Tests for Bridging Faults in Sequential CircuitsPaul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel. ftcs 1995: 340-349

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact ListsSrikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel. dac 1995: 133-138 [doi]

1994

Microprocessor Testing: Which Technique is Best? (Panel)Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther. dac 1994: 294 [doi]

Hybrid Resource Management Algorithms for Multicomputer SystemsJeff Baxter, John W. C. Fu, Balkrishna Ramkumar, Janak H. Patel. ipps 1994: 482-489

Latch Design for Transient Pulse ToleranceHungse Cha, Janak H. Patel. iccd 1994: 385-388

Addressing design for testability at the architectural levelVivek Chickermane, Jaushin Lee, Janak H. Patel. tcad, 13(7):920-934, 1994. [doi]

Fast timing simulation of transient faults in digital circuitsAbhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel. iccad 1994: 719-722 [doi]

Trace Driven Simulation using Sampled TracesJohn W. C. Fu, Janak H. Patel. hicss 1994: 211-220

Architectural level test generation for microprocessorsJaushin Lee, Janak H. Patel. tcad, 13(10):1288-1300, 1994. [doi]

ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test GenerationSteven Parkes, Prithviraj Banerjee, Janak H. Patel. dac 1994: 717-721 [doi]

Sequential Circuit Test Generation in a Genetic Algorithm FrameworkElizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann. dac 1994: 698-704 [doi]

Application of Simple Genetic Algorithms to Sequential Circuit Test GenerationElizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel. eurodac 1994: 40-45

An observability enhancement approach for improved testability and at-speed testElizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel. tcad, 13(8):1051-1056, 1994. [doi]

1993

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