Georges G. E. Gielen - researchr alias

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2011

Circuits and systems engineering education through interdisciplinary team-based design projectsWim Dehaene, Georges G. E. Gielen, Geert Deconinck, Johan Driesen, Marc Moonen, Bart Nauwelaers, C. Van Hoof, Patrick Wambacq. iscas 2011: 1195-1198 [doi]

A novel operating-point driven method for the sizing of analog ICBo Liu, Murat Pak, Xuezhi Zheng, Georges G. E. Gielen. iscas 2011: 781-784 [doi]

Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence TechniquesBo Liu, Francisco V. Fernández, Georges G. E. Gielen. tcad, 30(6):793-805, 2011. [doi]

A 16-channel low-noise programmable system for the recording of neural signalsCarolina Mora Lopez, Dries Braeken, Carmen Bartic, Robert Puers, Georges G. E. Gielen, Wolfgang Eberle. iscas 2011: 1451-1454 [doi]

Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building BlocksTrent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen. tec, 15(4):557-570, 2011. [doi]

2010

Design automation towards reliable analog integrated circuitsGeorges G. E. Gielen, Elie Maricau, Peter H. N. De Wit. iccad 2010: 248-251 [doi]

An enhanced MOEA/D-DE and its application to multiobjective analog cell sizingBo Liu, Francisco V. Fernández, Qingfu Zhang, Murat Pak, Suha Sipahi, Georges G. E. Gielen. cec 2010: 1-7 [doi]

An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search techniqueBo Liu, Francisco V. Fernández, Georges G. E. Gielen. date 2010: 1106-1111 [doi]

Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexityElie Maricau, Georges G. E. Gielen. date 2010: 1094-1099 [doi]

Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability AnalysisElie Maricau, Georges G. E. Gielen. tcad, 29(12):1884-1893, 2010. [doi]

A 0.5 V-1.4 V supply-independent frequency-based analog-to-digital converter with fast start-up time for wireless sensor networksWouter Volkaerts, Bart Marien, Hans Danneels, Valentijn De Smedt, Patrick Reynaert, Wim Dehaene, Georges G. E. Gielen. iscas 2010: 3096-3099 [doi]

Efficient simulation model for DAC dynamic propertiesPieter De Wit, Georges G. E. Gielen. iscas 2010: 2896-2899 [doi]

2009

Health-care electronics The market, the challenges, the progressWolfgang Eberle, Ashwin S. Mecheri, Thi Kim Thoa Nguyen, Georges G. E. Gielen, Raymond Campagnolo, Alison Burdett, Chris Toumazou, Bart Volckaerts. date 2009: 1030-1034 [doi]

Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOSGeorges G. E. Gielen. ddecs 2009: 1 [doi]

A design methodology for fully reconfigurable Delta-Sigma data convertersYi Ke, Jan Craninckx, Georges G. E. Gielen. date 2009: 1379-1384 [doi]

A 3-tier UWB-based indoor localization system for ultra-low-power sensor networksZheng Li, Wim Dehaene, Georges G. E. Gielen. TWC, 8(6):2813-2818, 2009. [doi]

A memetic approach to the automatic design of high-performance analog integrated circuitsBo Liu, Francisco V. Fernández, Georges G. E. Gielen, R. Castro-López, Elisenda Roca. todaes, 14(3), 2009. [doi]

Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentionsBo Liu, Francisco V. Fernández, Georges G. E. Gielen. cec 2009: 622-629 [doi]

Efficient reliability simulation of analog ICs including variability and time-varying stressElie Maricau, Georges G. E. Gielen. date 2009: 1238-1241 [doi]

A methodology for measuring transistor ageing effects towards accurate reliability simulationElie Maricau, Georges G. E. Gielen. iolts 2009: 21-26 [doi]

ANTIGONE: Top-down creation of analog-to-digital converter architecturesEwout Martens, Georges G. E. Gielen. integration, 42(1):10-23, 2009. [doi]

Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural HomotopyTrent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen. tcad, 28(9):1281-1294, 2009. [doi]

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural HomotopyTrent McConaghy, Georges G. E. Gielen. tcad, 28(11):1627-1640, 2009. [doi]

Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic ProgrammingTrent McConaghy, Georges G. E. Gielen. tcad, 28(8):1162-1175, 2009. [doi]

Massively multi-topology sizing of analog integrated circuitsPieter Palmers, Trent McConaghy, Michiel Steyaert, Georges G. E. Gielen. date 2009: 706-711 [doi]

Prediction of Non-uniform Sampling Distortion Due to Substrate Noise Coupling in Regenerative ComparatorsA. Stefanou, Georges G. E. Gielen. iscas 2009: 968-971 [doi]

Guess, solder, measure, repeat: how do I get my mixed-signal chip right?Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O Leary, Sandeep Tare, Warren Wong. dac 2009: 520-521 [doi]

2008

From Transistor to PLL - Analogue Design and EDA MethodsDavid Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury. date 2008: [doi]

A low-power mixing DAC IR-UWB-receiverHans Danneels, Marian Verhelst, Pieter Palmers, Wim Vereecken, Bruno Boury, Wim Dehaene, Michiel Steyaert, Georges G. E. Gielen. iscas 2008: 2697-2700 [doi]

ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology SynthesisPeng Gao, Trent McConaghy, Georges G. E. Gielen. ices 2008: 11-21 [doi]

Importance sampled circuit learning ensembles for robust analog IC designPeng Gao, Trent McConaghy, Georges G. E. Gielen. iccad 2008: 396-399 [doi]

Emerging Yield and Reliability Challenges in Nanometer CMOS TechnologiesGeorges G. E. Gielen, P. De Wit, E. Maricau, J. Loeckx, J. Martin-Martinez, Ben Kaczer, Guido Groeseneken, R. Rodríguez, M. Nafría. date 2008: 1322-1327 [doi]

Analysis of quantization effects on high-order function neural networksMinghu Jiang, Georges G. E. Gielen. apin, 28(1):51-67, 2008. [doi]

An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applicationsElie Maricau, P. De Wit, Georges G. E. Gielen. mr, 48(8-9):1576-1580, 2008. [doi]

Classification of analog synthesis tools based on their architecture selection mechanismsEwout Martens, Georges G. E. Gielen. integration, 41(2):238-252, 2008. [doi]

Automated extraction of expert knowledge in analog topology selection and sizingTrent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert. iccad 2008: 392-395 [doi]

2007

Scalable Gate-Level Models for Power and Timing AnalysisMustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. iscas 2007: 2938-2941 [doi]

An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selectionTom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen. date 2007: 81-86 [doi]

2007 International Conference on Computer-Aided Design (ICCAD 07), November 5-8, 2007, San Jose, CA, USAGeorges G. E. Gielen, editor, IEEE, 2007.

Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologiesGeorges G. E. Gielen. aspdac 2007: 432-437 [doi]

Future trends for wireless communication frontends in nanometer CMOSGeorges G. E. Gielen. glvlsi 2007: 600-605 [doi]

Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference]Georges G. E. Gielen, Donatella Sciuto. tcad, 26(3):405-407, 2007. [doi]

Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit TopologiesTrent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert. dac 2007: 944-947 [doi]

2006

SWAN: high-level simulation methodology for digital substrate noise generationMustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. tvlsi, 14(1):23-33, 2006. [doi]

Clock-skew-optimization methodology for substrate-noise reduction with supply-current foldingMustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. tcad, 25(6):1146-1154, 2006. [doi]

Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standardTom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen. dac 2006: 25-30 [doi]

Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006Georges G. E. Gielen, editor, European Design and Automation Association, Leuven, Belgium, 2006.

Proceedings of the Conference on Design, Automation and Test in Europe: Designers Forum, DATE 2006, Munich, Germany, March 6-10, 2006Georges G. E. Gielen, editor, European Design and Automation Association, Leuven, Belgium, 2006.

Assessment of parameter extraction methods for integrated inductor design and model validationAlkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs. iscas 2006: [doi]

Top-down heterogeneous synthesis of analog and mixed-signal systemsEwout Martens, Georges G. E. Gielen. date 2006: 275-280 [doi]

Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral modelsEwout Martens, Georges G. E. Gielen. tcad, 25(5):924-932, 2006. [doi]

A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceiversEwout Martens, Georges G. E. Gielen. iscas 2006: [doi]

Generic Behavioral Modeling of Analog and Mixed-Signal SystemsEwout Martens, Georges G. E. Gielen. fdl 2006: 15-23 [doi]

Automation in mixed-signal design: challenges and solutions in the wake of the nano eraTrent McConaghy, Georges G. E. Gielen. iccad 2006: 461-463 [doi]

Canonical form functions as a simple means for genetic programming to evolve human-interpretable functionsTrent McConaghy, Georges G. E. Gielen. gecco 2006: 855-862 [doi]

Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit intronsTrent McConaghy, Georges G. E. Gielen. date 2006: 269-274 [doi]

2005

Digital ground bounce reduction by supply current shaping and clock frequency ModulationMustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. tcad, 24(1):65-76, 2005. [doi]

Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance HypersurfacesTom Eeckelaert, Trent McConaghy, Georges G. E. Gielen. date 2005: 1070-1075 [doi]

Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich. date 2005: 36-42 [doi]

Performance space modeling for hierarchical synthesis of analog integrated circuitsGeorges G. E. Gielen, Trent McConaghy, Tom Eeckelaert. dac 2005: 881-886 [doi]

Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial SeriesEwout Martens, Georges G. E. Gielen. date 2005: 120-125 [doi]

Behavioral modeling and simulation of weakly nonlinear sampled-data systemsEwout Martens, Georges G. E. Gielen. iscas 2005: 2247-2250 [doi]

CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic ProgrammingTrent McConaghy, Tom Eeckelaert, Georges G. E. Gielen. date 2005: 1082-1087 [doi]

IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programmingTrent McConaghy, Georges G. E. Gielen. iscas 2005: 5170-5173 [doi]

Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimizationTrent McConaghy, Georges G. E. Gielen. iscas 2005: 1298-1301 [doi]

A CAD Platform for Sensor Interfaces in Low-Power ApplicationsDidier Van Reeth, Georges G. E. Gielen. patmos 2005: 374-381 [doi]

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagramsHuiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen. aspdac 2005: 230-235 [doi]

2004

Digital Ground Bounce Reduction by Phase Modulation of the ClockMustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. date 2004: 88-93 [doi]

Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A convertersTao Chen, Georges G. E. Gielen. iscas 2004: 293-296

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effectsGeert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. dac 2004: 854-859 [doi]

An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulatorsGeorges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels. tcad, 23(3):389-399, 2004. [doi]

Backpropagation Analysis of the Limited Precision on High-Order Function Neural NetworksMinghu Jiang, Georges G. E. Gielen. isnn 2004: 305-310 [doi]

A Bayesian Classifier by Using the Adaptive Construct Algorithm of the RBF NetworksMinghu Jiang, Dafan Liu, Beixing Deng, Georges G. E. Gielen. isnn 2004: 876-881 [doi]

Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector MachinesTholom Kiely, Georges G. E. Gielen. date 2004: 448-453 [doi]

A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level DesignEwout Martens, Georges G. E. Gielen. date 2004: 436-441 [doi]

High-level modeling of continuous-time Delta-Sigma A/D-converters using formal modelsEwout Martens, Georges G. E. Gielen. aspdac 2004: 51-56 [doi]

Knowledge- and optimization-based design of RF power amplifiersJoão Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert. iscas 2004: 629-632 [doi]

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance ModelsMukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen. date 2004: 604-609 [doi]

2003

Analysis of the dynamic SFDR property of high-accuracy current-steering D/A convertersTao Chen, Georges G. E. Gielen. iscas 2003: 973-976 [doi]

Simulation-based generation of posynomial performance models for the sizing of analog integrated circuitsWalter Daems, Georges G. E. Gielen, Willy M. C. Sansen. tcad, 22(5):517-534, 2003. [doi]

Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN ReceiverWolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. date 2003: 10642-10649 [doi]

Generalized Posynomial Performance ModelingTom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen. date 2003: 10250-10255 [doi]

A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulatorsKenneth Francken, Georges G. E. Gielen. tcad, 22(8):1049-1061, 2003. [doi]

Fast Learning Algorithms for Feedforward Neural NetworksMinghu Jiang, Georges G. E. Gielen, Bo Zhang, Zhensheng Luo. apin, 18(1):37-54, 2003.

The Effects of Quantization on Multi-Layer Feedforward Neural NetworksMinghu Jiang, Georges G. E. Gielen. ijprai, 17(4):637-661, 2003. [doi]

Guest editorialH. Alan Mantooth, Georges G. E. Gielen. tcad, 22(2):121-123, 2003. [doi]

A Model of Computation for Continuous-Time ?-? ModulatorsEwout Martens, Georges G. E. Gielen. date 2003: 10162-10167 [doi]

HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated CircuitsBart De Smedt, Georges G. E. Gielen. date 2003: 10256-10263 [doi]

WATSON: design space boundary exploration and model generation for analog and RFIC designBart De Smedt, Georges G. E. Gielen. tcad, 22(2):213-224, 2003. [doi]

A Generalized Method for Computing Oscillator Phase Noise SpectraPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. iccad 2003: 247-250 [doi]

Behavioral modeling of (coupled) harmonic oscillatorsPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. tcad, 22(8):1017-1026, 2003. [doi]

Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency DetectorsPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. date 2003: 10238-10243 [doi]

Figure of Merit Based Selection of A/D ConvertersMartin Vogels, Georges G. E. Gielen. date 2003: 11090-11091 [doi]

Architectural selection of A/D convertersMartin Vogels, Georges G. E. Gielen. dac 2003: 974-977 [doi]

2002

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transientsMustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen. dac 2002: 399-404 [doi]

Optimal design of delta-sigma ADCs by design space explorationOvidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen. dac 2002: 443-448 [doi]

A behavioral simulation tool for continuous-time delta sigma modulatorsKenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen. iccad 2002: 234-239 [doi]

Systematic Design of a 200 Ms/S 8-bit Interpolating A/D ConverterJan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen. date 2002: 357-361 [doi]

Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converterJan Vandenbussche, K. Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen. dac 2002: 449-454 [doi]

Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integrationMartin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen. iscas 2002: 237-240 [doi]

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