Sachin S. Sapatnekar - researchr alias

researchr

You are not signed in
Sign in
Sign up

2011

2010

Incremental solution of power grids using random walksBaktash Boghrati, Sachin S. Sapatnekar. aspdac 2010: 757-762 [doi]

Scalable methods for the analysis and optimization of gate oxide breakdownJianxin Fang, Sachin S. Sapatnekar. isqed 2010: 638-645 [doi]

Current source modeling in the presence of body biasSaket Gupta, Sachin S. Sapatnekar. aspdac 2010: 199-204 [doi]

Capturing Post-Silicon Variations Using a Representative Critical PathQunzeng Liu, Sachin S. Sapatnekar. tcad, 29(2):211-222, 2010. [doi]

Fast Poisson solvers for thermal analysisHaifeng Qian, Sachin S. Sapatnekar. iccad 2010: 698-702 [doi]

EditorialSachin S. Sapatnekar. tcad, 29(1):1, 2010. [doi]

Adding a new dimension to physical designSachin S. Sapatnekar. ispd 2010: 55 [doi]

Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010Sachin S. Sapatnekar, editor, ACM, 2010.

Dummy fill optimization for enhanced manufacturabilityYaoguang Wei, Sachin S. Sapatnekar. ispd 2010: 97-104 [doi]

Physical design techniques for optimizing RTA-induced variationsYaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar. aspdac 2010: 745-750 [doi]

Application-specific 3D Network-on-Chip design using simulated allocationPingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar. aspdac 2010: 517-522 [doi]

2009

Adaptive techniques for overcoming performance degradation due to aging in digital circuitsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. aspdac 2009: 284-289 [doi]

Synthesizing a representative critical path for post-silicon delay predictionQunzeng Liu, Sachin S. Sapatnekar. ispd 2009: 183-190 [doi]

A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process VariationsQunzeng Liu, Sachin S. Sapatnekar. tcad, 28(8):1201-1212, 2009. [doi]

Fast and Accurate Statistical Criticality Computation Under Process VariationsHushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan. tcad, 28(3):350-363, 2009. [doi]

Addressing thermal and power delivery bottlenecks in 3D circuitsSachin S. Sapatnekar. aspdac 2009: 423-428 [doi]

Technical perspective - Where the chips may fallSachin S. Sapatnekar. CACM, 52(8):94, 2009. [doi]

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing BiochipsPing-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang. tcad, 28(9):1295-1306, 2009. [doi]

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid IntegrityPingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar. dt, 26(5):15-25, 2009. [doi]

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitorsPingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar. aspdac 2009: 179-184 [doi]

2008

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization PropertyJie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim. tvlsi, 16(2):206-209, 2008. [doi]

Technology Mapping Using Logical Effort for Solving the Load-Distribution ProblemShrirang K. Karandikar, Sachin S. Sapatnekar. tcad, 27(1):45-58, 2008. [doi]

Stack Sizing for Optimal Current Drivability in Subthreshold CircuitsJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim. tvlsi, 16(5):598-602, 2008. [doi]

Body Bias Voltage Computations for Process and Temperature CompensationSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. tvlsi, 16(3):249-262, 2008. [doi]

A framework for block-based timing sensitivity analysisSanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar. dac 2008: 688-693 [doi]

Stochastic Preconditioning for Diagonally Dominant MatricesHaifeng Qian, Sachin S. Sapatnekar. siamsc, 30(3):1178-1204, 2008. [doi]

Reinventing EDA with manycore processorsSachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou. dac 2008: 126-127 [doi]

Building your yield of dreamsSachin S. Sapatnekar. dt, 25(2):194-195, 2008. [doi]

Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]Sachin S. Sapatnekar. dt, 25(5):496-497, 2008. [doi]

A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter VariationsJaskirat Singh, Sachin S. Sapatnekar. tcad, 27(1):160-173, 2008. [doi]

A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial CorrelationJaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar. tcad, 27(2):295-308, 2008. [doi]

A progressive-ILP based routing algorithm for cross-referencing biochipsPing-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang. dac 2008: 284-289 [doi]

Automated module assignment in stacked-Vdd designs for high-efficiency power deliveryYong Zhan, Sachin S. Sapatnekar. jetc, 4(4), 2008. [doi]

Thermally Aware DesignYong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar. fteda, 2(3):255-370, 2008. [doi]

Buffering global interconnects in structured ASIC designTianpei Zhang, Sachin S. Sapatnekar. integration, 41(2):171-182, 2008. [doi]

2007

A general model for performance optimization of sequential systemsDmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar. iccad 2007: 362-369 [doi]

Editorial to special issue DAC 2006Krishnendu Chakrabarty, Sachin S. Sapatnekar. jetc, 3(3), 2007. [doi]

Prediction of leakage power under process uncertaintiesHongliang Chang, Sachin S. Sapatnekar. todaes, 12(2), 2007. [doi]

In Memoriam: Margarida F. JacomeGustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar. tcad, 26(9):1549-1550, 2007. [doi]

Placement of 3D ICs with Thermal and Interlayer Via ConsiderationsBrent Goplen, Sachin S. Sapatnekar. dac 2007: 626-631 [doi]

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage ShiftJie Gu, Sachin S. Sapatnekar, Chris H. Kim. dac 2007: 87-92 [doi]

NBTI-Aware Synthesis of Digital CircuitsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. dac 2007: 370-375 [doi]

Probabilistic Congestion Prediction with Partial BlockagesZhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi. isqed 2007: 841-846 [doi]

Confidence Scalable Post-Silicon Statistical Delay Prediction under Process VariationsQunzeng Liu, Sachin S. Sapatnekar. dac 2007: 497-502 [doi]

DAG based library-free technology mappingFelipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. glvlsi 2007: 293-298 [doi]

Clustering based pruning for statistical criticality computation under process variationsHushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan. iccad 2007: 340-343 [doi]

DAC HighlightsSachin S. Sapatnekar, Leon Stok. dt, 24(5):502-504, 2007. [doi]

Book Review: An Assay of BiochipsSachin S. Sapatnekar. dt, 24(4):402-403, 2007. [doi]

Computer-aided design of 3d integrated circuitsSachin S. Sapatnekar. glvlsi 2007: 317 [doi]

Module assignment for pin-limited designs under the stacked-Vdd paradigmYong Zhan, Tianpei Zhang, Sachin S. Sapatnekar. iccad 2007: 656-659 [doi]

High-Efficiency Green Function-Based Thermal Simulation AlgorithmsYong Zhan, Sachin S. Sapatnekar. tcad, 26(9):1661-1675, 2007. [doi]

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global RoutingTianpei Zhang, Sachin S. Sapatnekar. tvlsi, 15(6):624-636, 2007. [doi]

2006

Accurate estimation of global buffer delay within a floorplanCharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze. tcad, 25(6):1140-1145, 2006. [doi]

Tutorial II: Variability and Its Impact on DesignKeith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar. isqed 2006: 5 [doi]

Fast disjoint transistor networks from BDDsLeomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. sbcci 2006: 137-142 [doi]

Placement of Thermal Vias in 3-D ICs Using Various Thermal ObjectivesBrent Goplen, Sachin S. Sapatnekar. tcad, 25(4):692-709, 2006. [doi]

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizingJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim. dac 2006: 425-428 [doi]

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systemsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. aspdac 2006: 559-564 [doi]

An analytical model for negative bias temperature instabilitySanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. iccad 2006: 493-496 [doi]

Impact of NBTI on SRAM Read Stability and Design for ReliabilitySanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. isqed 2006: 210-218 [doi]

Comparing simulation techniques for microarchitecture-aware floorplanningVidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar. ispass 2006: 80-88 [doi]

Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysisVidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar. islped 2006: 298-303 [doi]

DAC HighlightsSachin S. Sapatnekar, Grant Martin. dt, 23(3):182-184, 2006. [doi]

Book Reviews: Plumbing the Depths of LeakageSachin S. Sapatnekar. dt, 23(4):318-319, 2006. [doi]

Technology Mapping Algorithm Targeting Routing Congestion Under Delay ConstraintsRupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar. tcad, 25(4):625-636, 2006. [doi]

Statistical timing analysis with correlated non-gaussian parameters using independent component analysisJaskirat Singh, Sachin S. Sapatnekar. dac 2006: 155-160 [doi]

Partition-Based Algorithm for Power Grid Design Using LocalityJaskirat Singh, Sachin S. Sapatnekar. tcad, 25(4):664-677, 2006. [doi]

A fixed-die floorplanning algorithm using an analytical approachYong Zhan, Yan Feng, Sachin S. Sapatnekar. aspdac 2006: 771-776 [doi]

Electrothermal analysis and optimization techniques for nanoscale integrated circuitsYong Zhan, Brent Goplen, Sachin S. Sapatnekar. aspdac 2006: 219-222 [doi]

Temperature-aware routing in 3D ICsTianpei Zhang, Yong Zhan, Sachin S. Sapatnekar. aspdac 2006: 309-314 [doi]

2005

Placement and Routing in 3D Integrated CircuitsCristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar. dt, 22(6):520-531, 2005. [doi]

Net weighting to reduce repeater counts during placementBrent Goplen, Prashant Saxena, Sachin S. Sapatnekar. dac 2005: 503-508 [doi]

Thermal via placement in 3D ICsBrent Goplen, Sachin S. Sapatnekar. ispd 2005: 167-174 [doi]

Fast estimation of area-delay trade-offs in circuit sizingShrirang K. Karandikar, Sachin S. Sapatnekar. iscas 2005: 3575-3578 [doi]

Fast comparisons of circuit implementationsShrirang K. Karandikar, Sachin S. Sapatnekar. tvlsi, 13(12):1329-1339, 2005. [doi]

A new approach to the use of satisfiability in false path detectionFelipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. glvlsi 2005: 308-311 [doi]

Designing optimized pipelined global interconnects: algorithms and methodology impactVidyasagar Nookala, Sachin S. Sapatnekar. iscas 2005: 608-611 [doi]

Microarchitecture-aware floorplanning using a statistical design of experiments approachVidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar. dac 2005: 579-584 [doi]

A hybrid linear equation solver and its application in quadratic placementHaifeng Qian, Sachin S. Sapatnekar. iccad 2005: 905-909

Guest Editors Introduction: New Dimensions in 3D IntegrationSachin S. Sapatnekar, Kevin J. Nowka. dt, 22(6):496-497, 2005. [doi]

High-Speed Interconnect Technology: On-Chip and Off-ChipSachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani. vlsid 2005: 7 [doi]

Empowering the designerSachin S. Sapatnekar. dt, 22(3):280-281, 2005. [doi]

An EDA compendiumSachin S. Sapatnekar. dt, 22(1):74-75, 2005. [doi]

Designing Vary Good CircuitrySachin S. Sapatnekar. dt, 22(6):596-597, 2005. [doi]

Exact lower bound for the number of switches in series to implement a combinational logic cellFelipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. iccd 2005: 357-362 [doi]

A predictive distributed congestion metric with application to technology mappingRupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang. tcad, 24(5):696-710, 2005. [doi]

BDD decomposition for delay oriented pass transistor logic synthesisRupesh S. Shelar, Sachin S. Sapatnekar. tvlsi, 13(8):957-970, 2005. [doi]

An efficient technology mapping algorithm targeting routing congestion under delay constraintsRupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar. ispd 2005: 137-144 [doi]

Congestion-aware topology optimization of structured power/ground networksJaskirat Singh, Sachin S. Sapatnekar. tcad, 24(5):683-695, 2005. [doi]

Robust gate sizing by geometric programmingJaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar. dac 2005: 315-320 [doi]

A fast algorithm for power grid designJaskirat Singh, Sachin S. Sapatnekar. ispd 2005: 70-77 [doi]

Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuitsAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar. tvlsi, 13(12):1362-1375, 2005. [doi]

Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-upYong Zhan, Sachin S. Sapatnekar. aspdac 2005: 87-92 [doi]

A high efficiency full-chip thermal simulation algorithmYong Zhan, Sachin S. Sapatnekar. iccad 2005: 635-638

Buffering global interconnects in structured ASIC designTianpei Zhang, Sachin S. Sapatnekar. aspdac 2005: 23-26 [doi]

PreviousNext