Youngsoo Shin - researchr alias

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2011

2010

Lookup Table-Based Adaptive Body biasing of Multiple Macros for Process Variation Compensation and Low LeakageByunghee Choi, Youngsoo Shin. jcsc, 19(7):1449-1464, 2010. [doi]

Pulsed-latch aware placement for timing-integrity optimizationYi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang. dac 2010: 280-285 [doi]

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOSHyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin. tvlsi, 18(3):505-509, 2010. [doi]

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed LatchesHyein Lee, Seungwhun Paik, Youngsoo Shin. tcad, 29(3):355-366, 2010. [doi]

Wakeup synthesis and its buffered tree construction for power gating circuit designsSeungwhun Paik, Sangmin Kim, Youngsoo Shin. islped 2010: 413-418 [doi]

Statistical time borrowing for pulsed-latch circuit designsSeungwhun Paik, Lee-eun Yu, Youngsoo Shin. aspdac 2010: 675-680 [doi]

HLS-l: A High-Level Synthesis Framework for Latch-Based ArchitecturesSeungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin. tcad, 29(5):657-670, 2010. [doi]

Synthesis and implementation of active mode power gating circuitsJun Seomun, Insup Shin, Youngsoo Shin. dac 2010: 487-492 [doi]

Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical designJun Seomun, Seungwhun Paik, Youngsoo Shin. aspdac 2010: 581-586 [doi]

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designsYoungsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai. todaes, 15(4), 2010. [doi]

2009

ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated CircuitsEunjoo Choi, Changsik Shin, Youngsoo Shin. tcad, 28(3):451-456, 2009. [doi]

Minimizing leakage power of sequential circuits through mixed-::::V::t:::::: flip-flops and multi-::::V::t:::::: combinational gatesJaehyun Kim, Chungki Oh, Youngsoo Shin. todaes, 15(1), 2009. [doi]

Frequency and yield optimization using power gates in power-constrained designsNam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae-Hee Han, Ken Choi, Youngsoo Shin. islped 2009: 121-126 [doi]

Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuitsSeonggwan Lee, Seungwhun Paik, Youngsoo Shin. iccad 2009: 375-380 [doi]

HLS-l: High-level synthesis of high performance latch-based circuitsSeungwhun Paik, Insup Shin, Youngsoo Shin. date 2009: 1112-1117 [doi]

Register allocation for high-level synthesis using dual supply voltagesInsup Shin, Seungwhun Paik, Youngsoo Shin. dac 2009: 937-942 [doi]

Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell ElementsYoungsoo Shin, Seungwhun Paik, Hyung-Ock Kim. tcad, 28(3):327-339, 2009. [doi]

2008

3-D thermal simulation with dynamic power profilesEunjoo Choi, Youngsoo Shin. iscas 2008: 2765-2768 [doi]

Power-gating-aware high-level synthesisEunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin. islped 2008: 39-44 [doi]

Statistical mixed Vt allocation of body-biased circuits for reduced leakage variationJinseob Jeong, Seungwhun Paik, Youngsoo Shin. aspdac 2008: 629-634 [doi]

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuitsHyein Lee, Seungwhun Paik, Youngsoo Shin. iccad 2008: 224-229 [doi]

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elementsSeungwhun Paik, Youngsoo Shin. dac 2008: 600-605 [doi]

Skewed Flip-Flop and Mixed-V::t:: Gates for Minimizing Leakage in Sequential CircuitsJun Seomun, Jae-Hyun Kim, Youngsoo Shin. tcad, 27(11):1956-1968, 2008. [doi]

2007

Lookup Table-Based Adaptive Body Biasing of Multiple MacrosByunghee Choi, Youngsoo Shin. isqed 2007: 533-538 [doi]

Minimizing leakage power in sequential circuits by using mixed ::::V::t:::::: flip-flopsJaehyun Kim, Youngsoo Shin. iccad 2007: 797-802 [doi]

Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential CircuitsJun Seomun, Jaehyun Kim, Youngsoo Shin. dac 2007: 103-106 [doi]

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS CircuitsYoungsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi. aspdac 2007: 654-659 [doi]

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS CircuitsYoungsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi. tvlsi, 15(7):758-766, 2007. [doi]

Cell-Based Semicustom Design of Zigzag Power Gating CircuitsYoungsoo Shin, Hyung-Ock Kim. isqed 2007: 527-532 [doi]

2006

Analysis and optimization of gate leakage current of power gating circuitsHyung-Ock Kim, Youngsoo Shin. aspdac 2006: 565-569 [doi]

Physical design methodology of power gating circuits for standard-cell-based designHyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo. dac 2006: 109-112 [doi]

Power Analysis of VLSI Interconnect with RLC Tree Models and Model ReductionYoungsoo Shin, Junghyup Lee. jcsc, 15(3):399-408, 2006. [doi]

2005

2004

Architecting voltage islands in core-based system-on-a-chip designsJingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu. islped 2004: 180-185 [doi]

2003

SEAS: a system for early analysis of SoCsReinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal. codes 2003: 150-155 [doi]

2002

Early analysis tools for system-on-a-chip designJohn A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin. ibmrd, 46(6):691-708, 2002. [doi]

2001

2000

Narrow bus encoding for low power systemsYoungsoo Shin, Kiyoung Choi. aspdac 2000: 217-220 [doi]

Power Optimization of Real-Time Embedded Systems on Variable Speed ProcessorsYoungsoo Shin, Kiyoung Choi, Takayasu Sakurai. iccad 2000: 365-368

Schedulability-driven performance analysis of multiple mode embedded real-time systemsYoungsoo Shin, Daehong Kim, Kiyoung Choi. dac 2000: 495-500 [doi]

1999

Power Conscious Fixed Priority Scheduling for Hard Real-Time SystemsYoungsoo Shin, Kiyoung Choi. dac 1999: 134-139 [doi]

1998

Rate Assignment for Embedded Reactive Real-Time SystemsYoungsoo Shin, Kiyoung Choi. euromicro 1998: 10237 [doi]

Partial bus-invert coding for power optimization of system level busYoungsoo Shin, Soo-Ik Chae, Kiyoung Choi. islped 1998: 127-129 [doi]

1997

Enforcing Schedulability of Multi-Task Systems by Hardware-Software CodesignYoungsoo Shin, Kiyoung Choi. codes 1997: 3-8 [doi]

1996

Software synthesis through task decomposition by dependency analysisYoungsoo Shin, Kiyoung Choi. iccad 1996: 98-104 [doi]

1995

Efficient Prototyping System Based on Incremental Design and Module-by-Module VerificationYongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi. iscas 1995: 924-927

An integrated hardware-software cosimulation environment for heterogeneous systems prototypingYongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha. aspdac 1995: [doi]