Hans-Joachim Wunderlich - researchr alias

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2011

Efficient multi-level fault simulation of HW/SW systems for structural faultsRafal Baranowski, Stefano Di Carlo, Nadereh Hatami, Michael E. Imhof, Michael A. Kochte, Paolo Prinetto, Hans-Joachim Wunderlich, Christian G. Zoellin. chinaf, 54(9):1784-1796, 2011. [doi]

Fail-safety in core-based system designRafal Baranowski, Hans-Joachim Wunderlich. iolts 2011: 276-281 [doi]

Structural In-Field Diagnosis for Random Logic CircuitsAlejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein. ets 2011: 111-116 [doi]

Structural Test for Graceful Degradation of NoC SwitchesAtefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich. ets 2011: 183-188 [doi]

Variation-aware fault modelingFabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich. chinaf, 54(9):1813-1826, 2011. [doi]

Soft error correction in embedded storage elementsMichael E. Imhof, Hans-Joachim Wunderlich. iolts 2011: 169-174 [doi]

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architecturesMichael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich. islped 2010: 33-38 [doi]

Towards Variation-Aware Test MethodsIlia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell. ets 2011: 219-225 [doi]

2010

Algorithm-based fault tolerance for many-core architecturesClaus Braun, Hans-Joachim Wunderlich. ets 2010: 253 [doi]

Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen (Algorithm-based Fault-Tolerance on Many-Core Architectures)Claus Braun, Hans-Joachim Wunderlich. it, 52(4):209-215, 2010. [doi]

BISD: Scan-based Built-In self-diagnosisMelanie Elm, Hans-Joachim Wunderlich. date 2010: 1243-1248 [doi]

On Determining the Real Output Xs by SAT-Based ReasoningMelanie Elm, Michael A. Kochte, Hans-Joachim Wunderlich. ats 2010: 39-44 [doi]

Variation-Aware Fault ModelingFabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich. ats 2010: 87-93 [doi]

Efficient fault simulation on many-core processorsMichael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin. dac 2010: 380-385 [doi]

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-LevelMichael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto. ats 2010: 3-8 [doi]

Efficient Concurrent Self-Test with Partially Specified PatternsMichael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich. et, 26(5):581-594, 2010. [doi]

Low-power test planning for arbitrary at-speed delay-test clock schemesChristian G. Zoellin, Hans-Joachim Wunderlich. vts 2010: 93-98 [doi]

2009

Restrict Encoding for Mixed-Mode BISTAbdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz. vts 2009: 179-184 [doi]

A diagnosis algorithm for extreme space compactionStefan Holst, Hans-Joachim Wunderlich. date 2009: 1355-1360 [doi]

Adaptive Debug and Diagnosis Without Fault DictionariesStefan Holst, Hans-Joachim Wunderlich. et, 25(4-5):259-268, 2009. [doi]

Test Encoding for Extreme Response CompactionMichael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich. ets 2009: 155-160 [doi]

Test exploration and validation using transaction level modelsMichael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto. date 2009: 1250-1253 [doi]

Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and OverheadMichael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich. ets 2009: 53-58 [doi]

Software-Based Hardware Fault Tolerance for Many-Core ArchitecturesHans-Joachim Wunderlich. dft 2009: 223-223 [doi]

2008

Signature Rollback - A Technique for Testing Robust CircuitsUranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich. vts 2008: 125-130 [doi]

Scan Chain Organization for Embedded DiagnosisMelanie Elm, Hans-Joachim Wunderlich. date 2008: 468-473 [doi]

Scan chain clustering for test power reductionMelanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding. dac 2008: 828-833 [doi]

Adaptive Debug and Diagnosis without Fault DictionariesStefan Holst, Hans-Joachim Wunderlich. ets 2008: 199-204 [doi]

Integrating Scan Design and Soft Error Correction in Low-Power ApplicationsMichael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin. iolts 2008: 59-64 [doi]

Test Set Stripping Limiting the Maximum Number of Specified BitsMichael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich. delta 2008: 581-586 [doi]

Selective Hardening in Early Design StepsChristian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker. ets 2008: 185-190 [doi]

2007

Synthesis of irregular combinational functions with large don t care setsValentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers. glvlsi 2007: 287-292 [doi]

Deterministic logic BIST for transition fault testingValentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers. iet-cdt, 1(3):180-186, 2007. [doi]

A Refined Electrical Model for Particle Strikes and its Impact on SEU PredictionSybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube. dft 2007: 50-58 [doi]

Adaptive Debug and Diagnosis without Fault DictionariesStefan Holst, Hans-Joachim Wunderlich. emnets 2007: 7-12 [doi]

Scan Test Planning for Power ReductionMichael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra. dac 2007: 521-526 [doi]

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and RepairPhilipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich. ddecs 2007: 185-190

An Integrated Built-In Test and Repair Approach for Memories with 2D RedundancyPhilipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich. emnets 2007: 91-96 [doi]

2006

Some Common Aspects of Design Validation, Debug and DiagnosisTalal Arnaout, Gunter Bartsch, Hans-Joachim Wunderlich. delta 2006: 3-10 [doi]

Structural-Based Power-Aware Assignment of Don t Cares for Peak Power Reduction during Scan TestingNabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich. vlsi 2006: 403-408 [doi]

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems)Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich. it, 48(5):304, 2006. [doi]

Deterministic Logic BIST for Transition Fault TestingValentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers. emnets 2006: 123-130 [doi]

X-masking during logic BIST and its impact on defect coverageYuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke. tvlsi, 14(2):193-202, 2006. [doi]

Software-based self-test of processors under power constraintsJun Zhou, Hans-Joachim Wunderlich. date 2006: 430-435 [doi]

2005

2004

Reliability Considerations forMechatronic Systems on the Basis of a State ModelTalal Arnaout, Peter Göhner, Hans-Joachim Wunderlich, Eduard Zimmer. arcs 2004: 106-112

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in EuropMarie-Lise Flottes, Yves Bertrand, L. Balado, E. Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich. delta 2004: 135-139 [doi]

Efficient Pattern Mapping for Deterministic Logic BISTValentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers. itc 2003: 48-56 [doi]

X-Masking During Logic BIST and Its Impact on Defect CoverageYuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker. itc 2003: 442-451 [doi]

Impact of Test Point Insertion on Silicon Area and Timing during LayoutHarald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich. date 2004: 810-815 [doi]

Panel SummariesHans-Joachim Wunderlich, Sandeep K. Shukla. dt, 21(1):65-66, 2004.

2003

Test Engineering Education in Europe: the EuNICE-Test ProjectYves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden. mse 2003: 85-86 [doi]

IntroductionShishpal Rawat, Hans-Joachim Wunderlich. todaes, 8(4):397-398, 2003. [doi]

2002

Reusing Scan Chains for Test Pattern DecompressionRainer Dorsch, Hans-Joachim Wunderlich. et, 18(2):231-240, 2002. [doi]

Adapting an SoC to ATE Concurrent Test CapabilitiesRainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer. itc 2002: 1169-1175 [doi]

High Defect Coverage with Low-Power Test Sequences in a BIST EnvironmentPatrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich. dt, 19(5):44-52, 2002. [doi]

Efficient Online and Offline Testing of Embedded DRAMsSybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik. TC, 51(7):801-809, 2002. [doi]

Two-Dimensional Test Data Compression for Scan-Based Deterministic BISTHuaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich. et, 18(2):159-170, 2002. [doi]

A Mixed-Mode BIST Scheme Based on Folding CompressionHuaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich. jcst, 17(2):203-212, 2002. [doi]

2001

On applying the set covering model to reseedingSilvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich. date 2001: 156-161 [doi]

Tailoring ATPG for embedded testingRainer Dorsch, Hans-Joachim Wunderlich. itc 2001: 530-537

Using mission logic for embedded testingRainer Dorsch, Hans-Joachim Wunderlich. date 2001: 805 [doi]

A Modified Clock Scheme for a Low Power BIST Test Pattern GeneratorPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich. vts 2001: 306-311 [doi]

A Mixed Mode BIST Scheme Based on Reseeding of Folding CountersSybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich. et, 17(3-4):341-349, 2001. [doi]

Circuit partitioning for efficient logic BIST synthesisA. Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich. date 2001: 86-91 [doi]

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testabilityMichael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich. itc 2001: 461-469

Application of Deterministic Logic BIST on Industrial CircuitsGundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich. et, 17(3-4):351-362, 2001. [doi]

Two-dimensional test data compression for scan-based deterministic BISTHuaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich. itc 2001: 894-902

2000

1999

1998

Accumulator based deterministic BISTRainer Dorsch, Hans-Joachim Wunderlich. itc 1998: 412-421 [doi]

Mixed-Mode BIST Using Embedded ProcessorsSybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig. et, 12(1-2):127-138, 1998. [doi]

Synthesizing Fast, Online-Testable Control UnitsSybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig. dt, 15(4):36-41, 1998. [doi]

Fast Self-Recovering ControllersAndre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich. vts 1998: 296-302 [doi]

Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BISTMadhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich. ats 1998: 492-499 [doi]

Deterministic BIST with multiple scan chainsGundolf Kiefer, Hans-Joachim Wunderlich. itc 1998: 1057-1064 [doi]

Hardware-optimal test register insertionAlbrecht P. Stroele, Hans-Joachim Wunderlich. tcad, 17(6):531-539, 1998. [doi]

BIST for systems-on-a-chipHans-Joachim Wunderlich. integration, 26(1-2):55-78, 1998. [doi]

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMsVyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich. date 1998: 173-179 [doi]

1997

1996

Mixed-Mode BIST Using Embedded ProcessorsSybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig. itc 1996: 195-204

Bit-flipping BISTHans-Joachim Wunderlich, Gundolf Kiefer. iccad 1996: 337-343 [doi]

1995

Pattern generation for a deterministic BIST schemeSybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich. iccad 1995: 88-94 [doi]

Test register insertion with minimum hardware costAlbrecht P. Stroele, Hans-Joachim Wunderlich. iccad 1995: 95-101 [doi]

1994

Configuring Flip-Flops to BIST RegistersAlbrecht P. Stroele, Hans-Joachim Wunderlich. itc 1994: 939-948

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