Abstract is missing.
- Seeing Chip Testability Through a Systems Person s EyesDavid W. Yen. 12 [doi]
- Test Challenges of Nanometer TechnologyJanusz Rajski. 13-22 [doi]
- EEPROM Memory: Threshold Voltage Built In Self DiagnosisJean Michel Portal, Hassen Aziza, Didier Née. 23-28 [doi]
- Fault Pattern Oriented Defect Diagnosis for MemoriesChih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong Tzer Yang. 29-38 [doi]
- Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable MemorieDerek Wright, Manoj Sachdev. 39-47 [doi]
- Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in ProductionMasashi Shimanouchi. 48-57 [doi]
- Effects of Deterministic Jitter in a Cable on Jitter Tolerance MeasurementsTakahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha. 58-66 [doi]
- CMOS Built-In Test Architecture for High-Speed Jitter MeasurementHenry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz. 67-76 [doi]
- Relating Yield Models to Burn-In Fall-Out in TimeThomas S. Barnett, Adit D. Singh. 77-84 [doi]
- Testing DSM ASIC With Static, /DeltaIDDQ, And Dynamic Test Suite: Implementation And ResultsYoshihito Nishizaki, Osamu Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura. 85-94 [doi]
- Burn-in Temperature Projections for Deep Sub-micron TechnologiesOleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins. 95-104 [doi]
- Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring DieHaihua Yan, Adit D. Singh. 105-111 [doi]
- HyAC: A Hybrid Structural SAT Based ATPG for CrosstalkXiaoliang Bai, Sujit Dey, Angela Krstic. 112-121 [doi]
- Path Delay Test Generation for Domino Logic Circuits in the Presence of CrosstalkRahul Kundu, R. D. (Shawn) Blanton. 122-130 [doi]
- Fault Injection for Verifying Testability at the VHDL LevelS. R. Seward, Parag K. Lala. 131-137 [doi]
- Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar DesignsMiroslav N. Velev. 138-147 [doi]
- Coverage-Directed Management and Optimization of Random Functional VerificationAmir Hekmatpour, James Coulter. 148-155 [doi]
- The PXI Modular Instrumentation ArchitectureEric Starkloff, Tim Fountain, Garth Black. 156-165 [doi]
- Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level ProberJ. S. Davis, David C. Keezer, O. Liboiron-Ladouceur, K. Bergman. 166-174 [doi]
- RIC/DICMOS-- Multi-channel CMOS FormatterAhmed Rashid Syed. 175-184 [doi]
- Data flow within an open architecture testerMaurizio Gavardoni. 185-190 [doi]
- A Production-Oriented Multiplexing System for Testing above 2.5 GbpsDavid C. Keezer, Dany Minier, Marie-Christine Caron. 191-200 [doi]
- A New Methodology For ADC Test Flow OptimizationSerge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell. 201-209 [doi]
- Method of reducing contactor effect when testing high-precision ADCsGwenolé Maugard, Carsten Wegener, Tom O Dwyer, Michael Peter Kennedy. 210-217 [doi]
- Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear InputsLe Jin, Kumar L. Parthasarathy, Turker Kuyel, Degang Chen, Randall L. Geiger. 218-227 [doi]
- Testing High Frequency ADCs and DACs with a Low Frequency Analog BusStephen K. Sunter. 228-235 [doi]
- Optical and Electrical Testing of Latchup in I/O Interface CircuitsFranco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia Sanda. 236-245 [doi]
- Designed -in-diagnostics: A new optical methodKeneth R. Wilsher. 246-253 [doi]
- Fault Localization using Time Resolved Photon Emission and STIL WaveformsRomain Desplats, Felix Beaudoin, Philippe Perdu, Nagamani Nataraj, Ted Lundquist, Ketan Shah. 254-263 [doi]
- Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA)Jeremy A. Rowlette, Travis M. Eiles. 264-273 [doi]
- Fault Collapsing via Functional DominanceVishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre. 274-280 [doi]
- Efficient Sequential ATPG Based on Partitioned Finite-State-Machine TraversalQingwei Wu, Michael S. Hsiao. 281-289 [doi]
- Efficient Sequential ATPG for Functional RTL CircuitsLiang Zhang, Indradeep Ghosh, Michael S. Hsiao. 290-298 [doi]
- Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random SimulationMahesh A. Iyer. 299-308 [doi]
- Progressive Bridge IdentificationThomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton. 309-318 [doi]
- Statistical Diagnosis for Intermittent Scan Chain Hold-Time FaultYu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung. 319-328 [doi]
- An Efficient and Effective Methodology on the Multiple Fault DiagnosisZhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski. 329-338 [doi]
- Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and MethodologiesAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak. 339-348 [doi]
- A New Maximal Diagnosis Algorithm for Bus-structured SystemsYongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang. 349-357 [doi]
- A Comprehensive Approach to Assessing and Analyzing 1149.1 Test LogicKevin Melocco, Hina Arora, Paul Setlak, Gary Kunselman, Shazia Mardhani. 358-367 [doi]
- Constructive Pattern Generation Heuristic for Meeting SSO LimitsKendrick Baker. 368 [doi]
- Optimal Interconnect ATPG Under a Ground-Bounce ConstraintHenk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen. 369-378 [doi]
- Exploiting Programmable BIST For The Diagnosis of Embedded Memory CoresDavide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante. 379-385 [doi]
- BIST for Deep Submicron ASIC Memories with High Performance ApplicationTheo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai. 386-392 [doi]
- A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D RedundancyJin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow. 393-402 [doi]
- Automatic Diagnostic Program Generation for Mixed Signal Load BoardKranthi K. Pinjala, Bruce C. Kim, Pramodchandran N. Variyam. 403-409 [doi]
- A High Precision IDDQ Measurement System With Improved Dynamic Load RegulationNobuhiro Sato, Yoshihiro Hashimoto. 410-414 [doi]
- Area and Time Co-Optimization for System-on-a-Chip based on Consecutive TestabilityTomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara. 415-422 [doi]
- Extraction Error Diagnosis and Correction in High-Performance DesignsYu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris. 423-430 [doi]
- Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor CoresNektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian. 431-440 [doi]
- Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan ChainsIrith Pomeranz. 441-450 [doi]
- A Hybrid Coding Strategy For Optimized Test Data CompressionArmin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand. 451-459 [doi]
- Deterministic BIST Based on a Reconfigurable Interconnection NetworkLei Li, Krishnendu Chakrabarty. 460-469 [doi]
- Double-Tree Scan: A Novel Low-Power Scan-Path ArchitectureBhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang. 470-479 [doi]
- A New Approach for Low Power Scan TestingTakaki Yoshida, Masafumi Watari. 480-487 [doi]
- Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing ConstraintYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. 488-493 [doi]
- IEEE 1149.6 - A Practical PerspectiveBill Eklow, Carl Barnhart, Mike Ricchetti, Terry Borroz. 494-502 [doi]
- Key Impediments to DFT-Focused Test and How to Overcome ThemKenneth E. Posse, Geir Eide. 503-511 [doi]
- Challenges in Low Cost Test Approach for ARM9TM Core Based Mixed-Signal SoC DragonBallTM-MX1George Bao. 512-519 [doi]
- Ultra Low Cost Linear TestingMichael A. Jones. 520-527 [doi]
- A Generic Test Path and DUT Model for DataCom ATEJie Sun, Mike Li. 528-536 [doi]
- Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus MeasurementsThomas P. Warwick. 537-544 [doi]
- Test Vector Generation Based on Correlation Model for Ratio-IddqXiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota. 545-554 [doi]
- Hysteresis of Intrinsic IDDQ CurrentsYukio Okuda, Nobuyuki Furukawa. 555-564 [doi]
- Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQChris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning. 565-573 [doi]
- A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan DesignsSeongmoon Wang, Srimat T. Chakradhar. 574-583 [doi]
- High Quality ATPG for Delay DefectsPuneet Gupta, Michael S. Hsiao. 584-591 [doi]
- An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational CircuitWangqi Qiu, D. M. H. Walker. 592-601 [doi]
- Modeling Scan Chain Modifications For Scan-in Test Power MinimizationOzgur Sinanoglu, Alex Orailoglu. 602-611 [doi]
- Power-aware NoC Reuse on the Testing of Core-based SystemsÉrika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski. 612-621 [doi]
- On Reducing Wrapper Boundary Register Cells in Modular SOC TestingQiang Xu, Nicola Nicolici. 622-631 [doi]
- First IC Validation of IEEE Std. 1149.6Suzette Vandivier, Mark Wahl, Jeff Rearick. 632-639 [doi]
- Design and Implementation of IEEE 1149.6Ivan Duzevik. 640 [doi]
- Adapting JTAG for AC Interconnect TestingLee Whetsel. 641-650 [doi]
- VDD Ramp Testing for RF CircuitsJosé Pineda de Gyvez, Guido Gronthoud, Rashid Amine. 651-658 [doi]
- Building An RF Source For Low Cost Testers Using An ADPLL Controlled By Texas Instruments Digital Signal Processor (DSP) TMS320C5402Iboun Taimiya Sylla. 659-664 [doi]
- Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral ModelsAchintya Halder, Soumendu Bhattacharya, Abhijit Chatterjee. 665-673 [doi]
- Introduction to Applications and Industries for Microelectromechanical Systems (MEMS)Jeremy A. Walraven. 674-680 [doi]
- MEMS Design And VerificationTamal Mukherjee. 681-690 [doi]
- MEMS FabricationGary K. Fedder. 691-698 [doi]
- Effectiveness Improvement of ECR TestsWanli Jiang, Erik Peterson, Bob Robotka. 699-708 [doi]
- Impedance Profile of a Commercial Power Grid and Test SystemDhruva Acharyya, Jim Plusquellic. 709-718 [doi]
- CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production TestingB. Alorda, B. Bloechel, Ali Keshavarzi, Jaume Segura. 719-726 [doi]
- X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST ArchitecturePeter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin. 727-736 [doi]
- On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST FailuresRamesh C. Tekumalla. 737-744 [doi]
- Convolutional Compaction of Test ResponsesJanusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy. 745-754 [doi]
- Latch Divergency In Microprocessor Failure AnalysisPeter Dahlgren, Paul Dickinson, Ishwar Parulkar. 755-763 [doi]
- Testability Features of the Alpha 21364 MicroprocessorScott Erlanger, Dilip K. Bhavsar, Richard A. Davies. 764-772 [doi]
- The Testability Features of The ARM1026EJ Microprocessor CoreTeresa L. McLaurin, Frank Frederick, Rich Slobodnik. 773-782 [doi]
- TRIBuTETM Board and Platform Test Methodology: Intel s Next-Generation Test and Validation Methodology for PlatformsJay J. Nejedlo. 783 [doi]
- IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IOJay J. Nejedlo. 784 [doi]
- An extension to JTAG for at-speed debug on a systemLeon van de Logt, Frank van der Heyden, Tom Waayers. 785-792 [doi]
- XML And Java For Open ATE Programming EnvironmentA. T. Sivaram, Daniel Fan, Jon Pryce. 793-801 [doi]
- Data Critically Estimation In Software ApplicationsAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri. 802-810 [doi]
- Case Study - Using STIL as Test Pattern LanguageDaniel Fan, Steve Roehling, Rusty Carruth. 811-817 [doi]
- Outlier Detection for DPPM ReductionPaul Buxton, Paul Tabor. 818-827 [doi]
- Failure Mechanisms in MEMSJeremy A. Walraven. 828-833 [doi]
- Tools and Techniques for Failure Analysis and Qualification of MEMSJeremy A. Walraven. 834-842 [doi]
- MEMS Manufacturing Testing: An Accelerometer Case StudyTheresa Maudie, Alex Hardt, Rick Nielsen, Dennis Stanerson, Ron Bieschke, Mike Miller. 843-849 [doi]
- Future Challenges for MEMS Failure AnalysisJeremy A. Walraven. 850-855 [doi]
- Deformations of IC Structure in Test and Yield LearningWojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey. 856-865 [doi]
- Detection of Resistive Shorts in Deep Sub-micron TechnologiesBram Kruseman, Stefan van den Oetelaar. 866-875 [doi]
- Analyzing the Effectiveness of Multiple-Detect Test SetsR. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah. 876-885 [doi]
- Novel Transient Fault Hardened Static LatchMartin Omaña, Daniele Rossi, Cecilia Metra. 886-892 [doi]
- Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic CircuitsKartik Mohanram, Nur A. Touba. 893-901 [doi]
- Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath SynthesisKaijie Wu, Ramesh Karri. 902-911 [doi]
- On-line Detection of Faults in Carry-Select AddersB. Kiran Kumar, Parag K. Lala. 912-918 [doi]
- Parity-Based Concurrent Error Detection in Symmetric Block CiphersRamesh Karri, Grigori Kuznetsov, Michael Gössel. 919-926 [doi]
- Hybrid Multisite Testing at ManufacturingHamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi, Farzin Karimi. 927-936 [doi]
- Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic Systems Assembly Using Real-Coded Genetic AlgorithmsZhen Shi, Peter Sandborn. 937-946 [doi]
- Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test StrategyBurnell G. West. 947-951 [doi]
- Agent Based DBIST/DBISR And Its Web/Wireless ManagementLiviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto. 952-960 [doi]
- Instruction Based BIST for Board/System Level Test of External Memories and InternconnectsOlivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan. 961-970 [doi]
- Test-Based Model Generation For Legacy SystemsHardi Hungar, Tiziana Margaria, Bernhard Steffen. 971-980 [doi]
- Evolution of IEEE 1149.1 Addressable Shadow Protocol DevicesRakesh N. Joshi, Kenneth L. Williams, Lee Whetsel. 981-987 [doi]
- Overview of the IEEE P1500 StandardFrancisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur. 988-997 [doi]
- The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT DataMichael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod. 998-1007 [doi]
- Low Contact-Force Fritting Probe Card Using Buckling MicrocantileversKenichi Kataoka, Toshihiro Itoh, Tadatomo Suga. 1008-1013 [doi]
- Elimination of Traditional Functional Testing of Interface Timings at IntelMike Tripp, T. M. Mak, Anne Meixner. 1014-1022 [doi]
- A BIST Solution for The Test of I/O SpeedCheng Jia, Linda S. Milor. 1023-1030 [doi]
- Impact of Multiple-Detect Test Patterns on Product QualityBrady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski. 1031-1040 [doi]
- Using Logic Models To Predict The Detection Behavior Of Statistical Timing DefectsLi-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir. 1041-1050 [doi]
- Simulating Resistive Bridging and Stuck-At FaultsPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker. 1051-1059 [doi]
- On-chip Compression of Output Responses with Unknown Values Using LFSR ReseedingMasao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu. 1060-1068 [doi]
- ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data VolumeHarald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink. 1069-1078 [doi]
- On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain DesignsHuaxing Tang, Sudhakar M. Reddy, Irith Pomeranz. 1079-1088 [doi]
- Structural Delay Testing of Latch-based High-speed Pipelines with Time BorrowingKun Young Chung, Sandeep K. Gupta. 1089-1097 [doi]
- A Case Study of IR-Drop in Structured At-Speed TestingJayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger. 1098-1104 [doi]
- DFFT : Design For Functional TestabilityHaluk Konuk, Leon Xiao. 1105-1114 [doi]
- Backplane Test Bus Applications For IEEE STD 1149.1Clayton Gibbs. 1115-1128 [doi]
- Infrastructure IP for Back-End Yield ImprovementL. Forli, Jean Michel Portal, Didier Née, Bertrand Borot. 1129-1134 [doi]
- A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test SchedulingErik Larsson, Zebo Peng. 1135-1144 [doi]
- An improved Test Control Architecture and Test Control Expansion for Core-Based System ChipsTom Waayers. 1145-1154 [doi]
- Analog Circuit Test using Transfer Function Coe .cient EstimatesZhen Guo, Jacob Savir. 1155-1163 [doi]
- Concurrent Error Detection in Linear Analog Circuits Using State EstimationHaralampos-G. D. Stratigopoulos, Yiorgos Makris. 1164-1173 [doi]
- Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and ResultsRamakrishna Voorakaranam, Randy Newby, Sasikumar Cherubal, Bob Cometta, Thomas Kuehl, David M. Majernik, Abhijit Chatterjee. 1174-1181 [doi]
- Towards Structural Testing of Superconductor ElectronicsArun A. Joseph, Hans G. Kerkhoff. 1182-1191 [doi]
- Testing of Droplet-Based Microelectrofluidic SystemsFei Su, Sule Ozev, Krishnendu Chakrabarty. 1192-1200 [doi]
- Defect Tolerance at the End of the RoadmapMahim Mishra, Seth Copen Goldstein. 1201-1211 [doi]
- Industrial Experience with Adoption of EDT for Low-Cost Test without ConcessionsFrank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski. 1211-1220 [doi]
- Circular BIST testing the digital logic within a high speed SerdesGraham Hetherington, Richard Simpson. 1221-1228 [doi]
- H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural TestingDavid M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish. 1229-1238 [doi]
- FPGA Interconnect Delay Fault TestingErik Chmelar. 1239-1247 [doi]
- Application of Built in Self-Test for Interconnect Testing of FPGAsDereck A. Fernandes, Ian G. Harris. 1248-1257 [doi]
- BIST for Xilinx 4000 and Spartan Series FPGAs: A Case StudyCharles E. Stroud, Keshia N. Leach, Thomas A. Slaughter. 1258-1267 [doi]
- Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?Kenneth P. Parker. 1268-1276 [doi]
- Board Test Coverage: The Value of Prediction and How to Compare NumbersWouter Rijckaert, Frans de Jong. 1277 [doi]
- IEEE P1581: To Live or Let die?Frans de Jong, Leon van de Logt. 1278 [doi]
- Panel Synopsis - How (In)Adequate is One Time Testing?Rubin A. Parekhji. 1279 [doi]
- Should Nanometer Circuits be Periodically Tested in the Field?Adit D. Singh. 1280 [doi]
- The Increasing Importance of On-line Testing to Ensure High-Reliability ProductsPhil Nigh. 1281 [doi]
- Reliability Threats in VDSM - Shortcomings in Conventional Test and Fault-Tolerance AlternativesMichael Nicolaidis. 1282 [doi]
- How (In)Adequate is One-time TestingPeter Ehlig. 1283 [doi]
- Yield Threats and Inadequacy of One-time TestYervant Zorian. 1284 [doi]
- Open Microphone - My DFT is better than yours ..Geir Eide, Kenneth E. Posse. 1285 [doi]
- RF Test 101: Defining the Problem, Finding SolutionsMustapha Slamani. 1286 [doi]
- Seamless Research Between Academia And Industry To Facilitate Test Of Integrated High-Speed Wireless Systems: Is This An Illusion?Abhijit Chatterjee. 1287 [doi]
- Improving Wireless Product Testing via University and Industry CollaborationWilliam R. Eisenstadt. 1288 [doi]
- Improving Wireless Product Testing: An Opportunity for University and Industry CollaboratioJim Paviol. 1289 [doi]
- The Confluence of Manufacturing Test and Design ValidationIan G. Harris. 1290 [doi]
- The Confluence of Manufacturing Test and Design ValidationFranco Fummi. 1291 [doi]
- Design Verification Problems: Test To The Rescue?Prab Varma. 1292 [doi]
- The Confluence of Manufacturing Test and Design ValidationKwang-Ting Cheng. 1293 [doi]
- PXI: A Solution For Board Functional Test?Jim Webster. 1294 [doi]
- Selecting PXI Architecture for Board (System) Functional TestEric L. Smitt. 1295 [doi]
- PXI - A New Architecture for Many Testing RequirementsBob Stasonis. 1296 [doi]
- Future ATE: Perspectives & RequirementsFidel Muradali. 1297 [doi]
- ATE-Customer Perspectives & Requirements PanelDonald L. Wheater. 1298 [doi]
- Test Outsourcing - A Subcontract Manufacturer s PerspectiveJohn Roberts. 1299 [doi]
- Future ATE: Perspectives & RequirementsLee Y. Song. 1300 [doi]
- Future ATE for System on a Chip... Some PerspectivesTom Newsom. 1301 [doi]
- Diagnosis in Modern Design - Just the Tip of the IcebergFidel Muradali. 1302 [doi]
- Debug and Diagnosis in the Age of System-on-a-ChipRobert F. Molyneaux. 1303 [doi]
- Diagnosis in Modern Design to Volume - The Tip of the IcebergWilliam V. Huott. 1304 [doi]
- Silicon DiagnosisWu-Tung Cheng. 1305 [doi]
- Production Test Challenges And Possible Solutions For Multiple GB/s ICsMike Li. 1306 [doi]
- Open Architecture ATE and 250 Consecutive UIsTakahiro J. Yamaguchi. 1307 [doi]
- Cost Containment for High-Volume Test of Multi-GB/s PortsJohn C. Johnson. 1308 [doi]
- Requirements, Challenges, And Solutions For Testing Multiple GB/s ICs In ProductionMike Li. 1309 [doi]
- Managing the Multi-Gbit/s Test ChallengesUlrich Schoettmer, Bernd Laquai. 1310 [doi]
- Multi-GB/s IC Test Challenges and SolutionsBurnell G. West. 1311 [doi]
- Jitter Test in Production for High Speed Serial LinksYi Cai. 1312 [doi]
- DFM: The Real 90nm HurdleRobert C. Aitken. 1313 [doi]
- Silicon IP And Successful DFMRobert C. Aitken. 1314 [doi]
- DFM - An Industry Paradigm ShiftCliff Ma. 1315 [doi]
- Design for Manufacturability - or the meaning of subtle Stefan Eichenberger. 1316 [doi]
- DFM - A Fabless PerspectiveJitendra Khare. 1317 [doi]
- Testing 3G-controlled systems: time to rejoice or time to feel pain?Tapio Koivukangas. 1318 [doi]
- Next-Generation Devices and Networks Bring Opportunities and ChallengesAntti Sivula. 1319 [doi]
- Self-Testing and Self-Healing via Mobile AgentsAlfredo Benso. 1320 [doi]
- Standards Based Wireless Device TestingJohn D. Bowne. 1321 [doi]
- Testing 3G-controlled systems: time to rejoice or time to feel pain?Moray Rumney. 1322 [doi]
- Testing Challenges of Future Wireless WorldTapio Koivukangas. 1323
- Board Life-Cycle Testing For Effective NPI Management of Wireless ProductsTimo Piironen. 1324 [doi]
- Architecting Millisecond Test Solutions for Wireless Phone RFIC sJohn Ferrario, Randy Wolf, Steve Moss. 1325 [doi]
- Elimination of Traditional Functional Testing of Interface Timings at IntelMike Tripp, T. M. Mak, Anne Meixner. 1448-1456 [doi]