Massimo Alioto - researchr profile publications

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Publications with a 'Massimo Alioto' as author, editor, or advisor:

Evaluation of power consumption in adiabatic circuitsM. Alioto, G. Palumbo. iscas 2000: 629-632 [doi]
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipherMassimo Alioto, Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti. mixdes 2014: 241-246 [doi]
Analysis of layout density in FinFET standard cells and impact of fin technologyMassimo Alioto. iscas 2010: 3204-3207 [doi]
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) SystemsMassimo Alioto. tvlsi, 28(1):1-2, 2020. [doi]
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic CircuitsMassimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti. tcas, 57-I(2):355-367, 2010. [doi]
Design strategies of cascaded CML gatesMassimo Alioto, Gaetano Palumbo. tcas, 53-II(2):85-89, 2006. [doi]
Comparative analysis of the robustness of master-slave flip-flops against variationsMassimo Alioto, Elio Consoli, Gaetano Palumbo. icecsys 2015: 117-120 [doi]
Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design EffortOrazio Aiello, Paolo Crovetti, Ayushparth Sharma, Massimo Alioto. icecsys 2019: 715-718 [doi]
Opening of the 2021 Editorial Year - Overture for a New Year of ChangeMassimo Alioto. tvlsi, 29(1):1-2, 2021. [doi]
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scalingFelice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jerome Mitard, Liesbeth Witters, Thomas Y. Hoffmann. iscas 2011: 2249-2252 [doi]
Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed VisionAnastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto. access, 8:18951-18961, 2020. [doi]
Delay Variability Due to Supply Variations in Transmission-Gate Full AddersMassimo Alioto, Gaetano Palumbo. iscas 2007: 3732-3735 [doi]
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency DividersMassimo Alioto, Rosario Mita, Gaetano Palumbo. tcas, 53-II(11):1165-1169, 2006. [doi]
Second Quarter of the 2021 Editorial Year - A Year in CrescendoMassimo Alioto. tvlsi, 29(5):815-842, 2021. [doi]
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper)Massimo Alioto, Sachin Taneja. cicc 2019: 1-8 [doi]
Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power- Performance Adaptation Beyond Voltage ScalingMassimo Alioto. socc 2019: 1-3 [doi]
Comparative soft error evaluation of layout cells in FinFET technologyLaurent Artola, Guillaume Hubert, Massimo Alioto. mr, 54(9-10):2300-2305, 2014. [doi]
EditorialKrishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai Helen Li, Huawei Li, Patrick Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Mohammad Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Miroslav N. Velev, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson. tvlsi, 25(1):1-20, 2017. [doi]
Last-Round and Joint First/Last-Round Power Analysis Attacks on PRESENTQiang Fang, Massimo Alioto. asianhost 2021: 1-6 [doi]
A novel back-biasing low-leakage technique for FinFET forced stacksDavide Baccarin, David Esseni, Massimo Alioto. iscas 2011: 2079-2082 [doi]
Automated Design of Reconfigurable Microarchitectures for Accelerators under Wide-Voltage ScalingSaurabh Jain, Longyang Lin, Massimo Alioto. iscas 2020: 1 [doi]
Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated DesignHui Zhang, Longyang Lin, Qiang Fang, Udara Samurdhi Harshanga Kalingage, Massimo Alioto. vlsit 2023: 1-2 [doi]
DET FF topologies: A detailed investigation in the energy-delay-area domainMassimo Alioto, Elio Consoli, Gaetano Palumbo. iscas 2011: 563-566 [doi]
2 Area in 180nmLuigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto. vlsic 2020: 1-2 [doi]
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active TransitionsMassimo Alioto, Elio Consoli, Jan M. Rabaey. jssc, 48(8):1921-1932, 2013. [doi]
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A TutorialMassimo Alioto. tcas, 59-I(1):3-29, 2012. [doi]
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital CircuitsMassimo Alioto, Elio Consoli, Gaetano Palumbo. iscas 2009: 3150-3153 [doi]
Analysis of the impact of process variations on static logic circuits versus fan-inMassimo Alioto, Gaetano Palumbo, Melita Pennisi. icecsys 2008: 137-140 [doi]
Efficient Post-Processing Module for a Chaos-based Random Bit GeneratorTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. icecsys 2006: 1224-1227 [doi]
Explicit energy evaluation in RLC tree circuits with ramp inputsMassimo Alioto, Massimo Poli, Gaetano Palumbo. iscas 2008: 2865-2868 [doi]
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 MetricMassimo Alioto, Giuseppe Scotti, Alessandro Trifiletti. tcas, 64(8):2073-2085, 2017. [doi]
Analysis and design of digital PRNGS based on the discretized sawtooth mapMassimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli. icecsys 2003: 427-430 [doi]
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional GatesMassimo Alioto, Gaetano Palumbo. patmos 2000: 265-275 [doi]
The Internet of Things on Its Edge: Trends Toward Its Tipping PointMassimo Alioto, Mohsen Shahghasemi. cem, 7(1):77-87, 2018. [doi]
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus TechnologyMassimo Alioto, Gaetano Palumbo. iscas 2007: 2998-3001 [doi]
A technique to design high entropy chaos-based true random bit generatorsTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. iscas 2006: [doi]
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs - Toward a Smarter, Greener WorldMassimo Alioto. dt, 38(5):90-133, 2021. [doi]
Mixed Full Adder topologies for high-performance low-power arithmetic circuitsMassimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo. mj, 38(1):130-139, 2007. [doi]
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on TimingMassimo Alioto, Elio Consoli, Gaetano Palumbo. tcas, 62-I(8):2035-2043, 2015. [doi]
TempDiff: Temporal Difference-Based Feature Map-Level Sparsity Induction in CNNs with <4% Memory OverheadUdari De Alwis, Massimo Alioto. aicas 2021: 1-4 [doi]
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nmAnimesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto. cicc 2022: 1-2 [doi]
Project-Based Learning in Digital Fundamentals Course Using FPGAsDingjuan Chua, Jieyi Gao, Massimo Alioto, Yong Ping Xu, Sangit Sasidhar. mcs 2018: 1-5 [doi]
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ CircuitsRaffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto. tcas, 65-I(3):1086-1095, 2018. [doi]
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL CircuitsArmin Tajalli, Massimo Alioto, Yusuf Leblebici. tcas, 56-II(2):127-131, 2009. [doi]
A pW-Power Hz-Range Oscillator Operating With a 0.3-1.8-V Unregulated SupplyOrazio Aiello, Paolo Crovetti, Longyang Lin, Massimo Alioto. jssc, 54(5):1487-1496, 2019. [doi]
CML ring oscillators: oscillation frequencyMassimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo. iscas 2001: 112-115 [doi]
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computingMassimo Alioto. date 2017: 127-132 [doi]
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process VariationsMassimo Alioto, Simone Bongiovanni, Milena Djukanovic, Giuseppe Scotti, Alessandro Trifiletti. tcas, 61-I(2):429-442, 2014. [doi]
A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined EntropyTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. jcsc, 19(4):879-895, 2010. [doi]
Power-delay optimization in MCML tapered buffersMassimo Alioto, Gaetano Palumbo. iscas 2008: 141-144 [doi]
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nmSachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto. asscc 2017: 301-304 [doi]
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor NodesKarim Ali Ahmed, Hayate Okuhara, Massimo Alioto. isscc 2023: 102-103 [doi]
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFSGiulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto. iscas 2018: 1-5 [doi]
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino LogicMassimo Alioto, Gaetano Palumbo, Melita Pennisi. patmos 2009: 136-145 [doi]
A simple keeper topology to reduce delay variations in nanometer domino logicMassimo Alioto, Gaetano Palumbo, Melita Pennisi. iscas 2012: 1576-1579 [doi]
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoffMassimo Alioto, Stéphane Badel, Yusuf Leblebici. mj, 41(10):669-679, 2010. [doi]
Design of CML gate with the best propagation delayMassimo Alioto, Gaetano Palumbo. icecsys 1998: 287-290 [doi]
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk TechnologyMatteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi. tvlsi, 18(2):232-245, 2010. [doi]
STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and aboveMassimo Alioto. vlsi-dat 2017: 1 [doi]
Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nWLongyang Lin, Saurabh Jain, Massimo Alioto. vlsic 2019: 178 [doi]
Power-precision scalable latch memoriesDarjn Esposito, Antonio G. M. Strollo, Massimo Alioto. iscas 2017: 1-4 [doi]
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speedMassimo Alioto, Paolo Bennati, Roberto Giorgi. iscas 2010: 37-40 [doi]
F4: Electronics for a Quantum WorldEdoardo Charbon, Alicia Klinefelter, Massimo Alioto, Yao-Hong Liu, Munehiko Nagatani, Arijit Raychowdhury, Andreia Cathelin, Boris Murmann. isscc 2021: 525-528 [doi]
Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited ContributionsMassimo Alioto. tvlsi, 27(7):1485, 2019. [doi]
Modeling and evaluation of positive-feedback source-coupled logicMassimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli. tcas, 51-I(12):2345-2355, 2004. [doi]
Improving the power-delay product in SCL circuits using source follower output stageArmin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer. iscas 2008: 145-148 [doi]
On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated DesignHui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto. vlsit 2022: 140-141 [doi]
Delay uncertainty due to supply variations in static and dynamic full addersMassimo Alioto, Gaetano Palumbo. iscas 2006: [doi]
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic MapTommaso Addabbo, Massimo Alioto, Ada Fort, Antonio Pasini, Santina Rocchi, Valerio Vignoli. tcas, 54-I(4):816-828, 2007. [doi]
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural NetworksThi-Nhan Pham, Kien Trinh Quang, Ik Joon Chang, Massimo Alioto. iscas 2021: 1-5 [doi]
Energy-performance design exploration of a low-power microprogrammed deep-learning acceleratorGiulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto. date 2018: 1151-1154 [doi]
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain designMassimo Alioto, Elio Consoli, Gaetano Palumbo. ecctd 2009: 61-64 [doi]
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis AttacksMassimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli. iscas 2007: 861-864 [doi]
Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM MemoriesKien Trinh Quang, Sergio Ruocco, Massimo Alioto. tcas, 65-I(10):3338-3348, 2018. [doi]
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area TradeoffMassimo Alioto, Stéphane Badel, Yusuf Leblebici. iscas 2009: 1285-1288 [doi]
Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to SensemakingMassimo Alioto, Edgar Sánchez-Sinencio, Alberto L. Sangiovanni-Vincentelli. tcas, 64-I(9):2221-2225, 2017. [doi]
Optimized design of high fan-in multiplexers using switches with driving capabilityMassimo Alioto, Gaetano Palumbo. icecsys 2001: 737-740 [doi]
Architecture for 3D Convolutional Neural Networks Based on Temporal Similarity RemovalUdari De Alwis, Massimo Alioto. icecsys 2022: 1-4 [doi]
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural ProcessingSaurabh Jain, Longyang Lin, Massimo Alioto. jssc, 56(10):2981-2992, 2021. [doi]
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-FlopsMarco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto. icecsys 2019: 158-161 [doi]
Analysis and performance evaluation of area-efficient true random bit generators on FPGAsMassimo Alioto, Luca Fondelli, Santina Rocchi. iscas 2008: 1572-1575 [doi]
An Approach to Energy Consumption Modeling in RC Ladder CircuitsMassimo Alioto, Gaetano Palumbo, Massimo Poli. patmos 2002: 239-246 [doi]
Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage ScalingSaurabh Jain, Longyang Lin, Massimo Alioto. jssc, 53(2):632-641, 2018. [doi]
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuitsMassimo Alioto, Elio Consoli, Gaetano Palumbo, Melita Pennisi. ecctd 2009: 779-782 [doi]
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage ScalingFelice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann. tvlsi, 20(8):1487-1495, 2012. [doi]
Conversion Time-Power Tradeoff in Capacitance-to-Digital Converters with Dual-Mode LogicOrazio Aiello, Paolo Crovetti, Massimo Alioto. sbcci 2022: 1-5 [doi]
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi. integration, 63:273-274, 2018. [doi]
Energy-Quality Scalable Adders Based on Nonzeroing Bit TruncationFabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto. tvlsi, 27(4):964-968, 2019. [doi]
6.3 Imager with In-Sensor Event Detection and Morphological Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40nmJapesh Vohra, Animesh Gupta, Massimo Alioto. isscc 2024: 104-106 [doi]
Exploiting Hysteresys in MCML CircuitsMassimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli. tcas, 53-II(11):1170-1174, 2006. [doi]
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis AttacksViveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto. vlsit 2022: 144-145 [doi]
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nmAnimesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto. vlsit 2023: 1-2 [doi]
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced StacksDavide Baccarin, David Esseni, Massimo Alioto. tvlsi, 20(8):1467-1472, 2012. [doi]
Optimized design of parallel carry-select addersMassimo Alioto, Gaetano Palumbo, Massimo Poli. integration, 44(1):62-74, 2011. [doi]
Analysis and design of MCML gates with hysteresisMassimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli. iscas 2006: [doi]
Approximate SRAMs With Dynamic Energy-Quality ManagementFabio Frustaci, David Blaauw, Dennis Sylvester, Massimo Alioto. tvlsi, 24(6):2128-2141, 2016. [doi]
Temporal Redundancy-Based Computation Reduction for 3D Convolutional Neural NetworksUdari De Alwis, Massimo Alioto. aicas 2022: 86-89 [doi]
Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power EnvelopeLongyang Lin, Karim Ali Ahmed, Praveenakumar Shivappa Salamani, Massimo Alioto. vlsic 2021: 1-2 [doi]
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metricMassimo Alioto, Giuseppe Scotti, Alessandro Trifiletti. iscas 2017: 1-4 [doi]
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay SpaceMassimo Alioto, Elio Consoli, Gaetano Palumbo. tcas, 57-I(7):1583-1596, 2010. [doi]
Novel Simple Models Of Cml Propagation DelayMassimo Alioto, Gaetano Palumbo. glvlsi 1998: 270-274 [doi]
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct HarvestingPedro Toledo, Paolo Crovetti, Orazio Aiello, Massimo Alioto. tcasI, 68(9):3693-3706, 2021. [doi]
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOIMahmood Khayatzadeh, Mehdi Saligane, Jingcheng Wang, Massimo Alioto, David Blaauw, Dennis Sylvester. isscc 2016: 310-312 [doi]
Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution ScalingOrazio Aiello, Paolo Stefano Crovetti, Massimo Alioto. tcas, 66(8):2865-2875, 2019. [doi]
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic GatesGaetano Palumbo, Melita Pennisi, Massimo Alioto. tcas, 59-I(10):2292-2300, 2012. [doi]
Enabling Always-On Sensor Nodes Entirely Powered by Sustainable Energy Sources - Making Our World Smarter and GreenerMassimo Alioto. ifip5-5 2020: [doi]
Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffersLongyang Lin, Kien Trinh Quang, Massimo Alioto. iscas 2017: 1-4 [doi]
A 300mV-Supply, Sub-nW-Power Digital-Based Operational Transconductance AmplifierPedro Toledo, Paolo Crovetti, Hamilton Klimach, Sergio Bampi, Orazio Aiello, Massimo Alioto. tcasII, 68(9):3073-3077, 2021. [doi]
A gate-level strategy to design Carry Select AddersMassimo Alioto, Gaetano Palumbo, Massimo Poli. iscas 2004: 465-468
Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity DetectorJinq Horng Teo, Shuai Cheng, Massimo Alioto. icecsys 2019: 174-177 [doi]
Low-hardware complexity PRBGs based on a piecewise-linear chaotic mapTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. tcas, 53-II(5):329-333, 2006. [doi]
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOSMassimo Alioto, Elio Consoli, Jan M. Rabaey. cicc 2012: 1-4 [doi]
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-HoppingValentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto. vlsi 2017: 152-172 [doi]
STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural NetworksThi-Nhan Pham, Quang-Kien Trinh, Ik Joon Chang, Massimo Alioto. esticas, 12(2):569-579, 2022. [doi]
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic GatesMassimo Alioto, Gaetano Palumbo. patmos 2002: 429-437 [doi]
A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated SupplyOrazio Aiello, Paolo Crovetti, Massimo Alioto. vlsic 2018: 119-120 [doi]
Very high-speed carry computation based on mixed dynamic/transmission-gate Full AddersMassimo Alioto, Gaetano Palumbo. ecctd 2007: 799-802 [doi]
Energy consumption in RLC tree circuitsMassimo Alioto, Gaetano Palumbo, Massimo Poli. ecctd 2007: 771-774 [doi]
Modelling and design considerations on CML gates under high-current effectsMassimo Alioto, Gaetano Palumbo. ijcta, 33(6):503-518, 2005. [doi]
From energy-delay metrics to constraints on the design of digital circuitsMassimo Alioto, Elio Consoli, Gaetano Palumbo. ijcta, 40(8):815-834, 2012. [doi]
Power estimation in adiabatic circuits: a simple and accurate modelMassimo Alioto, Gaetano Palumbo. tvlsi, 9(5):608-615, 2001. [doi]
Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level ShufflingQiang Fang, Longyang Lin, Hui Zhang, Tianqi Wang, Massimo Alioto. vlsit 2023: 1-2 [doi]
Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMsKien Trinh Quang, Sergio Ruocco, Massimo Alioto. tcas, 65-I(4):1269-1278, 2018. [doi]
STT-MRAM write energy minimization via area optimization under dynamic voltage ScalingKien Trinh Quang, Sergio Ruocco, Massimo Alioto. iscas 2016: 2791-2794 [doi]
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 ProcessorYiqun Zhang 0002, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David Blaauw, Dennis Sylvester. jssc, 53(2):619-631, 2018. [doi]
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital CircuitsMassimo Alioto, David Esseni. sbcci 2014: 32 [doi]
Delay estimation of SCL gates with output bufferMassimo Alioto, Gaetano Palumbo, Salvatore Pennisi. icecsys 2001: 719-722 [doi]
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)Mike Shuo-Wei Chen, Visvesh S. Sathe 0001, Massimo Alioto, Jae-sun Seo, Hidehiro Shiga. jssc, 59(1):4-7, January 2024. [doi]
Session 36 Overview: Hardware Security Digital Architectures and Systems SubcommitteeHirofumi Shinohara, Massimo Alioto, Ingrid Verbauwhede. isscc 2021: 496-497 [doi]
Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested SystemsKarim Ali Ahmed, Longyang Lin, Praveenakumar Shivappa Salamani, Massimo Alioto. vlsit 2022: 50-51 [doi]
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic CircuitsMahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici. tcas, 62-I(2):458-467, 2015. [doi]
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technologyFabio Frustaci, Pasquale Corsonello, Massimo Alioto. iscas 2011: 2075-2078 [doi]
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video EncodingShifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas. acssc 2018: 251-255 [doi]
Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form AnalysisMassimo Alioto. tcas, 57-I(7):1597-1607, 2010. [doi]
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor FusionSachin Taneja, Massimo Alioto. jssc, 56(7):2182-2192, 2021. [doi]
Guest Editorial IEEE 2022 European Solid-State Circuits ConferenceMakoto Nagata, Massimo Alioto. jssc, 58(7):1823-1824, 2023. [doi]
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device LevelDavid Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, Massimo Alioto. tvlsi, 22(12):2488-2498, 2014. [doi]
TempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal DifferenceUdari De Alwis, Massimo Alioto. esticas, 11(4):620-633, 2021. [doi]
Voltage Scaled STT-MRAMs Towards Minimum-Energy Write AccessKien Trinh Quang, Sergio Ruocco, Massimo Alioto. esticas, 6(3):305-318, 2016. [doi]
Evaluation of energy consumption in RC ladder circuits driven by a ramp inputMassimo Alioto, Gaetano Palumbo, Massimo Poli. tvlsi, 12(10):1094-1107, 2004. [doi]
Power-Aware Design of Nanometer MCML Tapered BuffersMassimo Alioto, Gaetano Palumbo. tcas, 55-II(1):16-20, 2008. [doi]
EditorialKrishnendu Chakrabarty, Massimo Alioto, Rajiv V. Joshi. tvlsi, 25(9):2393, 2017. [doi]
Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performanceKien Trinh Quang, Sergio Ruocco, Massimo Alioto. iscas 2015: 2313-2316 [doi]
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOSFabio Frustaci, Mahmood Khayatzadeh, David Blaauw, Dennis Sylvester, Massimo Alioto. jssc, 50(5):1310-1323, 2015. [doi]
Super-Cutoff Analog Building Blocks for pW/Stage Operation and Demonstration of 78-pW Battery-Less Light-Harvested Wake-Up Receiver down to MoonlightJoydeep Basu, Luigi Fassio, Karim Ali, Massimo Alioto. vlsit 2023: 1-2 [doi]
Editorial on the Conclusion of the 2020 Editorial Year - The Climactic Finale of a Peculiar YearMassimo Alioto. tvlsi, 28(12):2479-2480, 2020. [doi]
2 in 40nmJinq Horng Teo, K. Ali, Massimo Alioto. asscc 2020: 1-3 [doi]
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES AlgorithmMassimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli. patmos 2006: 593-602 [doi]
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design PerspectivesMassimo Alioto, David Esseni. tvlsi, 22(12):2499-2512, 2014. [doi]
Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 VOrazio Aiello, Paolo Crovetti, Massimo Alioto. iscas 2018: 1-5 [doi]
Processor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In MethodologiesSaurabh Jain, Longyang Lin, Massimo Alioto. jssc, 55(10):2670-2679, 2020. [doi]
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green SystemsKarim Ali Ahmed, Ruiyuan Yang, Praveenakumar Shivappa Salamani, Viveka Konandur Rajanna, Massimo Alioto. esscirc 2023: 49-52 [doi]
Understanding Loading Effects of RC Uniform InterconnectsMassimo Alioto. iscas 2009: 2269-2272 [doi]
Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI SystemsMassimo Alioto. tvlsi, 30(1):1-4, 2022. [doi]
Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of ThingsOrazio Aiello, Paolo Crovetti, Massimo Alioto. icecsys 2019: 105-106 [doi]
Analysis and comparison of low-voltage CML D-latchMassimo Alioto, Rosario Mita, Gaetano Palumbo. icecsys 2002: 737-740 [doi]
Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine LearningJinq Horng Teo, Shuai Cheng, Massimo Alioto. tcas, 67-I(4):1378-1388, 2020. [doi]
2 and 749-1, 459 TOPS/W in 28nmViveka Konandur Rajanna, Sachin Taneja, Massimo Alioto. esscirc 2021: 127-130 [doi]
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nmJoydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto. vlsit 2023: 1-2 [doi]
Analysis and Modeling of Energy Consumption in RLC Tree CircuitsMassimo Alioto, Gaetano Palumbo, Massimo Poli. tvlsi, 17(2):278, 2009. [doi]
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full AddersMassimo Alioto, Gaetano Palumbo. icecsys 2006: 518-521 [doi]
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level ShifterLuigi Fassio, Francesco Settino, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto. tcasII, 68(4):1393-1397, 2021. [doi]
Power-delay trade-offs in SCL gatesMassimo Alioto, Gaetano Palumbo. iscas 2002: 249-252 [doi]
Fully Synthesizable Unified True Random Number Generator and Cryptographic CoreSachin Taneja, Massimo Alioto. jssc, 56(10):3049-3061, 2021. [doi]
Efficient and Accurate Models of Output Transition Time in CMOS LogicMassimo Alioto, Massimo Poli, Gaetano Palumbo. icecsys 2007: 1264-1267 [doi]
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design StrategiesMassimo Alioto, Elio Consoli, Gaetano Palumbo. tvlsi, 19(5):725-736, 2011. [doi]
Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage RegulationOrazio Aiello, Paolo Crovetti, Massimo Alioto. isscc 2021: 74-76 [doi]
2 per Receptor for Scaling to Human-Like Tactile Sensing DensityPrachi Agarwal, Viveka Konandur Rajanna, Toh Wei Da, Benjamin C. K. Tee, Massimo Alioto. vlsic 2021: 1-2 [doi]
Reconfigurable Clock Networks for Wide Voltage ScalingLongyang Lin, Saurabh Jain, Massimo Alioto. jssc, 54(9):2622-2631, 2019. [doi]
Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct HarvestingOrazio Aiello, Massimo Alioto. esscirc 2022: 381-384 [doi]
A feedback strategy to improve the entropy of a chaos-based random bit generatorTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. tcas, 53(2):326-337, 2006. [doi]
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryptionWenfeng Zhao, Yajun Ha, Massimo Alioto. iscas 2015: 2349-2352 [doi]
Design of Fast Large Fan-In CMOS Multiplexers Accounting for InterconnectsMassimo Alioto, Gaetano Palumbo. iscas 2007: 3255-3258 [doi]
Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-BasedMassimo Alioto, Vivek De, Andrea Marongiu. esticas, 8(3):361-368, 2018. [doi]
Modelling of source-coupled logic gatesMassimo Alioto, Gaetano Palumbo, Salvatore Pennisi. ijcta, 30(4):459-477, 2002. [doi]
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensingLongyang Lin, Saurabh Jain, Massimo Alioto. isscc 2018: 44-46 [doi]
Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode LogicMassimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli. tcas, 54-I(9):1916-1928, 2007. [doi]
Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuitsMassimo Alioto. iscas 2010: 1468-1471 [doi]
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logicMassimo Alioto. icecsys 2007: 431-434 [doi]
26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltageLongyang Lin, Saurabh Jain, Massimo Alioto. isscc 2017: 440-441 [doi]
A General Power Model of Differential Power Analysis Attacks to Static Logic CircuitsMassimo Alioto, Massimo Poli, Santina Rocchi. tvlsi, 18(5):711-724, 2010. [doi]
Efficient output transition time modeling in CMOS gates with ramp/exponential inputsMassimo Alioto, Gaetano Palumbo, Massimo Poli. iscas 2006: [doi]
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuitsPaolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer. iscas 2010: 1699-1702 [doi]
A 0.4V 12b Comparator Offset Injection Assisted SAR ADC achieving 0.425 fJ/conv-stepJapesh Vohra, Karim Ali Ahmed, Massimo Alioto. esscirc 2023: 137-140 [doi]
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillatorsMahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici. iscas 2015: 157-160 [doi]
Energy evaluation in RLC tree circuits with exponential inputMassimo Alioto, Gaetano Palumbo, Massimo Poli. icecsys 2008: 578-581 [doi]
PVT variations in differential flip-flops: A comparative analysisMassimo Alioto, Gaetano Palumbo, Elio Consoli. ecctd 2015: 1-4 [doi]
Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nWLongyang Lin, Saurabh Jain, Massimo Alioto. jssc, 55(4):967-976, 2020. [doi]
2 and 749-1, 459 TOPS/W in 28nmViveka Konandur Rajanna, Sachin Taneja, Massimo Alioto. essderc 2021: 127-130 [doi]
Design guidelines for bipolar frequency dividersMassimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo. icecsys 2002: 521-524 [doi]
A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic AlgorithmsMassimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli. ecctd 2007: 368-371 [doi]
Standard Cell-Based Ultra-Compact DACs in 40-nm CMOSOrazio Aiello, Paolo Crovetti, Massimo Alioto. access, 7:126479-126488, 2019. [doi]
A general model for differential power analysis attacks to static logic circuitsMassimo Alioto, Massimo Poli, Santina Rocchi. iscas 2008: 3346-3349 [doi]
Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systemsSuyoung Bang, David Blaauw, Dennis Sylvester, Massimo Alioto. cicc 2012: 1-4 [doi]
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar, editors, IEEE, 2017. [doi]
Boosted sensing for enhanced read stability in STT-MRAMsKien Trinh Quang, Sergio Ruocco, Massimo Alioto. iscas 2016: 1238-1241 [doi]
Design techniques for low-power cascaded CML gatesMassimo Alioto, Gaetano Palumbo. iscas 2005: 4685-4688 [doi]
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variationsMilena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto. iscas 2011: 2043-2046 [doi]
29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016Karan S. Bhatia, Massimo Alioto, Danella Zhao, Andrew Marshall, Ramalingam Sridhar, editors, IEEE, 2016. [doi]
An efficient implementation of PRNGs based on the digital sawtooth mapMassimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli. ijcta, 32(6):615-627, 2004. [doi]
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental MeasurementsPaolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer, Brice De Jaeger. tvlsi, 19(9):1569-1582, 2011. [doi]
Active RFID: Perpetual wireless communications platform for sensorsJesse Richmond, Mervin John, Louis P. Alarcón, Wenting Zhou, Wen Li, Tsung-Te Liu, Massimo Alioto, Seth Sanders, Jan M. Rabaey. esscirc 2012: 434-437 [doi]
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and ComparisonMassimo Alioto, Gaetano Palumbo. tvlsi, 14(12):1322-1335, 2006. [doi]
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nmSachin Taneja, Anastacia B. Alvarez, Massimo Alioto. jssc, 53(10):2828-2839, 2018. [doi]
Ultra-low voltage standard cell libraries: Design strategies and a case studySomayeh Timarchi, Massimo Alioto. icecsys 2016: 520-523 [doi]
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffersFabio Frustaci, Pasquale Corsonello, Massimo Alioto. ecctd 2011: 592-595 [doi]
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed LatchesElio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto. tvlsi, 22(7):1593-1605, 2014. [doi]
Nanometer MCML gates: models and design considerationsMassimo Alioto, Gaetano Palumbo. iscas 2006: [doi]
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On OperationJoydeep Basu, Luigi Fassio, Karim Ali 0004, Massimo Alioto. jssc, 59(4):1038-1049, April 2024. [doi]
A 0.6-to-1.8V CMOS Current Reference With Near-100% Power UtilizationLuigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto. tcasII, 68(9):3038-3042, 2021. [doi]
Highly accurate and simple models for CML and ECL gatesMassimo Alioto, Gaetano Palumbo. tcad, 18(9):1369-1375, 1999. [doi]
Opening of the 2023 Editorial Year - This Coda as Prelude of Next TVLSI Cycle With Sustained GrowthMassimo Alioto. tvlsi, 31(1):1-3, 2023. [doi]
Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD ScalingSaurabh Jain, Longyang Lin, Massimo Alioto. asscc 2019: 125-128 [doi]
Editorial TVLSI Positioning - Continuing and Accelerating an Upward TrajectoryMassimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han 0001, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber. tvlsi, 27(2):253-280, 2019. [doi]
Hardware-efficient PRBGs based on 1-D piecewise linear chaotic mapsTommaso Addabbo, Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli. icecsys 2004: 242-245 [doi]
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOSElio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey. isscc 2012: 482-484 [doi]
2 Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less SystemsLuigi Fassio, Orazio Aiello, Massimo Alioto. vlsit 2023: 1-2 [doi]
An approach to the design of PFSCL gatesMassimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli. iscas 2005: 2437-2440 [doi]
Positive-Feedback Source-Coupled Logic: a delay modelMassimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli. iscas 2004: 641-644
Interconnect-Aware Design of Fast Large Fan-In CMOS MultiplexersMassimo Alioto, Gaetano Palumbo. tcas, 54-II(6):484-488, 2007. [doi]
Energy Consumption in RC Tree CircuitsMassimo Alioto, Gaetano Palumbo, Massimo Poli. tvlsi, 14(5):452-461, 2006. [doi]
45pW ESD clamp circuit for ultra-low power applicationsYen-Po Chen, Yoonmyung Lee, Jae-Yoon Sim, Massimo Alioto, David Blaauw, Dennis Sylvester. cicc 2013: 1-4 [doi]
Power-delay optimization of D-latch/MUX source coupled logic gatesMassimo Alioto, Gaetano Palumbo. ijcta, 33(1):65-86, 2005. [doi]
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware SecuritySachin Taneja, Viveka Konandur Rajanna, Massimo Alioto. isscc 2021: 498-500 [doi]
Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic AlgorithmsMassimo Alioto, Massimo Poli, Santina Rocchi. tdsc, 7(3):226-239, 2010. [doi]
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical ModelMassimo Alioto, Gaetano Palumbo, Massimo Poli. patmos 2005: 355-363 [doi]
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video ResolutionShifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto. asscc 2021: 1-3 [doi]
Analysis and comparison on full adder block in submicron technologyMassimo Alioto, Gaetano Palumbo. tvlsi, 10(6):806-823, 2002. [doi]
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device MeasurementsFelice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, M. Togo, N. Horiguchi, Guido Groeseneken. tcas, 59-II(7):439-442, 2012. [doi]
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning ApplicationsViveka Konandur Rajanna, Massimo Alioto. jssc, 56(11):3533-3543, 2021. [doi]
Techniques to Enhance the Resistance of Precharged Busses to Differential Power AnalysisMassimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli. patmos 2006: 624-633 [doi]
Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's LawMassimo Alioto, Vivek De, Andrea Marongiu. esticas, 8(4):653-678, 2018. [doi]
A Design Methodology for High-Speed Low-Power MCML Frequency DividersMassimo Alioto, Rosario Mita, Gaetano Palumbo. icecsys 2006: 1308-1311 [doi]
High-speed bipolar MUX modeling and designMassimo Alioto, Gaetano Palumbo. iscas 2000: 1-4 [doi]
Ultra-low power design approaches for IoTMassimo Alioto. hotchips 2014: 1-57 [doi]
Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated DesignHui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto. jssc, 58(10):2919-2930, October 2023. [doi]
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuseFabio Frustaci, David Blaauw, Dennis Sylvester, Massimo Alioto. patmos 2015: 132-139 [doi]
New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyondBozena Kaminska, Bernard Courtois, Bernard Courtois, Massimo Alioto. vts 2013: 1 [doi]
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware SecuritySachin Taneja, Viveka Konandur Rajanna, Massimo Alioto. jssc, 57(1):153-166, 2022. [doi]
Performance evaluation of the low-voltage CML D-latch topologyMassimo Alioto, Rosario Mita, Gaetano Palumbo. integration, 36(4):191-209, 2003. [doi]
Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green ComputingMassimo Alioto. tcas, 59-II(12):849-852, 2012. [doi]
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient ApplicationsViveka Konandur Rajanna, Massimo Alioto. cicc 2019: 1-4 [doi]
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network DesignMassimo Alioto, Elio Consoli, Gaetano Palumbo. tcas, 57-I(6):1273-1286, 2010. [doi]
Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight HarvestingLongyang Lin, Saurabh Jain, Massimo Alioto. vlsic 2020: 1-2 [doi]
Rail-to-Rail Dynamic Voltage Comparator Scalable Down to pW-Range Power and 0.15-V SupplyOrazio Aiello, Paolo Crovetti, Pedro Toledo, Massimo Alioto. tcasII, 68(7):2675-2679, 2021. [doi]
From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWsMassimo Alioto. esscirc 2022: 33-40 [doi]
Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cellsMassimo Alioto. ecctd 2011: 536-539 [doi]
Leakage Power Analysis attacks: Theoretical analysis and impact of variationsMassimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti. icecsys 2009: 85-88 [doi]
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional MapTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. iscas 2007: 693-696 [doi]
Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nmSachin Taneja, Massimo Alioto. iscas 2020: 1-5 [doi]
Circuits and Architectures for Next-generation Attentive & Intelligent SystemsMassimo Alioto. vlsi-dat 2022: 1 [doi]
The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom BitsTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. tim, 55(5):1451-1458, 2006. [doi]
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuitsDavid Esseni, Massimo Alioto. newcas 2014: 321-324 [doi]
2 area in 40nm CMOSAnastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto. asscc 2017: 241-244 [doi]
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of MeritMassimo Alioto, Elio Consoli, Gaetano Palumbo. tvlsi, 19(5):737-750, 2011. [doi]
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 VLuigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto. access, 11:3584-3596, 2023. [doi]
Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage RegulationOrazio Aiello, Paolo Stefano Crovetti, Massimo Alioto. tcasI, 70(4):1439-1449, April 2023. [doi]
Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security PatchingQiang Fang, Longyang Lin, Yao Zu Wong, Hui Zhang, Massimo Alioto. isscc 2022: 1-3 [doi]
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage ScalingSaurabh Jain, Longyang Lin, Massimo Alioto. tvlsi, 28(3):777-790, 2020. [doi]
Design metrics for RTL level estimation of delay variability due to intradie (random) variationsMichael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto. iscas 2010: 2498-2501 [doi]
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processorYiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David Blaauw, Dennis Sylvester. isscc 2016: 160-162 [doi]
Long period pseudo random bit generators derived from a discretized chaotic mapTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. iscas 2005: 892-895 [doi]
Novel Time-Based Sensing Scheme for STT-MRAMsKien Trinh Quang, Sergio Ruocco, Massimo Alioto. iscas 2018: 1-5 [doi]
Variability budgetin pulsed flip-flopsMassimo Alioto, Gaetano Palumbo, Elio Consoli. newcas 2015: 1-4 [doi]
A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nmLuigi Fassio, Hoang Hong Hanh, Massimo Alioto. asscc 2023: 1-3 [doi]
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nmAnastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto. jssc, 51(3):763-775, 2016. [doi]
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI CircuitsMassimo Alioto, Elio Consoli, Gaetano Palumbo. patmos 2011: 62-72 [doi]
Simple and accurate modeling of the output transition time in nanometer CMOS gatesMassimo Alioto, Gaetano Palumbo, Massimo Poli. ijcta, 38(10):995-1012, 2010. [doi]
Modeling strategies of the input admittance of RC interconnects for VLSI CAD toolsMassimo Alioto. mj, 42(1):63-73, 2011. [doi]
PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor FusionSachin Taneja, Massimo Alioto. esscirc 2019: 61-64 [doi]
Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM ReadKien Trinh Quang, Sergio Ruocco, Massimo Alioto. tcas, 63-I(10):1652-1660, 2016. [doi]
Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy PointSaurabh Jain, Longyang Lin, Massimo Alioto. tcas, 64(12):3115-3125, 2017. [doi]
Temporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera NodesUdari De Alwis, Zhongheng Xie, Massimo Alioto. aicas 2023: 1-5 [doi]
Analysis and Design of Ultra-low Power Subthreshold MCML GatesMassimo Alioto, Yusuf Leblebici. iscas 2009: 2557-2560 [doi]
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOSFabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto. isscc 2014: 244-245 [doi]
Enabling sizing for enhancing the static noise marginsValeriu Beiu, Azam Beg, Walid Ibrahim, Fekri Kharbash, Massimo Alioto. isqed 2013: 278-285 [doi]
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOSLaura Fick, David Fick, Massimo Alioto, David Blaauw, Dennis Sylvester. jssc, 49(11):2462-2473, 2014. [doi]
Token-Based Security for the Internet of Things With Dynamic Energy-Quality TradeoffMuhammad Naveed Aman, Sachin Taneja, Biplab Sikdar, Kee Chaing Chua, Massimo Alioto. iotj, 6(2):2843-2859, 2019. [doi]
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality DegradationFabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto. tcas, 67-II(12):3427-3431, 2020. [doi]
Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse ModulationOrazio Aiello, Paolo Crovetti, Massimo Alioto. access, 8:70890-70899, 2020. [doi]
Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression LogicOrazio Aiello, Paolo Crovetti, Massimo Alioto. iscas 2019: 1-5 [doi]
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of VariationsMassimo Alioto, Elio Consoli, Gaetano Palumbo. tcas, 62-I(3):835-843, 2015. [doi]
Tapered-Vth Approach for Energy-Efficient CMOS BuffersFabio Frustaci, Massimo Alioto, Pasquale Corsonello. tcas, 58-I(11):2698-2707, 2011. [doi]
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case StudyWenfeng Zhao, Yajun Ha, Massimo Alioto. tvlsi, 23(8):1390-1401, 2015. [doi]
Understanding the Effect of Process Variations on the Delay of Static and Domino LogicMassimo Alioto, Gaetano Palumbo, Melita Pennisi. tvlsi, 18(5):697-710, 2010. [doi]
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard CellsMassimo Alioto. tvlsi, 19(5):751-762, 2011. [doi]
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nmAnastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto. isscc 2015: 1-3 [doi]
A variation-aware simulation framework for hybrid CMOS/spintronic circuitsRaffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto. iscas 2017: 1-4 [doi]
Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor NodesLongyang Lin, Saurabh Jain, Massimo Alioto. jssc, 56(5):1618-1629, 2021. [doi]
A closed-form energy model for VLSI circuits under wide voltage scalingSaurabh Jain, Massimo Alioto. icecsys 2016: 548-551 [doi]
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total AccuracyLuigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto. esscirc 2021: 343-346 [doi]
Optimum clock slope for flip-flops within a clock domain: Analysis and a case studyMassimo Alioto, Elio Consoli, Gaetano Palumbo. icecsys 2009: 275-278 [doi]
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOSMahmood Khayatzadeh, Fabio Frustaci, David Blaauw, Dennis Sylvester, Massimo Alioto. vlsic 2015: 270 [doi]
Design of MUX, XOR and D-latch SCL gatesMassimo Alioto, Gaetano Palumbo. iscas 2003: 261-264 [doi]
Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy GatesMihai Tache, Valeriu Beiu, Walid Ibrahim, Fekri Kharbash, Massimo Alioto. jolpe, 10(1):137-148, 2014. [doi]
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pWLuigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto. jssc, 56(10):3134-3144, 2021. [doi]
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiencyMassimo Alioto, Elio Consoli, Gaetano Palumbo. iscas 2010: 321-324 [doi]
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic CircuitsArmin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici. patmos 2009: 21-30 [doi]
Editorial First TVLSI Best AE and Reviewer AwardsKrishnendu Chakrabarty, Massimo Alioto. tvlsi, 24(8):2613, 2016. [doi]
Analysis of the impact of random process variations in CMOS tapered buffersMassimo Alioto, Gaetano Palumbo, Melita Pennisi. icecsys 2009: 57-60 [doi]

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